CN114911647A - Polynomial configurable parallel CRC hardware implementation method, device and computer equipment - Google Patents

Abstract

The application relates to a polynomial configurable parallel CRC hardware implementation method, a device, computer equipment and a storage medium, wherein the method comprises the following steps: acquiring a parallel CRC hardware implementation request with a configurable polynomial; generating a CRC check matrix parameter according to a CRC generator polynomial in a protocol and the requirement of parallelism of hardware processing data; the generated CRC check matrix parameters are adapted to a check matrix cache region of a CRC calculation unit in a hardware circuit through a software and hardware interaction interface; and a CRC calculation unit in the hardware circuit performs iterative calculation according to the input data and the check matrix parameters to generate a CRC result. The invention effectively improves the flexibility of CRC hardware and removes the limitation of a single polynomial in a parallel CRC hardware circuit.

Description

Polynomial configurable parallel CRC hardware implementation method, device and computer equipment

technical field

The present invention relates to the technical field of solid-state hard disks, and in particular, to a method, device, computer equipment and storage medium for implementing a polynomially configurable parallel CRC hardware.

Background technique

Cyclic Redundancy Check (CRC) is a channel coding technology that generates a short, fixed-digit check code based on data such as network packets or computer files. It is mainly used to detect or verify data transmission or storage. possible errors later. The CRC algorithm has strong error detection ability and low detection cost, and has become the most common verification method in the fields of solid-state storage and computer information communication.

At present, the realization of the existing parallel CRC in the hardware circuit is realized according to different classifications of each CRC generator polynomial. For the generator polynomial of the same CRC, a hardware circuit is implemented, and the CRC of different generator polynomials is implemented using different digital circuits. This method can basically meet the needs of the application in a single communication protocol. However, when the product becomes complicated and the types of the adapted communication protocols increase, the hardware needs to be customized again to generate a parallel CRC hardware circuit according to the CRC generator polynomial in the protocol. This method leads to poor adaptability of the implemented CRC hardware circuit in different application scenarios, which limits the application of the product.

SUMMARY OF THE INVENTION

Based on this, it is necessary to provide a polynomially configurable parallel CRC hardware implementation method, apparatus, computer device and storage medium that can improve the read performance of the SSD, aiming at the above technical problems.

A polynomial configurable parallel CRC hardware implementation method, the method comprising:

Get a polynomial configurable parallel CRC hardware implementation request;

Generate CRC check matrix parameters according to the requirements of the CRC generation polynomial in the protocol and the parallelism of the hardware processing data;

The generated described CRC check matrix parameter is adapted to the check matrix buffer area of the CRC calculation unit in the hardware circuit through the software-hardware interactive interface;

The CRC calculation unit in the hardware circuit performs iterative calculation according to the input data and the check matrix parameters to generate a CRC result.

In one of the embodiments, the step of generating the CRC check matrix parameter according to the CRC generator polynomial in the protocol and the parallelism of the hardware processing data further includes:

Determine the CRC generator polynomial g(x) and the degree of parallelism n;

The corresponding CRC coefficient matrix and CRC data matrix are respectively generated by the CRC coefficient matrix generator and the CRC data matrix generator;

The CRC coefficient matrix and the CRC data matrix are combined to obtain a CRC check matrix.

In one of the embodiments, the step of generating the corresponding CRC coefficient matrix and the CRC data matrix by the CRC coefficient matrix generator and the CRC data matrix generator, respectively, further comprises:

A sparse matrix is constructed according to the CRC generator polynomial g(x), and the CRC coefficient matrix is generated by performing n-1 linear transformations on the sparse matrix.

In one of the embodiments, the step of the CRC calculation unit in the hardware circuit performing iterative calculation according to the input data and the check matrix parameters to generate the CRC result further includes:

The kbit data in the data buffer area and the CRC check matrix buffer area are processed according to the row direction of the check matrix to generate m intermediate values respectively;

The row direction processing is to perform a bitwise AND operation on the kbit data in the data buffer area and the single row kbit data in the CRC check matrix to generate an intermediate value;

The m intermediate values are respectively carried out bitwise XOR operation to generate the CRC update value of m bit;

When the input nbit data is the last group, the corresponding generated CRC update value is stabilized by the mbit D flip-flop as the output result of the CRC.

A polynomial configurable parallel CRC hardware implementation device, the device comprising:

an acquisition module, which is used to acquire a polynomial configurable parallel CRC hardware implementation request;

A generation module, the generation module is used to generate a CRC check matrix parameter according to the requirement of the parallelism of the CRC generator polynomial in the protocol and the hardware processing data;

an adaptation module, the adaptation module is used to adapt the generated described CRC check matrix parameters to the check matrix buffer area of the CRC calculation unit in the hardware circuit through a software-hardware interactive interface;

A calculation module, the calculation module is configured to generate a CRC result by iterative calculation according to the input data and the check matrix parameters by the CRC calculation unit in the hardware circuit.

In one of the embodiments, the generating module is further used for:

Determine the CRC generator polynomial g(x) and the degree of parallelism n;

The corresponding CRC coefficient matrix and CRC data matrix are respectively generated by the CRC coefficient matrix generator and the CRC data matrix generator;

The CRC coefficient matrix and the CRC data matrix are combined to obtain a CRC check matrix.

In one of the embodiments, the generating module is further used for:

A sparse matrix is constructed according to the CRC generator polynomial g(x), and the CRC coefficient matrix is generated by performing n-1 linear transformations on the sparse matrix.

In one embodiment, the computing module is further used for:

The kbit data in the data buffer area and the CRC check matrix buffer area are processed according to the row direction of the check matrix to generate m intermediate values respectively;

The row direction processing is to perform a bitwise AND operation on the kbit data in the data buffer area and the single row kbit data in the CRC check matrix to generate an intermediate value;

The m intermediate values are respectively carried out bitwise XOR operation to generate the CRC update value of m bit;

When the input nbit data is the last group, the corresponding generated CRC update value is stabilized by the mbit D flip-flop as the output result of the CRC.

A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of any one of the above methods when the processor executes the computer program.

A computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the steps of any one of the above-mentioned methods.

The above-mentioned polynomial configurable parallel CRC hardware implementation method, device, computer equipment and storage medium, through the software, the check matrix parameters generated by the adaptation are transferred to the check matrix of the hardware CRC calculation unit, and then passed the hardware CRC with the input data. The calculation unit generates check redundancy codes through iterative calculation, and uses multiple sets of check array parameters to correspond to multiple sets of CRC generator polynomials and the parallelism of the input data, thereby effectively improving the flexibility of the CRC hardware and eliminating the need for parallel CRC hardware circuits. Limitations to single polynomials.

Description of drawings

1 is a schematic flowchart of a polynomial-configurable parallel CRC hardware implementation method in one embodiment;

Fig. 2 is a structural block diagram of a parallel CRC software and hardware adaptation that polynomials can be configured to in one embodiment;

3 is a schematic flowchart of a polynomial-configurable parallel CRC hardware implementation method in another embodiment;

4 is a schematic diagram of the relationship between a CRC check matrix, a CRC coefficient matrix, and a CRC data matrix in one embodiment;

5 is a schematic flowchart of a method for implementing a parallel CRC hardware with a polynomial configurable in another embodiment;

6 is a circuit diagram of a CRC calculation unit in a parallel CRC hardware circuit with a polynomial configurable in one embodiment;

7 is a structural block diagram of a polynomial-configurable parallel CRC hardware implementation device in one embodiment;

FIG. 8 is a diagram of the internal structure of a computer device in one embodiment.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

At present, the realization of the existing parallel CRC in the hardware circuit is realized according to different classifications of each CRC generator polynomial. For the generator polynomial of the same CRC, a hardware circuit is implemented, and the CRC of different generator polynomials is implemented using different digital circuits. This method can basically meet the needs of the application in a single communication protocol. However, when the product becomes complicated and the types of the adapted communication protocols increase, the hardware needs to be customized again to generate a parallel CRC hardware circuit according to the CRC generator polynomial in the protocol. This method leads to poor adaptability of the implemented CRC hardware circuit in different application scenarios, which limits the application of the product.

Based on this, the present invention proposes a polynomial-configurable parallel CRC hardware implementation method and device, which aims to relieve the limitation of a single polynomial in the parallel CRC hardware circuit.

In one embodiment, as shown in FIG. 1, a polynomial configurable parallel CRC hardware implementation method is provided, and the method includes:

Step 102, obtain a polynomial configurable parallel CRC hardware implementation request;

Step 104, generate the CRC check matrix parameter according to the requirement of the parallelism of the CRC generator polynomial in the protocol and the hardware processing data;

Step 106, the generated CRC check matrix parameter is adapted to the check matrix buffer area of the CRC calculation unit in the hardware circuit through the software-hardware interactive interface;

Step 108, the CRC calculation unit in the hardware circuit performs iterative calculation according to the input data and the check matrix parameters to generate a CRC result.

The present invention provides a polynomial configurable parallel CRC hardware implementation method, which can be applied to the polynomial configurable parallel CRC hardware and software adaptation structure as shown in FIG. 2 .

Specifically, the polynomial configurable parallel CRC software and hardware adaptation structure is mainly composed of a generation check matrix unit, a configuration unit and a CRC calculation unit. Wherein, the check matrix generating unit generates the check matrix parameters to be adapted by the software according to the requirements of the polynomial and the input data parallelism. The configuration unit adapts the parity check matrix parameters to be adapted into the parity check matrix of the CRC calculation unit through the software. The CRC calculation unit generates the CRC result by iterative calculation according to the check matrix and the input data by hardware. The hardware device improves flexibility on the basis of ensuring parallel processing, and can adapt to multiple sets of generator polynomials.

For example: take CRC-5, the generator polynomial g(x)=x5+x2+1, the parallelism of the hardware processing data n=13, and the input data 13'h1F as an example, the operation steps are as follows:

First, the software generates a CRC check matrix according to the requirements of the CRC generator polynomial and parallelism. The results are as follows:

Then, the software adapts the check matrix parameters to be adapted to the check matrix buffer area in the CRC calculation unit in the hardware circuit through the software-hardware interactive interface.

Finally, the hardware circuit operates on the input data to generate a CRC result: 5'h14.

In this embodiment, the check matrix parameters generated by adaptation are transferred to the check matrix of the hardware CRC calculation unit through software, and then the check redundancy code is generated by iterative calculation with the input data through the hardware CRC calculation unit. Multiple sets of check array parameters correspond to multiple sets of CRC generator polynomials and input data parallelism, which effectively improves the flexibility of CRC hardware and relieves the limitation of a single polynomial in parallel CRC hardware circuits.

In one embodiment, as shown in FIG. 3 , a polynomial-configurable parallel CRC hardware implementation method is provided. In the method, a CRC check matrix is generated according to the CRC generator polynomial in the protocol and the parallelism of hardware processing data. The parameter steps also include:

Step 302, determine the CRC generator polynomial g(x) and the degree of parallelism n;

Step 304, generate corresponding CRC coefficient matrix and CRC data matrix respectively by CRC coefficient matrix generator and CRC data matrix generator;

Step 306, combining the CRC coefficient matrix and the CRC data matrix to obtain a CRC check matrix.

In one embodiment, the step of generating the corresponding CRC coefficient matrix and the CRC data matrix by the CRC coefficient matrix generator and the CRC data matrix generator, respectively, further includes: constructing a sparse matrix according to the CRC generator polynomial g(x), After the matrix is linearly transformed for n-1 times, the CRC coefficient matrix is generated.

Specifically, reference may be made to the polynomially configurable parallel CRC software and hardware adaptation structure shown in FIG. 2 , where the CRC check matrix generator mainly includes: a CRC coefficient matrix generator and a CRC data matrix generator. When the CRC generating polynomial g(x) and the degree of parallelism n are determined, the corresponding CRC coefficient matrix and CRC data matrix are respectively generated by the above two generators; the two are combined to obtain the CRC check matrix.

The CRC coefficient matrix generator mainly generates the CRC coefficient matrix according to the CRC generating polynomial g(x) and the parallelism n of the hardware processing data after operation processing. The processing process mainly includes two steps: 1. Constructing a sparse matrix according to the generator polynomial g(x); 2. Converting the sparse matrix n-1 times to generate a CRC coefficient matrix.

For example, the form of selecting the CRC generator polynomial g(x) is as shown in Equation 1:

Wherein c _k =1 indicates that the circuit is connected, otherwise it indicates disconnection; x ^k indicates the value of the kth register D _k ; c ₀ = _cm =1.

Step 1: Construct a sparse matrix T ⁽¹⁾ , see formula 2 for the reference form;

c_m＝c₀＝1；E为m×m的单位矩阵；

为零向量；Wherein "1" in T ⁽¹⁾ represents the first shift;

c _m =c ₀ =1; E is the identity matrix of m×m;

zero vector;

Step 2: After n-1 transformations, generate a CRC coefficient matrix, and each transformation follows L ₂ linear transformation - T ⁽ⁿ⁾ = L ₂ (T ^(n-1) )

等同于CRC系数矩阵中的元素。Denote the i-th row, j-th column, and the elements in the state matrix corresponding to the n transformations in T ⁽ⁿ⁾ as

Equivalent to the elements in the CRC coefficient matrix.

L2 operates as follows: the elements in the row vector of the _1st to m-1 rows of T ⁽ⁿ⁾ are updated according to formula 3; the elements in the row vector of the mth row are updated according to formula 4;

The CRC data matrix generator mainly takes the first column elements from the n state matrices {T(1), T(2), ..., T(n)}, and then generates the CRC data matrix (CD, where the number of rows is m, the number of columns is n), as shown in Equation 5.

Finally, the CRC coefficient matrix and the CRC data matrix are combined to obtain a CRC check matrix. Specifically, referring to FIG. 4 , m in FIG. 4 represents the number of stages of the CRC generator polynomial g(x), for example, CRC-16, corresponding to m is 16; CRC-32, corresponding to m is 32. n represents the parallelism of the input data, which mainly refers to the bit width (bit level) of the input data in the hardware circuit. For example, when the bit width of the input data is 32 bits, the corresponding n is 32; when the bit width of the input data is 128 bits, the corresponding n is 128.

It should be noted that the relationship between the CRC coefficient matrix and the CRC data matrix in FIG. 4 supports modification schemes such as swapping and crossover, and this scheme is also applicable to other modification schemes.

In one embodiment, as shown in FIG. 5 , a polynomial configurable parallel CRC hardware implementation method is provided, in which the CRC calculation unit in the hardware circuit performs iterative calculation according to the input data and the check matrix parameters to generate the CRC The resulting steps also include:

Step 502, processing the kbit data in the data buffer area and the CRC check matrix buffer area according to the row direction of the check matrix to generate m intermediate values respectively;

Step 504, the row direction processing is to perform bitwise AND operation on the kbit data in the data buffer area and the single row kbit data in the CRC check matrix to generate an intermediate value;

Step 506, respectively carry out bitwise XOR operation to m intermediate values to generate the CRC update value of m bit;

Step 508, when the input n-bit data is the last group, the corresponding generated CRC update value is stabilized by the m-bit D flip-flop as the output result of the CRC.

Referring to the circuit diagram of the CRC calculation unit in the polynomially configurable parallel CRC hardware circuit shown in FIG. 6 , in this embodiment, the CRC calculation unit mainly converts the data received at the input interface to generate an m-bit CRC result.

The main operation process is described as follows: the kbit data in the data buffer area (composed of mbit CRC update value and nbit input data, k=m+n) and the CRC check matrix buffer area are processed according to the row direction of the check matrix, Generate m intermediate values (tmp0, tmp1...tmpm-1) respectively; each row is processed by performing a bitwise AND "&" operation between the kbit data in the data buffer and the single row of kbit data in the CRC check matrix to generate an intermediate value ; Then perform bitwise exclusive-OR "XOR" operation on m intermediate values to generate m-bit CRC update value (composed of {CNm-1, ..., CN1, CN0}); when the input nbit data is the last group , corresponding to the generated CRC update value, after the m bit D flip-flop (Dm) is stabilized, it is used as the output result of the CRC.

There are two data sources for the CRC update value in the data buffer: when the data just starts to transmit, corresponding to the first group of data, it comes from the initial value (DI, generally set to all '1') in the D flip-flop; otherwise , which is derived from the CRC update value stabilized by the D flip-flop.

It is worth noting that when the data in the data buffer area in the CRC calculation unit in Figure 6 and the data in the CRC check array buffer area perform bitwise AND calculation, the relationship of bit alignment needs to be satisfied, and the modification on this basis is the same. Be applicable. In addition, a certain column of the CRC check array buffer area in the CRC calculation unit in FIG. 6 has a corresponding relationship with a certain bit in the CRC update value, and the modification on this basis is also applicable to the scheme.

It should be understood that although the steps in the flowcharts of FIGS. 1-6 are shown in sequence according to the arrows, these steps are not necessarily executed in the sequence shown by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIGS. 1-6 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed and completed at the same time, but may be executed at different times. These sub-steps or stages are not necessarily completed at the same time. The order of execution of the steps is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of sub-steps or stages of other steps.

In one embodiment, as shown in FIG. 7 , a polynomial-configurable parallel CRC hardware implementation apparatus 700 is provided, and the apparatus includes:

Obtaining module 701, the obtaining module is used to obtain a polynomial configurable parallel CRC hardware implementation request;

Generation module 702, the generation module is used to generate a CRC check matrix parameter according to the requirements of the CRC generator polynomial in the protocol and the parallelism of the hardware processing data;

Adaptation module 703, the adaptation module is used to adapt the generated CRC check matrix parameters to the check matrix buffer area of the CRC calculation unit in the hardware circuit through the software-hardware interactive interface;

Calculation module 704, the calculation module is configured to generate a CRC result by iterative calculation according to the input data and the check matrix parameter by the CRC calculation unit in the hardware circuit.

In one embodiment, the generation module 702 is also used to:

Determine the CRC generator polynomial g(x) and the degree of parallelism n;

The corresponding CRC coefficient matrix and CRC data matrix are respectively generated by the CRC coefficient matrix generator and the CRC data matrix generator;

The CRC coefficient matrix and the CRC data matrix are combined to obtain a CRC check matrix.

In one embodiment, the generation module 702 is also used to:

A sparse matrix is constructed according to the CRC generator polynomial g(x), and the CRC coefficient matrix is generated by performing n-1 linear transformations on the sparse matrix.

In one embodiment, the computing module 704 is also used to:

The kbit data in the data buffer area and the CRC check matrix buffer area are processed according to the row direction of the check matrix to generate m intermediate values respectively;

The row direction processing is to perform a bitwise AND operation on the kbit data in the data buffer area and the single row kbit data in the CRC check matrix to generate an intermediate value;

The m intermediate values are respectively carried out bitwise XOR operation to generate the CRC update value of m bit;

When the input nbit data is the last group, the corresponding generated CRC update value is stabilized by the mbit D flip-flop as the output result of the CRC.

For the specific limitation of the polynomially configurable parallel CRC hardware implementation device, reference may be made to the foregoing limitations on the polynomially configurable parallel CRC hardware implementation method, which will not be repeated here.

In one embodiment, a computer device is provided, the internal structure of which can be shown in FIG. 8 . The computer device includes a processor, memory, and a network interface connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium, an internal memory. The nonvolatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the execution of the operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. The computer program implements a polynomially configurable parallel CRC hardware implementation method when executed by the processor.

Those skilled in the art can understand that the structure shown in FIG. 8 is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer equipment to which the solution of the present application is applied. Include more or fewer components than shown in the figures, or combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps in the above method embodiments when the processor executes the computer program.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, implements the steps in each of the above method embodiments.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage In the medium, when the computer program is executed, it may include the processes of the above-mentioned method embodiments. Wherein, any reference to memory, storage, database or other medium used in the various embodiments provided in this application may include non-volatile and/or volatile memory. Nonvolatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Road (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features It is considered to be the range described in this specification.

The above-mentioned embodiments only represent several embodiments of the present application, and the descriptions thereof are specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the appended claims.

Claims (10)

1. A polynomial-configurable parallel CRC hardware implementation method, the method comprising:

acquiring a parallel CRC hardware implementation request with a configurable polynomial;

generating a CRC check matrix parameter according to a CRC generator polynomial in a protocol and the requirement of parallelism of hardware processing data;

the generated CRC check matrix parameters are adapted to a check matrix cache region of a CRC calculation unit in a hardware circuit through a software and hardware interaction interface;

and a CRC calculation unit in the hardware circuit performs iterative calculation according to the input data and the check matrix parameters to generate a CRC result.

2. The hardware implementation method of parallel CRC polynomial of claim 1, wherein the step of generating CRC check matrix parameters according to the CRC generator polynomial in the protocol and the parallelism requirement of the hardware processing data further comprises:

determining a CRC generator polynomial g (x) and a parallelism n;

respectively generating a corresponding CRC coefficient matrix and a corresponding CRC data matrix through a CRC coefficient matrix generator and a CRC data matrix generator;

and combining the CRC coefficient matrix and the CRC data matrix to obtain a CRC check matrix.

3. The method of claim 2, wherein the step of generating corresponding CRC coefficient matrices and CRC data matrices by a CRC coefficient matrix generator and a CRC data matrix generator, respectively, further comprises:

and constructing a sparse matrix according to the CRC generator polynomial g (x), and performing linear transformation on the sparse matrix for n-1 times to generate a CRC coefficient matrix.

4. The hardware implementation method of claim 3, wherein the step of generating the CRC result by the CRC calculation unit in the hardware circuit performing iterative computation according to the input data and the check matrix parameters further comprises:

processing kbit data in the data cache region and a CRC (cyclic redundancy check) check matrix cache region according to the row direction of a check matrix, and respectively generating m intermediate values;

the row direction processing is to perform bitwise AND operation on the kbit data in the data cache region and the single-row kbit data in the CRC check matrix to generate an intermediate value;

performing bitwise XOR operation on the m intermediate values to generate a CRC update value of m bits;

and when the input nbit data is the last group, stabilizing the correspondingly generated CRC updating value by an mbit D trigger to be used as the output result of the CRC.

5. An apparatus for parallel hardware implementation of a polynomial configurable CRC, the apparatus comprising:

the acquisition module is used for acquiring a parallel CRC hardware implementation request with configurable polynomial;

the generating module is used for generating CRC check matrix parameters according to the CRC generator polynomial in the protocol and the requirement of the parallelism of hardware processing data;

the adaptation module is used for adapting the generated CRC check matrix parameters to a check matrix cache region of a CRC calculation unit in a hardware circuit through a software and hardware interaction interface;

and the calculation module is used for performing iterative calculation on the CRC calculation unit in the hardware circuit according to the input data and the check matrix parameters to generate a CRC result.

6. The apparatus of claim 5, wherein the generating module is further configured to:

determining a CRC generator polynomial g (x) and a parallelism n;

respectively generating a corresponding CRC coefficient matrix and a corresponding CRC data matrix through a CRC coefficient matrix generator and a CRC data matrix generator;

and combining the CRC coefficient matrix and the CRC data matrix to obtain a CRC check matrix.

7. The apparatus of claim 6, wherein the generating module is further configured to:

and constructing a sparse matrix according to the CRC generator polynomial g (x), and performing linear transformation on the sparse matrix for n-1 times to generate a CRC coefficient matrix.

8. The apparatus of claim 5, wherein the computing module is further configured to:

processing kbit data in the data cache region and a CRC (cyclic redundancy check) check matrix cache region according to the row direction of a check matrix, and respectively generating m intermediate values;

the row direction processing is to perform bitwise AND operation on the kbit data in the data cache region and the single-row kbit data in the CRC check matrix to generate an intermediate value;

performing bitwise XOR operation on the m intermediate values to generate a CRC update value of m bits;

when the input n-bit data is the last group, the corresponding generated CRC update value is stabilized by the m-bit D trigger and then used as the output result of the CRC.

9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method of any of claims 1 to 4 are implemented when the computer program is executed by the processor.

10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.

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