CN114911418B - Radio signal storage and playback device - Google Patents

Abstract

The embodiment of the present specification provides a radio signal storage and playback device, including: a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip, a digital walkie-talkie, and a host computer; the radio frequency front end is used to receive a signal to be analyzed through an antenna, and perform at least one of amplification, filtering, and mixing processing on the signal to be analyzed to obtain an intermediate frequency signal; the AD data acquisition module is used to sample the intermediate frequency signal, and the FPGA processor is used to perform at least one of digital frequency shifting, spectrum calculation, digital demodulation, storage and playback control, trigger signal recognition and trigger processing on the sampled data, and upload the data generated in the processing to the host computer when receiving an instruction from the host computer; the DDR3 memory chip is used to classify and store the data.

Description

A radio signal storage and playback device

Technical Field

The present invention relates to the field of radio monitoring, and in particular to a radio signal storage and playback device.

Background technique

With the development of society, wireless communication plays an increasingly important role in national security and people's livelihood security. Radio signal storage and playback devices are used to search, measure, analyze, identify radio signals, and find the direction and locate the radiation source, which is an important part of wireless communication technology. As the radio environment becomes more and more complex, the relevant technical indicators of the monitoring system, such as sensitivity, stability, miniaturization, bandwidth and analysis speed, also need to be upgraded accordingly, especially the addition of some offline analysis application scenarios.

Therefore, it is hoped to provide a spectrum analysis device, method and storage medium for a radio signal storage and playback device, which can realize the classification, storage and management of data sources, the identification and storage of abnormal signals, and the matching of playback rates through an FPGA processor, thereby enriching the offline analysis function of radio signals.

Summary of the invention

One or more embodiments of the present specification provide a radio signal storage and playback device, including: a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip, a digital walkie-talkie, and a host computer; the radio frequency front end is communicatively connected to the AD data acquisition module, and the radio frequency front end is used to receive a signal to be analyzed through an antenna, and amplify, filter, and mix the signal to be analyzed to obtain an intermediate frequency signal; the AD data acquisition module is communicatively connected to the FPGA processor, and the AD data acquisition module is used to sample the intermediate frequency signal and upload the obtained sampled data to the FPGA processor; the FPGA processor is communicatively connected to the DDR3 memory chip, the host computer, and the digital walkie-talkie respectively, and the FPGA processor is used to perform at least one of digital frequency shifting, spectrum calculation, digital demodulation, storage and playback control, trigger signal recognition and trigger processing on the sampled data, and upload the data generated in the processing to the host computer when receiving an instruction from the host computer; the DDR3 memory chip is used to perform at least one of digital frequency shifting, spectrum calculation, digital demodulation, storage and playback control, trigger signal recognition and trigger processing on the sampled data based on the DDR3 memory chip. The instructions issued by the FPGA processor classify and store the data received by the FPGA processor, and serve as the data source when the FPGA processor plays back the data; the digital walkie-talkie is communicatively connected to the FPGA processor, and the digital walkie-talkie is used to interact with the FPGA processor to receive sound signals under each channel; the host computer is used to run the human-computer interaction software, and obtain user instructions based on the running human-computer interaction software, and issue the user instructions to the FPGA processor, and display the spectrum information based on the data generated in the processing.

In some embodiments, the FPGA processor includes a digital frequency shift control module, a data source selection module, a digital signal processing module, and a storage and playback control module; the digital frequency shift control module is communicatively connected to the storage and playback control module and the data source selection module, respectively, and the storage and playback control module is communicatively connected to the data source selection module and the digital signal processing module, respectively; the data source selection module is communicatively connected to the digital signal processing module.

In some embodiments, the digital signal processing module includes: a digital filter, an FFT unit, a detection unit, and a digital demodulation unit; the digital filter is communicatively connected to the digital demodulation unit and the FFT unit, respectively, and the FFT unit is communicatively connected to the detection unit.

In some embodiments, the sampling working mode of the radio signal storage and playback device includes a real-time sampling working mode and a recording and playback working mode.

In some embodiments, the real-time sampling working mode is implemented based on the following method:

The AD data acquisition module transmits the real-time sampling data to the data source selection module through the digital frequency shift control module of the FPGA processor; the data source selection module transmits the received real-time sampling data to the digital filter of the FPGA processor; the digital filter transmits the received real-time sampling data to the FFT unit and the digital demodulation unit respectively, so as to perform narrowband filtering, digital demodulation, spectrum calculation and digital detection operations on the real-time sampling data respectively; the digital demodulation unit and the detection unit respectively transmit the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

In some embodiments, the record and playback working mode is divided into original IQ data record and playback and narrowband IQ data record and playback based on different data sources.

In some embodiments, the original IQ data recording and playback is implemented based on the following method:

The AD data acquisition module transmits the real-time sampling data to the storage and playback control module through the digital frequency shift control module of the FPGA processor; the storage and playback control module performs at least one of abnormal signal recognition, data packaging, and interface protocol conversion processing on the real-time sampling data, and transmits the processed data to the DDR3 storage chip for storage; when playing back the data, the storage and playback control module reads data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching so that the playback data matches the rate of the real-time sampling data and sends it to the digital signal processing module for processing; the digital signal processing module transmits the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

In some embodiments, the narrowband IQ data recording and playback is implemented based on the following method:

The AD data acquisition module transmits the real-time sampling data to the digital filter of the digital signal processing module through the digital frequency shift control module and the data source selection module of the FPGA processor in sequence; wherein the digital filter includes a plurality of filter units and the decimation rate of each filter unit is different; the digital filter processes the received data and outputs narrowband IQ data of different bandwidths, and the bandwidth range of the narrowband IQ data is 2kHz-160MHz; the digital filter then sends the narrowband IQ data of each file to the storage and playback control module for at least one of abnormal signal identification, data packaging, and interface protocol conversion processing; the storage and playback control module sends the processed data to the DDR3 storage chip for storage; when playing back the data, the storage and playback control module reads data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching to make the playback data match the narrowband IQ of the real-time sampling. The data rate is sent to the digital signal processing module for processing; the digital signal processing module transmits the processed data to the digital intercom for playback or the host computer for real-time spectrum display.

In some embodiments, the operating mode of the storage and playback control module includes a normal mode;

In the conventional mode, the radio signal storage and playback device is configured to perform the following operations:

Based on the host computer, the storage parameters set by the user are obtained, and the storage parameters include storage data source, storage starting point, and storage length; the FPGA processor stores the received sampled data in the DDR3 storage chip based on the storage parameters; after the storage length is satisfied, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt manner; wherein the execution number of the above storage process is not less than 1, and each time the storage process is executed, the host computer has a corresponding file record storage setting; when playing back the data, the data source for playback is determined based on the host computer;

Based on the FPGA processor, the playback data volume and playback speed are controlled to simulate real sampling data; based on the FPGA processor, the playback data is processed, and the processed data is transmitted to the digital intercom for playback or to the host computer for real-time spectrum display.

In some embodiments, the operating mode of the storage and playback control module includes a trigger mode;

In the trigger mode, the radio signal storage and playback device is configured to perform the following operations:

Before storage, trigger parameters and storage parameters are obtained based on the host computer, and the trigger parameters include the trigger advance data amount and the trigger threshold; the storage parameters include the storage starting point and the storage length; when storing, the FPGA processor stores the received sampled data to the DDR3 storage chip based on the storage parameters, and judges the abnormal signal and counts the amount of stored data according to the trigger threshold during the storage process; based on the detection status of the abnormal signal, the FPGA processor performs the following operations respectively: if the abnormal signal is detected after the amount of stored data exceeds the trigger advance data amount, the abnormal signal and the data of the remaining data length continue to be stored, and the storage location of the abnormal signal is recorded; if the amount of stored data does not reach the trigger advance data amount ... When the leading data volume is triggered, that is, the abnormal signal is detected, the abnormal signal is discarded and the stored data is cleared; the detection of new abnormal signals is restarted and the stored data volume is counted until the stored data volume exceeds the trigger leading data volume, and then the abnormal signal is detected; after the storage length is met, the FPGA processor generates a storage completion signal, and notifies the host computer in an interrupt manner to upload the storage location of the abnormal signal at the same time; wherein, the execution number of the above storage process is not less than 1, and each time the storage process is executed, the host computer has a corresponding file record storage setting; when playing back the data, the host computer first sends down the storage location, storage boundary and other parameters of the abnormal signal, and determines the data source for playback; based on the FPGA processor, the playback data volume and playback speed are controlled to simulate real sampling data; based on the FPGA processor, the playback data is processed, and the processed data is transmitted to the digital intercom for playback or the host computer for real-time spectrum display.

BRIEF DESCRIPTION OF THE DRAWINGS

This specification will be further described in the form of exemplary embodiments, which will be described in detail by the accompanying drawings. These embodiments are not restrictive, and in these embodiments, the same number represents the same structure, wherein:

FIG1 is a schematic diagram of an application scenario of a radio signal storage and playback device according to some embodiments of this specification;

FIG2 is an exemplary structural diagram of a radio signal storage and playback device according to some embodiments of this specification;

FIG3 is an exemplary flow chart of a real-time sampling working mode according to some embodiments of the present specification;

FIG4 is an exemplary flow chart of recording and replaying raw IQ data in a recording and replaying working mode according to some embodiments of this specification;

FIG5 is an exemplary flow chart of narrowband IQ data recording and playback according to some embodiments of the present specification;

FIG6 is an exemplary flow chart of a normal mode according to some embodiments of the present specification;

FIG. 7 is an exemplary flow chart of a trigger mode according to some embodiments of the present specification.

Detailed ways

In order to more clearly illustrate the technical solutions of the embodiments of this specification, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of this specification. For ordinary technicians in this field, without paying creative work, this specification can also be applied to other similar scenarios based on these drawings. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

It should be understood that the "system", "device", "unit" and/or "module" used herein are a method for distinguishing different components, elements, parts, portions or assemblies at different levels. However, if other words can achieve the same purpose, the words can be replaced by other expressions.

As shown in this specification and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and/or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "comprises" and "includes" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

Flowcharts are used in this specification to illustrate the operations performed by the system according to the embodiments of this specification. It should be understood that the preceding or following operations are not necessarily performed precisely in order. Instead, the steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.

FIG. 1 is a schematic diagram of an application scenario 100 of a radio signal storage and playback device according to some embodiments of this specification.

In some embodiments, the application scenario 100 may be configured as radio monitoring and analysis, etc. It may be applied in corresponding communication control scenarios such as radio monitoring, radio identification, and radio management. The application scenario 100 may include a server 110, a network 120, a user terminal 130, a storage device 140, and a signal source 150. The server 110 may include a processing engine 112. In some embodiments, the server 110, the user terminal 130, the storage device 140, and the signal source 150 may be connected and/or communicate with each other via a wireless connection (e.g., the network 120), a wired connection, or a combination thereof.

The server 110 can be used to implement radio processing, such as radio signal storage and playback, etc. In some embodiments, it can be specifically used to implement monitoring of satellite radio.

The server 110 refers to a system with computing capabilities. In some embodiments, the server 110 may be a single server or a server group. The server group may be centralized or distributed (for example, the server 110 may be a distributed system). In some embodiments, the server 110 may be local or remote. For example, the server 110 may access information and/or data stored in the user terminal 130 and/or the storage device 140 via the network 120. For another example, the server 110 may be directly connected to the user terminal 130 and/or the storage device 140 to access the stored information and/or data. In some embodiments, the server 110 may be implemented on a cloud platform. By way of example only, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distributed cloud, an internal cloud, a multi-layer cloud, etc., or any combination thereof.

In some embodiments, the server 110 may include a processing engine 112. The processing engine 112 may process information and/or data related to wireless signals. For example, the processing engine 112 may implement radio monitoring in the information data obtained by the signal source 150. In some embodiments, the processing engine 112 may include one or more processing engines (e.g., a single-core processing engine or a multi-core processor). By way of example only, the processing engine 112 may include one or more hardware processors, such as a central processing unit (CPU), an application specific integrated circuit (ASIC), an application specific instruction set processor (ASIP), a graphics processing unit (GPU), a physical processing unit (PPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a microcontroller unit, a reduced instruction set computer (RISC), a microprocessor, etc., or any combination thereof.

The network 120 can facilitate the exchange of information and/or data. In some embodiments, one or more components in the application scenario 100 (e.g., the server 110, the user terminal 130, the storage device 140, and the signal source 150) can send information and/or data to other components in the application scenario 100 through the network 120. For example, the processing engine 112 can send the analysis results of the monitored radio to the user terminal 130 via the network 120. In some embodiments, the network 120 can be a wired network or a wireless network, etc. or any combination thereof. As an example only, the network 120 can include a cable network, a wired network, an optical fiber network, a telecommunications network, an intranet, the Internet, a local area network (LAN), a wide area network (WAN), a wireless local area network (WLAN), a metropolitan area network (MAN), a wide area network (WAN), a public switched telephone network (PSTN), a Bluetooth TM network, a ZigBee network, a near field communication (NFC) network, or the like, or any combination thereof. In some embodiments, the network 120 can include one or more network access points. For example, the network 120 may include wired or wireless network access points such as base stations and/or Internet exchange points 120-1, 120-2, ..., and one or more components of the application scenario 100 may be connected to the network 120 via the wired or wireless network access points to exchange data and/or information.

In some embodiments, the user terminal 130 may include a mobile device 130-1, a tablet computer 130-2, a laptop computer 130-3, a desktop computer 130-4, etc., or any combination thereof. In some embodiments, the mobile device 140-1 may include a smart home device, a wearable device, a mobile device, a virtual reality device, an augmented reality device, etc., or any combination thereof. In some embodiments, the smart home device may include a smart lighting device, a smart appliance control device, a smart monitoring device, a smart TV, a smart camera, an intercom, etc., or any combination thereof. In some embodiments, the wearable device may include a bracelet, shoes and socks, glasses, a helmet, a watch, clothing, a backpack, smart accessories, etc., or any combination thereof. In some embodiments, the mobile device may include a mobile phone, a personal digital assistant (PDA), a gaming device, a navigation device, a point of sale (POS) device, a laptop computer, a desktop computer, etc., or any combination thereof. In some embodiments, the virtual reality device and/or the augmented virtual reality device may include a virtual reality helmet, virtual reality glasses, virtual reality goggles, augmented reality helmets, augmented reality glasses, augmented reality goggles, etc., or any combination thereof. For example, the virtual reality device and/or augmented reality device may include Google Glass ^™ , RiftCon ^™ , Fragments ^™ , GearVR ^™ , etc.

In some embodiments, the user terminal 130 may be a mobile terminal configured to collect radio signals. The user terminal 130 may send and/or receive information related to radio signal monitoring and identification to the processing engine 112 or a processor installed in the user terminal 130 via a user interface. For example, the user terminal 130 may send radio signal data captured by the user terminal 130 to the processing engine 112 or a processor installed in the user terminal 120 via a user interface. The user interface may be in the form of an application for identifying satellites implemented on the user terminal 130. The user interface implemented on the user terminal 130 may facilitate communication between the user and the processing engine 112. For example, the user may input and/or import radio signal data to be identified via the user interface. The processing engine 112 may receive the input signal data via the user interface. For another example, the user may input a request to identify a radio signal via the user interface implemented on the user terminal 130.

In some embodiments, in response to the identification request, the user terminal 130 may directly process the radio signal data via a processor of the user terminal 130 based on a signal collection device installed in the user terminal 130 as described elsewhere in this application. In some embodiments, in response to the identification request, the user terminal 130 may send an identification request to the processing engine 112 for determining the radio signal based on a signal collection device installed by the signal source 150 or elsewhere in this application. In some embodiments, the user interface may facilitate the presentation or display of information and/or data (e.g., signals) related to radio monitoring received from the processing engine 112. For example, the information and/or data may include results indicating the content of the radio monitoring, or instructions to perform radio monitoring, etc. In some embodiments, the information and/or data may be further configured to cause the user terminal 130 to display the results to the user.

The storage device 140 may store data and/or instructions. In some embodiments, the storage device 140 may store data obtained from the signal source 150. The storage device 140 may store data and/or instructions that the processing engine 112 may execute or use to execute the exemplary methods described in the present application. In some embodiments, the storage device 140 may include a mass storage, a removable storage, a volatile read-write memory, a read-only memory (ROM), etc., or any combination thereof. An exemplary mass storage may include a disk, an optical disk, a solid-state drive, etc. An exemplary removable storage may include a flash drive, a floppy disk, an optical disk, a memory card, a compressed disk, a magnetic tape, etc. An exemplary volatile read-write memory may include a random access memory (RAM). An exemplary RAM may include a dynamic random access memory (DRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), a static random access memory (SRAM), a thyristor random access memory (T-RAM), and a zero capacitance random access memory (Z-RAM), etc. Exemplary ROMs may include mask read-only memory (MROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM), and digital versatile disk read-only memory, etc. In some embodiments, the storage device 140 may be executed on a cloud platform. By way of example only, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distributed cloud, an internal cloud, a multi-layer cloud, etc., or any combination thereof.

In some embodiments, the storage device 140 may be connected to the network 120 to communicate with one or more components (e.g., the server 110, the user terminal 130) in the application scenario 100. One or more components in the application scenario 100 may access data or instructions stored in the storage device 140 via the network 120. In some embodiments, the storage device 140 may be directly connected to or communicate with one or more components (e.g., the server 110, the user terminal 130) in the application scenario 100. In some embodiments, the storage device 140 may be part of the server 110.

The signal source 150 is a signal end that sends out a radio signal, for example, the signal source may be a satellite, a signal generator, a base station, etc. The radio signal generated by the signal source 150 may be collected based on a corresponding signal collection device.

It should be noted that the above description is intended to be illustrative, rather than limiting the scope of the application. For those skilled in the art, many substitutions, modifications and variations will be apparent. The features, structures, methods and other characteristics of the exemplary embodiments described herein can be combined in various ways to obtain additional and/or alternative exemplary embodiments. For example, signal source 150 can be configured with storage modules, processing modules, communication modules, etc. However, these variations and modifications do not depart from the scope of the application.

FIG. 2 is a diagram showing an exemplary structure of a radio signal storage and playback device according to some embodiments of the present specification.

As shown in FIG. 2 , the radio signal storage and playback device 200 may include: a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip, a digital intercom, and a host computer.

The RF front end is communicatively connected to the AD data acquisition module, and is used to receive the signal to be analyzed through an antenna, and perform at least one of amplification, filtering, and mixing processing on the signal to be analyzed to obtain an intermediate frequency signal.

The AD data acquisition module is in communication connection with the FPGA processor, and is used for sampling the intermediate frequency signal and uploading the obtained sampled data to the FPGA processor.

The FPGA processor is respectively connected to the DDR3 memory chip, the host computer, and the digital intercom for communication. The FPGA processor is used to perform at least one of digital frequency shifting, spectrum calculation, digital demodulation, storage and playback control, trigger signal identification and trigger processing on the sampled data, and upload the data generated during the processing to the host computer when receiving instructions from the host computer.

In some embodiments, the FPGA processor includes a digital frequency shift control module, a data source selection module, a digital signal processing module, and a storage and playback control module; the digital frequency shift control module is communicatively connected to the storage and playback control module and the data source selection module, respectively, and the storage and playback control module is communicatively connected to the data source selection module and the digital signal processing module, respectively; the data source selection module is communicatively connected to the digital signal processing module.

Among them, the digital frequency shift control module can be used to perform digital frequency shift processing on the received signal; the data source selection module determines the data source read by the FPGA processor when performing data playback processing; the digital signal processing module is used to process the read data, and the storage and playback control module is used to read the data and perform playback processing.

In some embodiments, the FPGA processor may further include an external connection module, which may be used to implement communication between the FPGA processor and at least some of the devices in the radio signal storage and playback device other than the processor. For example, the external connection module may include a PCIe interface, a jesd204b interface, etc. The FPGA processor may be connected to the DDR3 memory chip via a PCIe interface, and the AD data acquisition module may be connected to the FPGA processor via a jesd204b interface. Specifically, the AD data acquisition module may transmit data to the FPGA processor via the jesd204b interface for subsequent processing. For another example, the FPGA processor, as a signal processing unit, may receive sampled data from the AD data acquisition module via the jesd204b interface, and further perform operations such as digital frequency shifting, spectrum calculation, digital demodulation, storage and playback control, trigger signal identification and triggering, and then selectively upload the generated data to the host computer via the PCIe interface.

In some embodiments, the digital signal processing module may include: a digital filter, an FFT unit, a detection unit, and a digital demodulation unit; wherein, inside the digital signal processing module, the digital filter is respectively connected to the digital demodulation unit and the FFT unit, and the FFT unit is connected to the detection unit; in the entire FPGA processor, the digital filter is respectively connected to the data source selection module and the storage and playback control module. The digital demodulation unit can also be connected to the digital intercom. The detection unit can also be connected to the host computer. In some embodiments, the digital filter, the FFT unit, the detection unit, and the digital demodulation unit can be used to perform digital filtering, spectrum calculation, digital detection, digital demodulation and other operations on the received data.

The DDR3 memory chip is used to classify and store the data received by the FPGA processor based on the instructions issued by the FPGA processor, and to serve as a data source when the FPGA processor plays back the data. In some embodiments, the DDR3 memory chip is used as the main storage space, and can classify and store the original IQ data and narrowband IQ data through the data source selection command. When the data is played back, the DDR3 memory chip takes out the data to replace the sampled data source.

Using DDR3 as the storage unit, under the design of 1866Mhz sampling clock and 64-bit data bus, it can support a maximum transmission speed of 14.9GMB/s, which is much higher than the throughput rate of IQ data, so the sampling signal will not be lost due to the bottleneck of memory transmission rate. And if the storage space of DDR3 is expanded to 4GB, it can store up to 5s for 160MHz real-time IQ data (sampling rate is 204.8MHz, data bit width is 32bit); for narrowband IQ data, it can be stored for up to several hours. Such storage time can meet the routine monitoring of radio signals.

The digital intercom is communicatively connected to the FPGA processor, and the digital intercom is used to perform data interaction with the FPGA processor to receive sound signals under each channel. For example, the digital intercom can perform data interaction with the digital demodulation module to receive sound signals under each channel.

The host computer is used to run the human-computer interaction software, obtain user instructions based on the running of the human-computer interaction software, send the user instructions to the FPGA processor, and display spectrum information based on the data generated in the processing.

It should be noted that the parameters required for use in this manual can be set by the user according to actual conditions, such as input based on a host computer.

It should be noted that the above description of the system and its components is only for the convenience of description and does not limit this specification to the scope of the embodiments. It is understandable that for those skilled in the art, after understanding the principle of the system, it is possible to arbitrarily combine the various components, or form a subsystem connected to other components without deviating from this principle. For example, the RF front end and the AD data acquisition module can be integrated into one component. For another example, the various components can share a storage device, or each component can have its own storage device. Such variations are all within the scope of protection of this specification.

In some embodiments, the radio signal storage and playback device supports a real-time sampling working mode and a record and playback working mode.

FIG. 3 is an exemplary flow chart of a real-time sampling working mode according to some embodiments of this specification. In some embodiments, process 300 may be executed by the radio signal storage and playback device 200. In some embodiments, process 300 may include the following steps:

Step 310: the AD data acquisition module transmits the real-time sampling data to the data source selection module through the digital frequency shift control module of the FPGA processor.

In some embodiments, the radio signal storage and playback device can first collect the received signal through the antenna based on the RF front end, and then output the intermediate frequency signal after processing such as amplification, filtering, mixing, etc. on the collected signal based on the RF front end.

In some embodiments, the RF front end can transmit the intermediate frequency signal it obtains to an AD data acquisition module designed using ADI high-speed AD chip, and the AD data acquisition module samples and processes the received intermediate frequency signal to obtain a corresponding digital signal such as IQ data.

In some embodiments, the AD data acquisition module can transmit its real-time sampling data to the data source selection module through the digital frequency shift control module of the FPGA processor.

In step 320, the data source selection module transmits the received real-time sampling data to the digital filter of the FPGA processor.

In step 330, the digital filter transmits the received real-time sampling data to the FFT unit and the digital demodulation unit respectively, so as to perform narrowband filtering, digital demodulation, spectrum calculation and digital detection operations on the real-time sampling data respectively.

Step 340: the digital demodulation unit and the detection unit transmit the processed data to the digital intercom for playback or to the host computer for real-time spectrum display.

As an example only, in the real-time sampling working mode, the real-time sampling data of the AD data acquisition module reaches the FPGA processor through the digital frequency shift control module and the data source selection module, and further performs narrowband filtering, digital demodulation, spectrum calculation and digital detection operations. The processed data is sent to the digital walkie-talkie for playback or to the host computer for real-time spectrum display.

It should be noted that the above description of process 300 is only for example and illustration, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to process 400 under the guidance of this specification. However, these modifications and changes are still within the scope of this specification.

In some embodiments, in the record and playback working mode, it can be specifically divided into original IQ data record and playback and narrowband IQ data record and playback according to different data sources.

FIG4 is an exemplary flow chart of recording and replaying raw IQ data in the recording and replaying working mode according to some embodiments of this specification; in some embodiments, process 400 may be executed by the radio signal storage and replaying device 200. In some embodiments, process 400 may include the following steps:

Step 410: The AD data acquisition module transmits the real-time sampling data to the storage and playback control module through the digital frequency shift control module of the FPGA processor.

Step 420: the storage and playback control module performs at least one of abnormal signal recognition, data packaging, and interface protocol conversion processing on the real-time sampled data, and transmits the processed data to the DDR3 storage chip for storage.

Step 430, when playing back data, the storage and playback control module reads data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching to make the playback data match the rate of the real-time sampling data and send it to the digital signal processing module for processing.

Step 440: the digital signal processing module transmits the processed data to the digital intercom for playback or to the host computer for real-time spectrum display.

Just as an example, when the original IQ data is recorded and played back, the real-time sampling data of the AD data acquisition module enters the storage and playback control module after passing through the digital frequency shift control module, and is further stored in the DDR3 storage chip after performing abnormal signal recognition, data packaging, interface protocol conversion and other operations. During playback, the storage and playback control module takes out data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching so that the playback data matches the rate of the real-time sampling data and is fed into the subsequent digital signal processing module. The processed data is then sent to the digital intercom for playback or the host computer for spectrum display.

It should be noted that the above description of process 400 is only for example and illustration, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to process 400 under the guidance of this specification. However, these modifications and changes are still within the scope of this specification.

FIG5 is an exemplary flowchart of narrowband IQ data recording and playback according to some embodiments of this specification; in some embodiments, process 500 may be executed by the radio signal storage and playback device 200. In some embodiments, process 500 may include the following steps:

In step 510, the AD data acquisition module transmits the real-time sampling data to the digital filter of the digital signal processing module through the digital frequency shift control module and the data source selection module of the FPGA processor in sequence.

Step 520: The digital filter processes the received data and outputs narrowband IQ data of different bandwidths.

In step 530, the digital filter sends the narrowband IQ data of each level to the storage and playback control module for at least one of abnormal signal identification, data packaging, and interface protocol conversion.

Step 540: the storage and playback control module sends the processed data to the DDR3 storage chip for storage.

Step 550: When playing back data, the storage and playback control module reads data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching.

Step 560, making the playback data match the rate of the narrowband IQ data sampled in real time and sending it to the digital signal processing module for processing.

Step 570: the digital signal processing module transmits the processed data to the digital intercom for playback or to the host computer for real-time spectrum display.

As an example only, when the narrowband IQ data is recorded and played back, the real-time sampling data of the AD data acquisition module passes through the digital frequency shift module and the digital filter group (where the sampling rates of each level of the filter group are different), and narrowband IQ data of different bandwidths can be output. The bandwidth range is 2kHz-160MHz, and can be divided into n levels according to user needs.

Each file of narrowband IQ data enters the storage and playback control module, and further performs abnormal signal identification, data packaging, interface protocol conversion and other operations to store in the DDR3 storage chip. During playback, the storage and playback control module takes out data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching to make the playback data match the real-time sampled narrowband IQ data rate and then feed it into the subsequent digital demodulation, spectrum calculation and detection modules for processing. The processed data is sent to the digital intercom for playback or the host computer for spectrum display.

It should be noted that the above description of process 500 is only for example and explanation, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to process 500 under the guidance of this specification. However, these modifications and changes are still within the scope of this specification.

In some embodiments, the operating mode of the storage and playback control module includes a normal mode.

FIG6 is an exemplary flow chart in a normal mode according to some embodiments of the present specification; in some embodiments, process 600 may be executed by the radio signal storage and playback device 200. In some embodiments, process 600 may include the following steps:

Step 610, based on the host computer, obtaining storage parameters set by the user, the storage parameters include storage data source, storage starting point, and storage length.

In step 620, the FPGA processor stores the received sampled data into the DDR3 memory chip based on the storage parameters.

Step 630: After the storage length is satisfied, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt manner.

Step 640: When playing back data, determine the data source for playback based on the host computer.

Step 650, controlling the playback data volume and playback speed based on the FPGA processor to simulate real sampled data.

Step 660: Process the playback data based on the FPGA processor, and transmit the processed data to the digital intercom for playback or to the host computer for real-time spectrum display.

As an example only, in normal mode, you can freely select the starting position and data volume for storage and playback. The host computer selects the storage data source, sets the storage starting point, storage length and other parameters. After the parameters take effect, data storage begins. When the storage length meets the set requirements, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt manner. The storage process can be executed multiple times, and each time the host computer stores data, there is a corresponding file record storage setting.

During playback, the host computer selects the data source to be played back, and then clicks to start playback. The FPGA processor performs logical control of the playback data volume and playback speed to match the real sampling data source. The playback data replaces the real-time sampling data for subsequent signal analysis, digital demodulation and other operations. The spectrum waveform generated by the playback data is also displayed on the host computer interface.

It should be noted that the above description of process 600 is only for example and explanation, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to process 600 under the guidance of this specification. However, these modifications and changes are still within the scope of this specification.

FIG. 7 is an exemplary flow chart of a trigger mode according to some embodiments of the present specification; in some embodiments, process 700 may be executed by the radio signal storage and playback device 200. In some embodiments, process 700 may include the following steps:

Step 710, before storing, obtaining trigger parameters and storage parameters based on the host computer, wherein the trigger parameters include the trigger advance data amount and the trigger threshold; and the storage parameters include the storage starting point and the storage length.

Step 720, when storing, the FPGA processor stores the received sampled data to the DDR3 memory chip based on the storage parameters, and judges abnormal signals and counts the amount of stored data according to the trigger threshold during the storage process.

Step 730: Based on the detection status of the abnormal signal, the FPGA processor performs different operations.

In some embodiments, based on the detection status of the abnormal signal, the FPGA processor performs the following operations respectively:

If the abnormal signal is detected after the amount of stored data exceeds the trigger advance data amount, the abnormal signal and the data of the remaining data length continue to be stored, and the storage location of the abnormal signal is recorded;

If the amount of stored data does not reach the trigger advance data amount, that is, the abnormal signal is detected, the abnormal signal is discarded and the stored data is cleared;

Restart detecting new abnormal signals and counting the amount of stored data until the amount of stored data exceeds the trigger advance data amount, and then detect the condition of the abnormal signal.

Step 740, after the storage length is satisfied, the FPGA processor generates a storage completion signal, and notifies the host computer in an interrupt mode to upload the storage location of the abnormal signal at the same time. The execution number of the above storage process is not less than 1, and each time the storage process is executed, the host computer has a corresponding file record storage setting.

Step 750, when playing back the data, the host computer first sends down the storage location, storage boundary and other parameters of the abnormal signal, and determines the source of the playback data.

Step 760, controlling the playback data volume and playback speed based on the FPGA processor to simulate real sampled data.

Step 770: Process the playback data based on the FPGA processor, and transmit the processed data to the digital intercom for playback or to the host computer for real-time spectrum display.

As an example only, the trigger mode mainly records and replays abnormal signals. The replay operation is limited by the storage process and cannot be set arbitrarily. In the storage operation, first set the trigger advance data volume, trigger threshold, storage start, storage length and other parameters through the host computer. After the parameters take effect, data storage begins, and during the storage process, the abnormal signal is judged according to the trigger threshold and the amount of stored data is counted. According to the state of the abnormal signal, it can be divided into two situations:

a. If the amount of stored data exceeds the set trigger advance data amount before the abnormal signal is detected, the abnormal signal and the remaining data length will continue to be stored, and the storage location of the abnormal point will be recorded;

b. If the amount of stored data does not reach the set trigger advance data amount and an abnormal signal is detected, the abnormal signal is discarded, the stored data is cleared, and new abnormal signals are detected again and the stored data is counted until situation a is met.

When the length meets the set requirements, the FPGA processor generates a storage completion signal, notifies the host computer in an interrupt mode, and uploads the abnormal signal storage location at the same time. The storage process can be executed multiple times, and each time the host computer stores, there is a corresponding file record storage setting.

In the playback operation, the host computer first sends the abnormal signal storage location, storage boundary and other parameters, selects the playback data source, and then clicks to start playback. The FPGA processor logic controls the playback data volume and playback speed to match the real sampling data source. The playback data replaces the real-time sampling data, and subsequent signal analysis, digital demodulation and other operations are performed. The spectrum waveform generated by the playback data is also displayed on the host computer interface.

It should be noted that the above description of process 700 is only for example and explanation, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to process 700 under the guidance of this specification. However, these modifications and changes are still within the scope of this specification.

In some embodiments of the present invention, rich storage and playback functions are designed. According to the working mode, it can be divided into normal mode and trigger mode, among which the trigger mode is aimed at capturing abnormal signals, which can greatly improve the retrieval efficiency of abnormal signals; according to the number of playbacks, it can be divided into single playback and loop playback modes, so that users can analyze signals and observe spectrum phenomena more clearly. At the same time, the storage data source can also be classified, and the original IQ data and narrowband IQ data can be stored separately, and the playback speed can be matched with the real-time sampling speed, so that there is no difference in sampling rate between the playback data source and the real-time sampling data source.

The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of this specification. Although not explicitly stated here, those skilled in the art may make various modifications, improvements and corrections to this specification. Such modifications, improvements and corrections are suggested in this specification, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of this specification.

At the same time, this specification uses specific words to describe the embodiments of this specification. For example, "one embodiment", "an embodiment", and/or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of this specification. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures or characteristics in one or more embodiments of this specification can be appropriately combined.

In addition, unless explicitly stated in the claims, the order of the processing elements and sequences described in this specification, the use of alphanumeric characters, or the use of other names are not intended to limit the order of the processes and methods of this specification. Although the above disclosure discusses some invention embodiments that are currently considered useful through various examples, it should be understood that such details are only for illustrative purposes, and the attached claims are not limited to the disclosed embodiments. On the contrary, the claims are intended to cover all modifications and equivalent combinations that are consistent with the essence and scope of the embodiments of this specification. For example, although the system components described above can be implemented by hardware devices, they can also be implemented only by software solutions, such as installing the described system on an existing server or mobile device.

Similarly, it should be noted that in order to simplify the description disclosed in this specification and thus help understand one or more embodiments of the invention, in the above description of the embodiments of this specification, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the subject matter of this specification are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of this specification are approximate values, in specific embodiments, the setting of such numerical values is as accurate as possible within the feasible range.

Each patent, patent application, patent application publication, and other materials, such as articles, books, specifications, publications, documents, etc., cited in this specification is hereby incorporated by reference in its entirety. Except for application history documents that are inconsistent with or conflicting with the contents of this specification, documents that limit the broadest scope of the claims of this specification (currently or later attached to this specification) are also excluded. It should be noted that if the descriptions, definitions, and/or use of terms in the materials attached to this specification are inconsistent or conflicting with the contents described in this specification, the descriptions, definitions, and/or use of terms in this specification shall prevail.

Finally, it should be understood that the embodiments described in this specification are only used to illustrate the principles of the embodiments of this specification. Other variations may also fall within the scope of this specification. Therefore, as an example and not a limitation, alternative configurations of the embodiments of this specification may be considered consistent with the teachings of this specification. Accordingly, the embodiments of this specification are not limited to the embodiments explicitly introduced and described in this specification.

Claims (9)

1. A radio signal storage and playback device, characterized in that it includes: a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip, a digital intercom, and a host computer; The RF front end is communicatively connected to the AD data acquisition module, and is used to receive the signal to be analyzed through the antenna, and perform at least one of amplification, filtering, and mixing processing on the signal to be analyzed to obtain an intermediate frequency signal; The AD data acquisition module is communicatively connected to the FPGA processor, and the AD data acquisition module is used to sample the intermediate frequency signal and upload the obtained sampled data to the FPGA processor; The FPGA processor is respectively connected to the DDR3 memory chip, the host computer, and the digital intercom, and the FPGA processor is used to perform at least one of digital frequency shifting, spectrum calculation, digital demodulation, storage and playback control, trigger signal identification and trigger processing on the sampled data, and upload the data generated in the processing to the host computer when receiving an instruction from the host computer; The DDR3 memory chip is used to classify and store the data received by the FPGA processor based on the instructions issued by the FPGA processor, and to serve as a data source when the FPGA processor plays back the data; The digital intercom is communicatively connected to the FPGA processor, and the digital intercom is used to perform data interaction with the FPGA processor to receive sound signals under each channel; The host computer is used to run the human-computer interaction software, obtain user instructions based on the running of the human-computer interaction software, issue the user instructions to the FPGA processor, and display spectrum information based on the data generated in the processing; Wherein, the working mode of the storage and playback control module includes a trigger mode; In the trigger mode, the radio signal storage and playback device is configured to perform the following operations: Before storage, trigger parameters and storage parameters are obtained based on the host computer, wherein the trigger parameters include the trigger advance data amount and the trigger threshold; and the storage parameters include the storage starting point and the storage length; During storage, the FPGA processor stores the received sampled data in the DDR3 storage chip based on the storage parameters, and determines abnormal signals and counts the amount of stored data according to the trigger threshold during the storage process; Based on the detection status of the abnormal signal, the FPGA processor performs the following operations respectively: If the abnormal signal is detected after the amount of stored data exceeds the trigger advance data amount, the abnormal signal and the data of the remaining data length continue to be stored, and the storage location of the abnormal signal is recorded; If the amount of stored data does not reach the trigger advance data amount, that is, the abnormal signal is detected, the abnormal signal is discarded and the stored data is cleared; Restart detecting new abnormal signals and counting the amount of stored data until the amount of stored data exceeds the trigger advance data amount, and then detect the abnormal signal; After the storage length is satisfied, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt manner to simultaneously upload the storage location of the abnormal signal; When replaying data, the host computer first sends the storage location and storage boundary parameters of the abnormal signal, and determines the data source for playback; Based on the FPGA processor, the playback data volume and playback speed are controlled to simulate real sampling data; based on the FPGA processor, the playback data is processed, and the processed data is transmitted to the digital intercom for playback or to the host computer for real-time spectrum display. 2. The radio signal storage and playback device according to claim 1 is characterized in that the FPGA processor includes a digital frequency shift control module, a data source selection module, a digital signal processing module, and a storage and playback control module; the digital frequency shift control module is communicatively connected to the storage and playback control module and the data source selection module respectively, and the storage and playback control module is communicatively connected to the data source selection module and the digital signal processing module respectively; the data source selection module is communicatively connected to the digital signal processing module. 3. The radio signal storage and playback device according to claim 2, characterized in that the digital signal processing module comprises: a digital filter, an FFT unit, a detection unit, and a digital demodulation unit; The digital filter is communicatively connected with the digital demodulation unit and the FFT unit respectively, and the FFT unit is communicatively connected with the detection unit. 4. The radio signal storage and playback device according to claim 3 is characterized in that the sampling working mode of the radio signal storage and playback device includes a real-time sampling working mode and a recording and playback working mode. 5. The radio signal storage and playback device according to claim 4, characterized in that the real-time sampling working mode is implemented based on the following method: The AD data acquisition module transmits the real-time sampling data to the data source selection module through the digital frequency shift control module of the FPGA processor; The data source selection module transmits the received real-time sampling data to the digital filter of the FPGA processor; The digital filter transmits the received real-time sampling data to the FFT unit and the digital demodulation unit respectively, so as to perform narrowband filtering, digital demodulation, spectrum calculation and digital detection operations on the real-time sampling data respectively; The digital demodulation unit and the detection unit respectively transmit the processed data to the digital intercom for playback or to the host computer for real-time spectrum display. 6. The radio signal storage and playback device according to claim 4 is characterized in that the recording and playback working mode is divided into original IQ data recording and playback and narrowband IQ data recording and playback based on different data sources. 7. The radio signal storage and playback device according to claim 6, wherein the original IQ data recording and playback is implemented based on the following method: The AD data acquisition module transmits the real-time sampling data to the storage and playback control module through the digital frequency shift control module of the FPGA processor; The storage and playback control module performs at least one of abnormal signal recognition, data packaging, and interface protocol conversion processing on the real-time sampled data, and transmits the processed data to the DDR3 storage chip for storage; When playing back data, the storage and playback control module reads data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching to make the playback data match the rate of the real-time sampling data and send it to the digital signal processing module for processing; The digital signal processing module transmits the processed data to the digital intercom for playback or to the host computer for real-time spectrum display. 8. The radio signal storage and playback device according to claim 6, wherein the narrowband IQ data recording and playback is implemented based on the following method: The AD data acquisition module transmits the real-time sampling data to the digital filter of the digital signal processing module through the digital frequency shift control module and the data source selection module of the FPGA processor in sequence; wherein the digital filter includes a plurality of filter units and the decimation rate of each filter unit is different; The digital filter processes the received data and outputs narrowband IQ data of different bandwidths, wherein the bandwidth range of the narrowband IQ data is 2kHz-160MHz; The digital filter then sends the narrowband IQ data to the storage and playback control module for at least one of abnormal signal identification, data packaging, and interface protocol conversion processing; The storage and playback control module sends the processed data to the DDR3 storage chip for storage; When playing back data, the storage and playback control module reads data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching so that the playback data matches the rate of the narrowband IQ data sampled in real time and sends it to the digital signal processing module for processing. 9. The radio signal storage and playback device according to any one of claims 1 to 8, characterized in that the working mode of the storage and playback control module includes a normal mode; In the conventional mode, the radio signal storage and playback device is configured to perform the following operations: Based on the host computer, the storage parameters set by the user are obtained, wherein the storage parameters include a storage data source, a storage starting point, and a storage length; The FPGA processor stores the received sampled data in the DDR3 memory chip based on the storage parameters; After the storage length is met, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt mode; The execution number of the above-mentioned storage process is not less than 1, and each time the storage process is executed, the host computer has a corresponding file record storage setting; When playing back data, determining the data source for playback based on the host computer; Controlling the playback data volume and playback speed based on the FPGA processor to simulate real sampled data; The playback data is processed based on the FPGA processor, and the processed data is transmitted to the digital intercom for playback or to the host computer for real-time spectrum display.