CN114882826A - Shift register, driving method thereof, gate driving circuit and display device - Google Patents

Abstract

A shift register, a driving method thereof, a gate driving circuit and a display device provided by the present disclosure include an input circuit configured to provide a signal of the input signal terminal to a first node in response to a signal of the input signal terminal; a driving output circuit, at least is configured to respond to the signal of the first node, provide the signal of the clock signal terminal as a gate drive signal to the driving signal output terminal; the residual charge discharge circuit is configured to respond to the signal of the discharge signal terminal, the first reference signal terminal A reference signal is provided to the driving signal output terminal, and the level of the first reference signal is the same as that of the gate driving signal.

Description

Shift register, driving method thereof, gate driving circuit and display device

technical field

The present disclosure relates to the field of display technology, and in particular, to a shift register, a driving method thereof, a gate driving circuit and a display device.

Background technique

With the vigorous development of display technology, the cost requirements of display devices are getting lower and lower, and how to effectively reduce the manufacturing cost of the panel is related to the strength of product competitiveness. In order to reduce the manufacturing cost of the display device, the related art utilizes the edge of the display device to design a gate drive circuit. The gate drive circuit includes a plurality of shift registers arranged in cascade. In the display stage, each row of shift registers controls the row of pixels to perform show. Such a design can save space for placing a chip on film and a printed circuit board on the display device, not only can realize a narrow frame design of the display device, but also can reduce the manufacturing cost of the display device and improve the competitiveness of the product.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure provide a shift register, a driving method thereof, a gate driving circuit and a display device, which are used to solve the problem in the prior art that the residual charge in the display area cannot be discharged normally, resulting in abnormal display.

Therefore, a shift register provided by an embodiment of the present disclosure includes:

an input circuit configured to provide the signal at the input signal terminal to the first node in response to the signal at the input signal terminal;

a drive output circuit, at least configured to provide the signal at the clock signal terminal as a gate drive signal to the drive signal output terminal in response to the signal at the first node;

a residual charge discharge circuit configured to provide a first reference signal at the first reference signal terminal to the drive signal output terminal in response to a signal at the discharge signal terminal, the level of the first reference signal being the same as that of the gate drive signal the same level.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, the discharge signal terminal includes: at least one sub-discharge signal terminal, and the residual charge discharge circuit includes: one-to-one with the sub-discharge signal terminal A corresponding sub-discharge circuit, the sub-discharge circuit is configured to provide the first reference signal to the drive signal output terminal in response to a signal corresponding to the sub-discharge signal terminal.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, the sub-discharge circuit includes: a first transistor, and a gate of the first transistor is coupled to the corresponding sub-discharge signal terminal, The first pole of the first transistor is coupled to the first reference signal terminal, and the second pole of the first transistor is coupled to the driving signal output terminal.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, at least some of the sub-discharge circuits further include: a first capacitor, and in the same sub-discharge circuit, the first capacitor is coupled to between the gate of the first transistor and the first reference signal terminal.

In some embodiments, the above-mentioned shift register provided by the embodiments of the present disclosure further includes: a reset circuit, configured at least to provide the signal of the second reference signal terminal to the first in response to the signal of the initial reset signal terminal node;

At least some of the sub-discharge signal terminals are multiplexed with the initial reset signal terminal and/or the first reference signal terminal, or all the sub-discharge signal terminals are multiplexed with the initial reset signal terminal and the first reference signal terminal. side independent settings.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, the reset circuit is further configured to provide the signal of the second reference signal terminal to the first node in response to the signal of the reset signal terminal , and provide the second reference signal at the first reference signal terminal to the driving signal output terminal, the level of the signal at the second reference signal terminal and the level of the second reference signal are the same as the first reference signal. The levels of the signals are opposite.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, the reset circuit includes: a second transistor, a third transistor and a fourth transistor, wherein,

The gate of the second transistor is coupled to the initial reset signal terminal, the first electrode of the second transistor is coupled to the second reference signal terminal, and the second electrode of the second transistor is coupled to the second reference signal terminal. the first node is coupled;

The gate of the third transistor is coupled to the reset signal terminal, the first electrode of the third transistor is coupled to the second reference signal terminal, and the second electrode of the third transistor is coupled to the second reference signal terminal. A node is coupled;

The gate of the fourth transistor is coupled to the reset signal terminal, the first electrode of the fourth transistor is coupled to the first reference signal terminal, and the second electrode of the fourth transistor is coupled to the driver signal output.

In some embodiments, the above-mentioned shift register provided by the embodiments of the present disclosure further includes at least one control circuit;

The control circuit is configured to control the level of the second node to be opposite to the level of the first node in response to the signal of the input signal terminal and the signal of the selection signal terminal, wherein the selection signal terminal, the second node The nodes are in one-to-one correspondence with the control circuit;

The drive output circuit is further configured to provide a second reference signal of the first reference signal terminal to the drive signal output terminal in response to the signal of the second node, the level of the second reference signal being the same as that of the drive signal output terminal. The level of the first reference signal is opposite.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, the control circuit includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

The gate of the fifth transistor and the first electrode of the fifth transistor are both coupled to the corresponding selection signal terminals, and the second electrode of the fifth transistor is coupled to the second electrode of the sixth transistor catch;

The gate of the sixth transistor is coupled to the first node, and the first electrode of the sixth transistor is coupled to the second reference signal terminal;

The gate of the seventh transistor is coupled to the input signal terminal, the first pole of the seventh transistor is coupled to the second reference signal terminal, and the second pole of the seventh transistor is connected to the corresponding the second node is coupled;

The gate of the eighth transistor is coupled to the corresponding second node, the first electrode of the eighth transistor is coupled to the second reference signal terminal, and the second electrode of the eighth transistor is coupled to the second node. The first node is coupled.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, the driving output circuit includes: a second capacitor, a ninth transistor, and a tenth transistor corresponding to the second node one-to-one, wherein ,

the second capacitor is coupled between the first node and the driving signal output end;

The gate of the ninth transistor is coupled to the first node, the first pole of the ninth transistor is coupled to the clock signal terminal, and the second pole of the ninth transistor is output to the driving signal end coupling;

The gate of the tenth transistor is coupled to the corresponding second node, the first electrode of the tenth transistor is coupled to the first reference signal terminal, and the second electrode of the tenth transistor is coupled to the first reference signal terminal. The driving signal output end is coupled.

In some embodiments, the above-mentioned shift register provided by the embodiments of the present disclosure further includes a cascade output circuit, configured to provide the signal of the clock signal terminal to the cascade in response to the signal of the first node A signal output terminal, and in response to the signal at the second node, providing a signal at the second reference signal terminal to the cascaded signal output terminal.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, the cascaded output circuit includes: an eleventh transistor and a twelfth transistor corresponding to the second node one-to-one, wherein,

The gate of the eleventh transistor is coupled to the first node, the first pole of the eleventh transistor is coupled to the clock signal terminal, and the second pole of the eleventh transistor is coupled to the clock signal terminal. The cascade signal output terminal is coupled;

The gate of the twelfth transistor is coupled to the corresponding second node, the first electrode of the twelfth transistor is coupled to the second reference signal terminal, and the second The pole is coupled to the cascaded signal output terminal.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, the input circuit includes a thirteenth transistor, and the gate of the thirteenth transistor and the first pole of the thirteenth transistor are both is coupled to the input signal terminal, and the second electrode of the thirteenth transistor is coupled to the first node.

Based on the same inventive concept, an embodiment of the present disclosure provides a gate driving circuit, including: a plurality of the above-mentioned shift registers provided by the embodiments of the present disclosure are cascaded;

The input signal terminal of the first stage shift register is coupled to the frame trigger signal terminal;

Except for the first stage shift register, the input signal terminals of the other stage shift registers are respectively coupled to the cascaded signal output terminals of the adjacent previous stage shift registers;

The drive signal output ends of the shift registers of all levels are connected to the gate lines of the corresponding row.

Based on the same inventive concept, an embodiment of the present disclosure provides a display device including the above-mentioned gate driving circuit provided by the embodiment of the present disclosure.

Based on the same inventive concept, an embodiment of the present disclosure provides a method for driving the above shift register, including:

In the input stage, the input circuit provides the signal of the input signal terminal to the first node in response to the signal of the input signal terminal;

In the output stage, the cascaded output circuit at least responds to the signal of the first node, and provides the signal of the clock signal terminal as the gate driving signal to the driving signal output terminal;

In the shutdown stage, the residual charge discharge circuit responds to the signal of the discharge signal terminal, and provides the first reference signal of the first reference signal terminal to the driving signal output terminal, and the level of the first reference signal is the same as that of the gate driving signal. the same level.

The beneficial effects of the present disclosure are as follows:

The shift register, the driving method thereof, the gate driving circuit and the display device provided by the embodiments of the present disclosure include an input circuit configured to provide the signal of the input signal terminal to the first node in response to the signal of the input signal terminal; the driving output circuit , at least configured to respond to the signal of the first node, provide the signal of the clock signal terminal as a gate drive signal to the drive signal output terminal; the residual charge discharge circuit is configured to respond to the signal of the discharge signal terminal, the first reference signal The first reference signal at the gate is provided to the driving signal output terminal, and the level of the first reference signal is the same as that of the gate driving signal. During the display time of each frame, the input circuit and the output circuit cooperate with each other to provide a gate driving signal for the output terminal of the driving signal, so that the gate driving signal is transmitted to the transistor in the display area through the gate line, and the transistor is controlled by the gate driving signal. Turn it on to charge the pixels and realize the screen display. By adding the residual charge discharge circuit, the first reference signal with the same level as the gate driving signal can be provided to the output terminal of the driving signal at the moment of shutdown, so that the first reference signal is transmitted to the transistor in the display area through the gate line, and the transistor is in the first Once it is turned on under the control of the reference signal, the residual charge in the transistor is fully released, so that when the screen needs to be displayed, abnormal display will not occur due to the residual charge.

Description of drawings

FIG. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure;

3 is a schematic diagram comparing the level curves of the drive signal output terminals before and after reliable operation provided by the embodiment of the present disclosure;

4 is a schematic diagram showing the comparison of the level curves of the drive signal output terminals before and after reliable operation in the related art;

FIG. 5 is a schematic structural diagram of a specific structure of a shift register provided by an embodiment of the present disclosure;

6 is a schematic diagram of another specific structure of a shift register provided by an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of another specific structure of a shift register provided by an embodiment of the present disclosure;

8 is a schematic diagram of another specific structure of a shift register provided by an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of another specific structure of a shift register provided by an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of another specific structure of a shift register provided by an embodiment of the present disclosure;

FIG. 11 is a schematic diagram of another specific structure of a shift register provided by an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of another specific structure of a shift register provided by an embodiment of the present disclosure;

FIG. 13 is a signal timing diagram provided by an embodiment of the present disclosure;

FIG. 14 is a working flowchart of a shift register provided by an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale, and are only intended to illustrate the present disclosure. And the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. As used in this disclosure and in the claims, "first," "second," and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. "Comprises" or "comprising" and similar words mean that the elements or things appearing before the word encompass the elements or things recited after the word and their equivalents, but do not exclude other elements or things. "Inner", "outer", "upper", "lower", etc. are only used to indicate the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

As shown in FIG. 1 , the display device may include a plurality of pixels arranged in an array, a plurality of gate lines (eg, G ₁ , G ₂ , G ₃ , G ₄ , etc.), and a plurality of data lines (eg, D ₁ , D ₂ , _D3 , etc.), and a gate drive circuit (GOA) composed of a plurality of shift registers arranged in cascade. Wherein, each pixel includes a plurality of sub-pixels SPX, a column of sub-pixels SPX corresponds to a data line, a row of pixels corresponds to a gate line, and a plurality of shift registers are coupled to each gate line in a one-to-one correspondence. In some embodiments, the pixels may include red sub-pixels, green sub-pixels and blue sub-pixels, so that red, green and blue colors can be mixed to realize color display. Alternatively, the pixels may also include red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels, so that red, green, blue and white can be mixed to achieve color display. Of course, in practical applications, the emission colors of the sub-pixels in the pixels can be designed and determined according to the actual application environment, which is not limited here.

However, after the reliability test of the display device in the related art, the driving signal output terminal cannot provide enough voltage to turn on the transistor in the display area to discharge the residual charge during the shutdown stage. The color of the solid color picture is abnormal, accompanied by poor horizontal lines.

In order to solve the above technical problems existing in the related art, an embodiment of the present disclosure provides a shift register, as shown in FIG. 2 , including:

The input circuit 101 is configured to provide the signal of the input signal terminal In to the first node Pu in response to the signal of the input signal terminal In;

The drive output circuit 102 is at least configured to provide the signal at the clock signal terminal Clk as a gate drive signal to the drive signal output terminal Gout in response to the signal at the first node Pu;

The residual charge discharge circuit 103 is configured to provide the first reference signal of the _first reference signal terminal Ref1 to the driving signal output terminal Gout in response to the signal of the discharge signal terminal V, and the level of the first reference signal is the same as that of the gate drive. The level of the signal is the same.

In the above-mentioned shift register provided by the embodiment of the present disclosure, during the display time of each frame, the input circuit 101 and the driving output circuit 102 cooperate with each other to provide a gate driving signal for the driving signal output terminal Gout, so that the gate driving signal passes through the gate The line is transmitted to the transistor in the display area (AA), and the transistor is turned on under the control of the gate driving signal to charge the pixel, so as to realize the picture display. By adding the residual charge discharge circuit 103, the driving signal output terminal Gout can be provided with a first reference signal with the same level as the gate driving signal at the moment of shutdown, so that the first reference signal is transmitted to the transistors in the display area through the gate lines, and the transistors It is turned on under the control of the first reference signal, and the residual charge in the transistor is fully released, so that when a picture needs to be displayed, abnormal display will not occur due to the residual charge.

FIG. 3 is a schematic diagram comparing the level curves of the driving signal output terminals before and after reliable operation according to an embodiment of the present disclosure; FIG. 4 is a schematic diagram comparing the level curves of the driving signal output terminals before and after reliable operation in the related art. The solid line in Fig. 3 and Fig. 4 represents the level curve of the output terminal of the driving signal before the reliable operation, and the dashed line represents the level curve of the output terminal of the driving signal after the reliable operation. It can be seen from FIG. 3 and FIG. 4 that after the reliable operation, the level of the driving signal terminal in the present disclosure is about 17v, which is only 3v lower than the 20v before the reliable operation, that is, only reduced by 6%; After operation, the level of the drive signal terminal is about 9v, which is 11v lower than the 20v before reliable operation, that is, 55% lower. Therefore, compared with the related art, the present disclosure has less influence on the level of the output terminal of the driving signal, which is beneficial to provide a sufficient voltage to turn on the transistors in the display area to fully discharge the residual charges.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, as shown in FIG. 5 to FIG. 12 , the discharge signal terminal V includes: at least one sub-discharge signal terminal (eg V_1, V_2, etc.), residual charge The discharge circuit 103 includes: sub-discharge circuits (eg, 103_1, 103_2, etc.) corresponding to the sub-discharge signal terminals (eg, V_1, V_2, etc.) one-to-one, and the sub-discharge circuits (eg, 103_1, 103_2, etc.) are configured to respond to the corresponding sub-discharge circuits (eg, 103_1, 103_2, etc.) The signals of the discharge signal terminals (eg V_1, V_2, etc.) provide the first reference signal to the driving signal output terminal Gout.

When there are multiple sub-discharge signal terminals (eg V_1, V_2, etc.), each sub-discharge signal terminal (eg V_1, V_2, etc.) can control each sub-discharge circuit (eg, 103_1, 103_2, etc.) to work at the same time, so that the first A reference signal is provided to the driving signal output terminal Gout under the multiple functions of the sub-discharge circuits (eg 103_1, 103_2, etc.), which can effectively ensure the level of the driving signal output terminal Gout, and is more conducive to controlling the full discharge of residual charges. In addition, since the more sub-discharge circuits (such as 103_1, 103_2, etc.), the more space they need to occupy, which is not conducive to the realization of a narrow frame design. Therefore, in order to take into account the residual charge release effect and the narrow frame, one or two can be set in the present disclosure. individual discharge circuits (eg 103_1 and/or 103_2).

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, as shown in FIG. 5 to FIG. 12 , each sub-discharge circuit (eg, 103_1 or 103_2 , etc.) includes: a first transistor M ₁ , a first transistor _The gate of M1 is coupled to the corresponding sub-discharge signal terminal (eg V_1 or V_2, etc.), the first electrode of the _first transistor M1 is coupled to the _first reference signal terminal Ref1, and the second terminal of the _first transistor M1 The pole is coupled to the driving signal output terminal Gout. In a specific implementation, the first transistor M1 is in _a conducting state in response to the signal of the corresponding sub-discharge signal terminal (eg V_1 or V_2, etc.), and the first reference signal of the _first reference signal terminal Ref1 is turned on through the first _The transistor M1 is provided to the driving signal output terminal Gout.

In some embodiments, in the above-mentioned display device provided by the embodiments of the present disclosure, as shown in FIG. 6 , FIG. 8 , FIG. 11 , and FIG. 12 , at least some of the sub-discharge circuits (eg, 103_1 , 103_2 , etc.) include the first transistor in addition to the first transistor. In addition to M ₁ , it may further include: a first capacitor C ₁ . In the same sub-discharge circuit (eg, 103_1 or 103_2 , etc.), the first capacitor C ₁ is coupled to the gate of the first transistor M ₁ and the first reference signal between terminals Ref ₁ . In a specific implementation, the bootstrap effect of the first capacitor C ₁ causes the gate voltage of the first transistor M ₁ to further increase compared to the first reference signal, for example, 1.5 times that of the first reference signal, which is beneficial to the first reference signal The signal is provided to the driving signal output terminal Gout more quickly at the moment of shutdown, so as to increase the release time of the residual charge and ensure that the residual charge is released more fully.

The above are only examples to illustrate the specific structures of the sub-discharge circuits (eg, 103_1 , 103_2 , etc.) provided by the embodiments of the present disclosure. During specific implementation, the specific structures of the sub-discharge circuits (eg, 103_1 , 103_2 , etc.) are not limited to those provided by the embodiments of the present disclosure. The above structure can also be other structures known to those skilled in the art, which are not limited here.

In some embodiments, the above-mentioned shift register provided by the embodiments of the present disclosure, as shown in FIG. 2 , FIG. 5 to FIG. 12 , may further include: a reset circuit 104 , at least configured to respond to the initial reset signal terminal TRst The signal of the second reference signal terminal Ref ₂ is provided to the first node Pu. Optionally, to save the number of signal terminals and simplify circuit design, at least some of the sub-discharge signal terminals (eg V_1, V_2, etc.) are multiplexed with the initial reset signal terminal TRst and/or the _first reference signal terminal Ref1. For example, all sub-discharge signal terminals (eg, V_1 and/or V_2, etc.) are multiplexed with the first reference signal terminal Ref ₁ ; or, all sub-discharge signal terminals (eg, V_1 and/or V_2, etc.) are multiplexed with the initial reset signal terminal TRst ; Or, when the number of sub-discharge signal terminals is multiple, some of the sub-discharge signal terminals (eg V_1) may be multiplexed with the initial reset signal terminal TRst, and the rest of the sub-discharge signal terminals (eg V_1) and the first reference signal terminal Ref ₁ is multiplexed; or, some of the sub-discharge signal terminals (for example, V_1 and/or V_2, etc.) are multiplexed with the initial reset signal terminal TRst and/or the first reference signal terminal Ref ₁ , and the rest of the sub-discharge signal terminals (not shown in the figure) are multiplexed. out) and the initial reset signal terminal TRst and the first reference signal terminal Ref ₁ are independently set. Of course, in some embodiments, all the sub-discharge signal terminals (such as V_1, V_2, etc.) can also be set independently from the initial reset signal terminal TRst and the first reference signal terminal Ref _1. In this case, the chip (IC ) uniformly load signals for each sub-discharge signal terminal (eg V_1, V_2, etc.), or set each sub-discharge signal terminal (eg V_1, V_2, etc.) in a floating state without loading any signal.

In addition, in the pre-frame stage and the post-frame stage of each frame display time t, the initial reset signal terminal TRst can output a signal with the same level as the shutdown stage. Therefore, in the pre-frame stage and the post-frame stage, the initial reset signal terminal TRst The sub-discharge circuits (eg, 103_1, 103_2, etc.) corresponding to the multiplexed sub-discharge signal terminals (eg, V_1, V_2, etc.) The output terminal Gout is discharged to prevent the residual charge of the output terminal Gout of the driving signal from affecting the normal display of the picture in the display area.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, as shown in FIG. 2 , FIG. 5 to FIG. 12 , the reset circuit 104 is further configured to, in response to the signal of the reset signal terminal Rst, reset the second The signal of the reference signal terminal Ref ₂ is provided to the first node Pu, and the second reference signal of the first reference signal terminal Ref ₁ is provided to the driving signal output terminal Gout, the level of the signal of the second reference signal terminal Ref ₂ , the first reference signal The levels of the two reference signals are opposite to those of the first reference signal. In this way, the first node Pu and the driving signal output terminal Gout can be reset through the reset circuit 104, thereby reducing the noise of the first node Pu and the driving signal output terminal Gout.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, as shown in FIG. 5 to FIG. 12 , the reset circuit 104 includes: a second transistor M ₂ , a third transistor M ₃ and a fourth transistor M ₄ , wherein the gate of the second transistor _M2 is coupled to the initial reset signal terminal TRst, the first pole of the _second transistor _M2 is coupled to the _second reference signal terminal Ref2, and the second pole of the second transistor M2 is coupled to the second reference signal terminal Ref2. The first node Pu is coupled; the gate of the _third transistor M3 is coupled to the reset signal terminal Rst, the first pole of the _third transistor M3 is coupled to the _second reference signal terminal Ref2, and the _third transistor M3 The diode is coupled to the first node Pu; the gate of the _fourth transistor M4 is coupled to the reset signal terminal Rst, the first electrode of the _fourth transistor M4 is coupled to the _first reference signal terminal Ref1, and the fourth transistor M4 is coupled to the reset signal terminal Rst. The second pole of ₄ is connected to the driving signal output terminal Gout.

In a specific implementation, the second transistor _M2 is in a conducting state in response to the signal of the initial reset signal terminal TRst, so that the signal of the _second reference signal terminal Ref2 is provided to the first node Pu through the second transistor _M2 that is turned on; The _third transistor M3 is in a conducting state in response to the signal of the reset signal terminal Rst, so that the signal of the _second reference signal terminal Ref2 is supplied to the first node Pu through the _third transistor M3 that is turned on; the _fourth transistor M4 responds to When the signal at the reset signal terminal Rst is in an on state, the second reference signal at the _first reference signal terminal Ref1 is provided to the driving signal output terminal Gout through the turned-on _fourth transistor M4.

The above is only an example to illustrate the specific structure of the reset circuit 104 provided by the embodiment of the present disclosure. During the specific implementation, the specific structure of the reset circuit 104 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be other structures known to those skilled in the art. The structure is not limited here.

In some embodiments, the above-mentioned shift register provided by the embodiments of the present disclosure, as shown in FIG. 2 to FIG. 10 , may further include at least one control circuit (eg 105_1 , 105_2 , etc.); control circuits (eg 105_1 , 105_2 , etc.) etc.) is configured to control the level of the second node (eg Pd_1, Pd_2, etc.) to be opposite to the level of the first node Pu in response to the signal of the input signal terminal In and the signal of the selection signal terminal (eg VN_1, VN_2, etc.), The selection signal terminals (eg VN_1, VN_2, etc.) and the second nodes (eg Pd_1, Pd_2, etc.) are in one-to-one correspondence with the control circuits (eg 105_1, 105_2, etc.); the drive output circuit 102 is also configured to respond to the second The signal of the node (such as Pd_1, _{Pd_2} , etc.) provides the second reference signal of the first reference signal terminal Ref1 to the driving signal output terminal Gout, and the level of the second reference signal is opposite to that of the first reference signal, so as to Noise reduction is performed on the driving signal output terminal Gout. Optionally, when there are multiple control circuits (such as 105_1, 105_2, etc.), each control circuit (such as 105_1 or 105_2, etc.) can work alternately at different times, so as to prolong the life of the control circuits (such as 105_1 or 105_2, etc.) , two control circuits (eg, 105_1 or 105_2 ) are used as examples for schematic illustration in the drawings of the present disclosure.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, as shown in FIG. 5 to FIG. 12 , each control circuit (eg, 105_1 or 105_2 , etc.) includes: a fifth transistor M ₅ , a sixth transistor M ₆ , the seventh transistor M ₇ and the eighth transistor M ₈ ; the gate of the fifth transistor M ₅ and the first pole of the fifth transistor M ₅ are all coupled to the corresponding selection signal terminals (eg VN_1 or VN_2, etc.), The second pole of the _fifth transistor M5 is coupled to the second pole of the _sixth transistor _M6 ; the gate of the sixth transistor M6 is coupled to the first node Pu, and the first pole of the _sixth transistor M6 is connected to the second pole The reference signal terminal Ref ₂ is coupled; the gate of the seventh transistor M ₇ is coupled to the input signal terminal In, the first pole of the seventh transistor M ₇ is coupled to the second reference signal terminal Ref ₂ , and the seventh transistor M ₇ The second pole is coupled to the corresponding second node (eg Pd_1 or Pd_2, etc.); the gate of the _eighth transistor M8 is coupled to the corresponding second node (eg Pd_1 or Pd_2, etc.), and the gate of the _eighth transistor M8 One pole is coupled to the second reference signal terminal Ref2, and the _second pole of the _eighth transistor M8 is coupled to the first node Pu.

In a specific implementation, each _sixth transistor M6 is in a conducting state in response to the signal of the first node Pu, so that the signal of the _second reference signal terminal Ref2 is respectively provided to the corresponding second through the _sixth transistor M6 that is turned on node (for example, Pd_1, Pd_2, etc.); at the same time, each _seventh transistor M7 is in a conducting state in response to the signal of the input signal terminal In, so that the signal of the _second reference signal terminal Ref2 is respectively provided through the conducting _seventh transistor M7 To the corresponding second node (such as Pd_1, Pd_2, etc.); in response to the signal of the corresponding selection signal terminal (such as VN_1 or VN_2, etc.), only one of the _fifth transistors M5 is in a conducting state, and the corresponding selection signal terminal (for example, VN_1 or VN_2, etc.) is provided to the corresponding second node (for example, Pd_1 or Pd_2, etc.), but because the sixth transistor _M6 and the _seventh transistor M7 simultaneously provide the signal of the second reference signal terminal Ref ₂ to The second node (eg Pd_1 or Pd_2 etc.), therefore, the level of the second node (eg Pd_1 or Pd_2 etc.) ultimately depends on the signal of the second reference signal terminal Ref ₂ and is opposite to the level of the first node Pu. Each eighth transistor M8 is in an off state under the control of the second node (eg, Pd_1, _{Pd_2} , etc.).

In addition, in response to the signal of the corresponding selection signal terminal (for example, VN_1 or VN_2, etc.), only one of the _fifth transistors M5 is in a conducting state, and the signal of the corresponding selection signal terminal (for example, VN_1 or VN_2, etc.) is provided to the corresponding the second node (eg Pd_1 or Pd_2, etc.), and both the sixth transistor _M6 and the _seventh transistor M7 are in the off state, one of the _eighth transistors M8 is at the second node (eg Pd_1 or Pd_2, etc.) Under control, it is in an on state, and the signal of the second reference signal terminal Ref ₂ is provided to the first node Pu through the turned on eighth transistor M ₈ .

The above is only an example to illustrate the specific structure of the control circuit (for example, 105_1 or 105_2, etc.) provided by the embodiment of the present disclosure. During specific implementation, the specific structure of the control circuit (for example, 105_1 or 105_2, etc.) is not limited to the above-mentioned provided by the embodiment of the present disclosure. The structure may also be other structures known to those skilled in the art, which are not limited here.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, as shown in FIG. 5 to FIG. 12 , the drive output circuit 102 may include: a second capacitor C ₂ , a ninth transistor M ₉ , and a second capacitor C 2 , a ninth transistor M 9 , and a Two nodes (eg Pd_1, Pd_2, etc.) one-to-one corresponding tenth transistor M ₁₀ , wherein the second capacitor C ₂ is coupled between the first node Pu and the driving signal output end Gout; the gate of the ninth transistor M ₉ is coupled to the first node Pu, the first pole of the _ninth transistor M9 is coupled to the clock signal terminal Clk, the second pole of the _ninth transistor M9 is coupled to the driving signal output terminal Gout; the gate of the _tenth transistor M10 The pole is coupled to the corresponding second node (eg Pd_1, Pd_2, etc.), the _first pole of the _tenth transistor M10 is coupled to the first reference signal terminal Ref1, and the second pole of the _tenth transistor M10 is connected to the driving signal output The terminal Gout is coupled.

In a specific implementation, the _ninth transistor M9 is in a conducting state in response to the signal of the first node Pu, so that the signal of the clock signal terminal Clk is provided to the driving signal output terminal Gout through the _ninth transistor M9 that is turned on. During this process , the bootstrap effect of the second capacitor C ₂ can maintain the level of the first node Pu. In response to the signal of the corresponding second node (for example, Pd_1, Pd_2, etc.), only _one of the _tenth transistors M10 is in a conducting state, passing the first reference signal or the second reference signal of the first reference signal terminal Ref1 through The turned-on _tenth transistor M10 is supplied to the driving signal output terminal Gout.

5 to 13 , in the shutdown stage T, the first reference signal of the first reference signal terminal Ref ₁ is provided to the driving signal output terminal Gout through the turned-on tenth transistor M ₁₀ and the first transistor M ₁ . Since the first reference signal is only provided for the driving signal output terminal Gout through the _first transistor M1, the residual charge in the display area can be better released, and the display quality can be further improved. Moreover, it should be understood that each _tenth transistor M10 is turned on alternately at the second node (for example, Pd_1, Pd_2, etc.). Therefore, the greater the number of _tenth transistors M10 is, the more tenth transistors M10 are in one frame time. The shorter the on-time of the transistor M10 is, the more favorable it is to maintain the stable characteristics of the _tenth transistor _M10 and reduce the risk of drift of the curve characteristic of the _tenth transistor M10. However, many tenth transistors M ₁₀ are not conducive to narrow frame design. Therefore, in order to take into account the performance stabilization effect of the tenth transistor M ₁₀ and the narrow frame, two or three tenth transistors M ₁₀ may be provided in the present disclosure.

The above is only an example to illustrate the specific structure of the driving output circuit 102 provided by the embodiment of the present disclosure. During specific implementation, the specific structure of the driving output circuit 102 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and can also be known by those skilled in the art. Other structures are not limited here.

In some embodiments, the above-mentioned shift register provided by the embodiments of the present disclosure, as shown in FIG. 2 , FIG. 5 to FIG. 12 , may further include a cascaded output circuit 106 configured to respond to the output of the first node Pu. signal, the signal of the clock signal terminal Clk is provided to the cascade signal output terminal Cout, and the signal of the second reference signal terminal Ref ₂ is provided to the cascade signal output in response to the signal of the second node (eg Pd_1, Pd_2, etc.) terminal Cout. The cascaded output of the shift register of the current stage to the shift register of the lower stage can be realized by the cascaded output circuit 106 .

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, as shown in FIG. 5 to FIG. 12 , the cascaded output circuit 106 may include: an eleventh transistor M ₁₁ , and a second node (eg, Pd_1, Pd_2, etc.) one-to-one corresponding twelfth transistors M ₁₂ , wherein the gate of the eleventh transistor M ₁₁ is coupled to the first node Pu, and the first pole of the eleventh transistor M ₁₁ is connected to the clock signal terminal Clk Coupling, the second pole of the _eleventh transistor M11 is coupled to the cascade signal output terminal Cout; the gate of the _twelfth transistor M12 is coupled to the corresponding second node (eg Pd_1 or Pd_2, etc.), the tenth _The first poles of the two transistors M12 are coupled to the second reference signal terminal Ref2, and the _second poles of the _twelfth transistor M12 are coupled to the cascade signal output terminal Cout.

In a specific implementation, the _eleventh transistor M11 is in a conducting state in response to the signal of the first node Pu, and the signal of the clock signal terminal Clk is provided to the cascade signal output terminal Cout through the conducting _eleventh transistor M11, so as to The input signal provided by the lower-level shift register; the twelfth transistor M ₁₂ is in a conducting state in response to the signal corresponding to the second node (eg, Pd_1 or Pd_2, etc.), and the signal of the second reference signal terminal Ref ₂ passes through the conducting tenth _The two transistors M12 are provided to the cascaded signal output terminal Cout, so as to perform noise reduction on the cascaded signal output terminal Cout.

The above is only an example to illustrate the specific structure of the cascaded output circuit 106 provided by the embodiment of the present disclosure. During specific implementation, the specific structure of the cascaded output circuit 106 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be a technology in the art. Other structures known to personnel are not limited here.

In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, as shown in FIG. 5 to FIG. 12 , the input circuit 101 includes a thirteenth transistor M ₁₃ , the gate of the thirteenth transistor M ₁₃ , the The first electrodes of the _thirteenth transistors M13 are all coupled to the input signal terminal In, and the second electrodes of the _thirteenth transistors M13 are coupled to the first node Pu. In a specific implementation, the _thirteenth transistor M13 is in a conducting state in response to the signal of the input signal terminal In, and the signal of the input signal terminal In is provided to the first node Pu through the conducting _thirteenth transistor M13.

The above is only an example to illustrate the specific structure of the input circuit 101 provided by the embodiment of the present disclosure. During specific implementation, the specific structure of the input circuit 101 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be other structures known to those skilled in the art. The structure is not limited here.

In order to reduce the manufacturing process, in the specific implementation, in the shift register provided by the embodiments of the present disclosure, all transistors can be set as N-type transistors, and the N-type transistors are turned on under the action of a high-level signal (VGH), and when a low-level signal is used, the N-type transistors are turned on. Cut off under the action of the level signal (VGL). Correspondingly, the first reference signal of the first reference signal terminal Ref ₁ may be a DC high level signal (VGH), and the second reference signal of the first reference signal terminal Ref ₁ may be a DC low level signal (VGL) , the signal of the second reference signal terminal Ref ₂ may be a DC low level signal (VGL). In some embodiments, the signal of the second reference signal terminal Ref ₂ can be made smaller than the second reference signal, which is beneficial to turn off the transistors in the display area as completely as possible.

Of course, in some embodiments, all transistors provided in the present disclosure may also be P-type transistors, and the P-type transistors are turned off under the action of a high-level signal (VGH) and turned on under the action of a low-level signal (VGL). Correspondingly, the first reference signal of the first reference signal terminal Ref ₁ may be a DC low level signal (VGL), and the second reference signal of the first reference signal terminal Ref ₁ may be a DC high level signal (VGH) , the signal of the second reference signal terminal Ref ₂ may be a DC high level signal (VGH). In some embodiments, the signal of the second reference signal terminal Ref ₂ can be made larger than the second reference signal, which is beneficial to turn off the transistors in the display area as completely as possible.

It should be noted that the above-mentioned transistors provided in the embodiments of the present disclosure may be thin film transistors (TFT, ThinFilm Transistor) or metal oxide semiconductor field effect transistors (MOS, Metal Oxide Scmiconductor), which is not limited herein. In a specific implementation, the gate of the above transistor may be the gate, the first electrode may be the source electrode, and the second electrode may be the drain electrode, or the first electrode may be the drain electrode and the second electrode may be the source electrode.

In specific implementation, taking two selection signal terminals (eg VN_1 and VN_2 ) as an example, the signals of the two selection signal terminals (eg VN_1 and VN_2 ) can be pulse signals switched at high level and low level respectively, and the two The levels of the selection signal terminals (eg, VN_1 and VN_2 ) are opposite. In some embodiments, the signals of the two selection signal terminals (eg VN_1 and VN_2 ) may also be DC signals respectively, and when one selection signal terminal is loaded with a high-level DC signal, the other selection signal terminal is not loaded with a signal Or load a low-level DC signal.

In the following, each transistor is an N-type transistor, and the structure of the shift register shown in FIG. 5 is taken as an example, combined with the signal timing diagram shown in FIG. detailed description. In the following description, 1 represents a high-level signal, and 0 represents a low-level signal, wherein 1 and 0 represent its logic levels, which are only for better explanation of the working process of the above-mentioned shift register provided by the embodiments of the present disclosure. rather than the potential applied to the gate of each transistor during implementation. Specifically, the display time t of each frame and the shutdown stage T in the working sequence diagram shown in FIG. 13 are used as examples for detailed description. And in order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the description of the transistors in the off state at each stage.

In some embodiments, each frame display time t may include a reset phase, an input phase, an output phase, and a reset phase.

In the reset phase, In=0, Clk=0, TRst=1, Rst=0, VN_1=1, VN_2=0, Ref ₁ =0, Ref ₂ =0.

The first transistor M1 is in _a conducting state in response to the high-level signal of the initial reset signal terminal _TRst , and provides the low-level signal of the first reference signal terminal Ref1 to the driving signal output terminal to reset the driving signal output terminal. . The second transistor _M2 is in a conducting state in response to the high-level signal at the initial reset signal terminal TRst, and the low-level signal at the first signal terminal VGL is provided to the first node Pu through the second transistor _M2 that is turned on, so as to realize the The reset of the pull-up node Pu. A fifth transistor M5 provides a high-level signal corresponding to the selection signal terminal (eg VN_1) to the corresponding second node (eg _{Pd_1} ) in response to the high-level signal conduction state of the selection signal terminal (eg VN_1), The corresponding _eighth transistor M8 is controlled to be in an on state, and the low-level signal of the _second reference signal terminal Ref2 is provided to the first node Pu through the turned-on _eighth transistor M8, so as to reset the first node Pu .

In the input stage, In=1, Clk=0, TRst=0, Rst=0, VN_1= ₁ , VN_2= ₀ , Ref1=0, Ref2=0.

The _thirteenth transistor M13 is in a conducting state in response to the high-level signal of the input signal terminal In, and the high-level signal of the input signal terminal In is provided to the first node Pu through the conducting _thirteenth transistor M13; The _six transistors M6 are in a conducting state in response to the high-level signal of the first node Pu, so that the low-level signal of the _second reference signal terminal Ref2 is respectively provided to the corresponding second node through the _sixth transistor M6 that is turned on (eg Pd_1, Pd_2, etc.); at the same time, each _seventh transistor M7 is in a conducting state in response to the high-level signal of the input signal terminal In, so that the low-level signal of the _second reference signal terminal Ref2 passes through the conducting seventh transistor The transistors M7 are respectively provided to the corresponding second nodes (eg Pd_1, _{Pd_2} , etc.); in response to the high level signal of the corresponding selection signal terminal (eg VN_1), the corresponding _fifth transistor M5 is turned on, and the selection The high level signal of the signal terminal (eg VN_1) is provided to the corresponding second node (eg Pd_1, etc.), but the sixth transistor _M6 and the _seventh transistor M7 convert the low level signal of the second reference signal terminal Ref2 to the corresponding _second node (eg Pd_1, etc.) Provided to the second node (eg Pd_1, Pd_2, etc.), therefore, the level of the second node (eg Pd_1, Pd_2, etc.) ultimately depends on the low-level signal of the second reference signal terminal Ref ₂ .

In the output stage, In=0, Clk=1, TRst=0, Rst=0, VN_1=1, VN_2=0, Ref ₁ =0, Ref ₂ =0.

The _ninth transistor M9 is in a conducting state in response to the high-level signal of the first node Pu, so that the high-level signal of the clock signal terminal Clk is provided to the driving signal output terminal Gout through the _ninth transistor M9 that is turned on, as the current The stage shift register corresponds to the gate driving signal of the gate line. During this process, the bootstrap effect of the second capacitor C ₂ can maintain the high level of the first node Pu. The _eleventh transistor M11 is turned on in response to the high-level signal of the first node Pu, and the high-level signal of the clock signal terminal Clk is provided to the cascade signal output terminal Cout through the _eleventh transistor M11 that is turned on, Input signal for the lower-level shift register.

In the reset phase, In=0, TRst ₌ 0, Rst= ₁ , Ref1=0, Ref2=0, the two selection signal terminals (eg VN_1 and VN_2) are alternately 1, and Clk is alternately 1 and 0.

The _third transistor M3 is in a conducting state in response to the high-level signal of the reset signal terminal Rst, and the low-level signal of the first signal terminal VGL is supplied to the first node Pu through the turned-on _third transistor M3. In response to the high level signal of the selection signal terminal (eg VN_1 or VN_2), a _fifth transistor M5 is turned on, and provides the high level signal corresponding to the selection signal terminal (eg VN_1 or VN_2) to the corresponding second node (eg Pd_1 or Pd_2), control the corresponding _eighth transistor M8 to be in a conducting state, and the low-level signal of the second reference signal terminal Ref ₂ is provided to the first node Pu through the _eighth transistor M8 that is turned on; at the same time, controlling The corresponding _tenth transistor M10 is in a conducting state, and the low-level signal of the second reference signal terminal Ref ₂ is provided to the driving signal output terminal Gout through the _tenth transistor M10 that is turned on; in addition, the twelfth pair of _The transistor M12 is in a conducting state, and the low-level signal of the _second reference signal terminal Ref2 is provided to the cascade signal output terminal Cout through the conducting _twelfth transistor M12. The _fourth transistor M4 is turned on in response to the high level signal of the reset signal terminal Rst, and the low level signal of the _first reference signal terminal Ref1 is supplied to the driving signal output terminal Gout through the turned on _fourth transistor M4.

In the shutdown phase T, In=1, Clk=1, TRst=1, Rst=0, Ref ₁ =1, Ref ₂ =0, VN_1=1, VN_2=1.

The first transistor M1 is in _a conducting state in response to the high level signal of the sub-discharge signal terminal (for example, V_1, multiplexed with the initial reset signal terminal TRst), and the high level of the _first reference signal terminal Ref1 is turned on by the first transistor M1. _A transistor M1 is provided to the driving signal output terminal Gout to control the transistors in the display area to be turned on and discharge residual charges. The _thirteenth transistor M13 is in a conducting state in response to the high-level signal of the input signal terminal In, and the high-level signal of the input signal terminal In is supplied to the first node Pu through the conducting _thirteenth transistor M13, but the The second transistor _M2 is in a conducting state in response to the high-level signal of the initial reset signal terminal TRst, and the low-level signal of the first signal terminal VGL is supplied to the first node Pu through the second transistor _M2 that is turned on, resulting in the first Node Pu cannot be at high potential. In response to the high-level signals of the input signal terminal In and the selection signal terminals (eg VN_1, VN_2), each _fifth transistor M5 is turned on, and the high-level signals corresponding to the selection signal terminals (eg VN_1, VN_2) are provided to The corresponding second node (eg Pd_1, Pd_2), but each _seventh transistor M7 is in a conducting state in response to the high-level signal of the input signal terminal In, so that the low-level signal of the _second reference signal terminal Ref2 passes through the conduction. The turned-on _seventh transistors M7 are respectively provided to the corresponding second nodes (eg Pd_1 , Pd_2 , etc.), so that the second nodes (eg Pd_1 , Pd_2 , etc.) cannot be at a high potential.

It should be noted that, after the shutdown stage T, the input signal terminal In, the clock signal terminal Clk, the initial reset signal terminal TRst, the reset signal terminal Rst, the first reference signal terminal Ref ₁ , the second reference signal terminal Ref ₂ , the selection signal The terminals (eg VN_1, VN_2, etc.) are all kept as the ground signal GND.

It can be seen from the above description that the sub-discharge signal terminal (eg V_1) multiplexed with the initial reset signal terminal TRst is a low-level signal in the input stage, output stage and reset stage, and the _first transistor M1 is in an off state. Therefore, the first transistor M1 is in an off state. _A transistor M1 will not affect the display quality; and, in the reset stage, the initial reset signal terminal TRst is a high-level signal, and the _first transistor M1 is in a conducting state, which can reduce noise on the driving output signal terminal Gout, thereby facilitating Improve display quality. In addition, since the gate potential of the _first transistor M1 is a low-level signal during most of the display time t of each frame, the characteristic curve of the _first transistor M1 is less likely to drift, so that the first transistor M can be maintained. The threshold voltage (V _th ) of ₁ solves the problem that the threshold voltage of the first transistor M ₁ cannot provide sufficient potential for the driving signal output terminal Gout, which may affect the discharge of residual charges in the display area.

In some embodiments, the present disclosure also provides descriptions of the working processes of the shift registers shown in FIG. 6 to FIG. 12 . The following only describes the operation of the shift registers shown in FIGS. 6 to 12 and the shift register shown in FIG. 5 . The differences in the process will be introduced, and the similarities will not be repeated.

For example, in FIG. 6 , FIG. 11 and FIG. 12 , when the first transistor M1 is in _an on state in response to the signal of the initialization signal terminal TRst, the first transistor M1 is coupled between the gate and the _first electrode of the first transistor M1 The first capacitor C ₁ in between can increase the gate potential of the first transistor M ₁ due to the bootstrap effect, so that the first transistor M ₁ is more fully turned on.

In FIG. 7 , FIG. 8 and FIG. 10 , the sub-discharge signal terminal (eg V_1 or V_2 ) can be provided with a signal or not loaded with a signal for the sub-discharge signal terminal (eg V-1 or V_2 ) through the chip, and, in order not to Influence display, in each frame time t, the signal of the sub-discharge signal terminal (eg V-1 or V_2) needs to be smaller than the low-level signal of the _first reference signal terminal Ref1.

In addition, in FIG. 8 and FIG. 11 , for the first transistor M ₁ corresponding to the sub-discharge signal terminal (eg V_1 or V_2 ) through the chip alone, a first capacitor is coupled between its gate and the first electrode C ₁ . When the _first transistor M1 is in an on state, the gate potential of the _first transistor M1 can be increased due to the bootstrap effect of the first capacitor _C1 , so that the _first transistor M1 is more fully turned on.

In FIG. 9 and FIG. 12 , the sub-discharge signal terminal (eg V_1 or V_2 ) is multiplexed with the first reference signal terminal Ref ₁ , so that the corresponding first transistor M ₁ can respond to the first reference signal terminal Ref ₁ in the shutdown stage T In the on state, the first reference signal of the first reference signal terminal Ref ₁ is provided to the driving signal output terminal Gout, and the residual charge in the display area is released; and within the display time t of each frame, because the first reference signal terminal Ref ₁ always outputs a low level signal, therefore, the first transistor M ₁ is in an off state during the display time t of each frame, which will not affect the display effect.

Based on the same inventive concept, an embodiment of the present disclosure also provides a method for driving the above shift register, as shown in FIG. 14 , including the following steps:

S1401. In the input stage, the input circuit responds to the signal at the input signal end and provides the signal at the input signal end to the first node;

S1402. In the output stage, the cascaded output circuit at least responds to the signal of the first node, and provides the signal of the clock signal terminal as the gate driving signal to the driving signal output terminal;

S1403 , in the shutdown stage, the residual charge discharge circuit responds to the signal at the discharge signal terminal, and provides the first reference signal at the first reference signal terminal to the drive signal output terminal. The level of the first reference signal is the same as that of the gate drive signal.

Based on the same inventive concept, an embodiment of the present disclosure provides a gate driving circuit, including: a plurality of the above-mentioned shift registers in cascade;

The input signal terminal of the first stage shift register is coupled to the frame trigger signal terminal;

Except for the first stage shift register, the input signal terminals of the other stages of shift registers are respectively coupled to the cascaded signal output terminals of the adjacent previous stage shift registers;

The drive signal output ends of the shift registers of all levels are connected to the gate lines of the corresponding row.

In some embodiments, in order to simplify the circuit design, the structures of the shift registers of all levels in the gate driving circuit provided by the present disclosure are the same, and the connection relationship between the shift registers of all levels and the signal terminals is also the same. For details, please refer to the above content. Repeat will not be repeated here.

In some embodiments, in the gate driving circuit provided by the embodiments of the present disclosure, four clock signal lines may be used to provide clock signals for the gate driving circuit, optionally, k is a positive integer, and the (4k-3)th stage The clock signal terminals Clk of the shift register unit are all electrically connected to the first clock signal line clk ₁ , and the clock signal terminals Clk of the (4k-2)th stage shift register unit are all electrically connected to the second clock signal line clk ₂ , the clock signal terminals Clk of the (4k-1) stage shift register unit are all electrically connected to the third clock signal line clk ₃ , and the clock signal terminals Clk of the 4k stage shift register unit are both electrically connected to the fourth clock signal line clk ₄ is electrically connected. Optionally, the clock signal provided by the first clock signal line clk ₁ , the clock signal provided by the second clock signal line clk ₂ , the clock signal provided by the third clock signal line clk ₃ , and the fourth clock signal line clk ₄ The provided clock signals can be sequentially shifted by 1/2 phase.

In some embodiments, in the gate driving circuit provided by the embodiments of the present disclosure, the first reference signal terminal Ref ₁ of each stage of the shift register is electrically connected to the same first reference line, and the The second reference signal terminals Ref ₂ are all electrically connected to the same second reference line, and the initial reset signal terminal TRst of each stage of the shift register is electrically connected to the same initial reset line.

Based on the same inventive concept, an embodiment of the present disclosure further provides a display device including the above gate driving circuit provided by the embodiment of the present disclosure. In some embodiments, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, etc. . The display device includes but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply and other components. In addition, those skilled in the art can understand that the above structure does not constitute a limitation on the above-mentioned display device provided by the embodiment of the present disclosure. In other words, the above-mentioned display device provided by the embodiment of the present disclosure may include more or less of the above-mentioned components, or a combination of certain components, or a different arrangement of components. Although the present disclosure has described the preferred embodiments, it should be understood that various changes and modifications can be made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit and scope of the embodiments of the present disclosure. Thus, provided that these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to cover such modifications and variations.

Claims (16)

1. A shift register, comprising:

an input circuit configured to supply a signal of an input signal terminal to a first node in response to a signal of the input signal terminal;

a driving output circuit at least configured to provide a signal of a clock signal terminal as a gate driving signal to a driving signal output terminal in response to a signal of the first node;

a residual charge discharging circuit configured to provide a first reference signal of a first reference signal terminal to the driving signal output terminal in response to a signal of a discharging signal terminal, a level of the first reference signal being the same as a level of the gate driving signal.

2. The shift register of claim 1, wherein the discharge signal terminal comprises: at least one sub-discharge signal terminal, the residual charge discharging circuit comprising: sub-discharge circuits in one-to-one correspondence with the sub-discharge signal terminals, the sub-discharge circuits being configured to supply the first reference signal to the driving signal output terminal in response to a signal of the corresponding sub-discharge signal terminal.

3. The shift register of claim 2, wherein the sub-discharge circuit comprises: a gate of the first transistor is coupled to the corresponding sub-discharge signal terminal, a first pole of the first transistor is coupled to the first reference signal terminal, and a second pole of the first transistor is coupled to the driving signal output terminal.

4. The shift register of claim 3, wherein at least some of the sub-discharge circuits further comprise: and a first capacitor, wherein in the same sub-discharge circuit, the first capacitor is coupled between the gate of the first transistor and the first reference signal terminal.

5. The shift register according to any one of claims 2 to 4, further comprising: a reset circuit configured to supply a signal of a second reference signal terminal to the first node at least in response to a signal of an initial reset signal terminal;

at least part of the sub-discharge signal terminals are multiplexed with the initial reset signal terminal and/or the first reference signal terminal, or all the sub-discharge signal terminals are independently arranged with the initial reset signal terminal and the first reference signal terminal.

6. The shift register of claim 5, wherein the reset circuit is further configured to supply a signal of the second reference signal terminal to the first node and supply a second reference signal of the first reference signal terminal to the driving signal output terminal in response to a signal of a reset signal terminal, a level of the signal of the second reference signal terminal and a level of the second reference signal being opposite to a level of the first reference signal.

7. The shift register of claim 6, wherein the reset circuit comprises: a second transistor, a third transistor, and a fourth transistor, wherein,

a gate of the second transistor is coupled to the initial reset signal terminal, a first pole of the second transistor is coupled to the second reference signal terminal, and a second pole of the second transistor is coupled to the first node;

a gate of the third transistor is coupled to the reset signal terminal, a first pole of the third transistor is coupled to the second reference signal terminal, and a second pole of the third transistor is coupled to the first node;

a gate of the fourth transistor is coupled to the reset signal terminal, a first pole of the fourth transistor is coupled to the first reference signal terminal, and a second pole of the fourth transistor is coupled to the driving signal output terminal.

8. The shift register according to any one of claims 1 to 4, 6 and 7, further comprising at least one control circuit;

the control circuit is configured to respond to a signal of the input signal terminal and a signal of a selection signal terminal, and control the level of a second node to be opposite to the level of the first node, wherein the selection signal terminal and the second node are in one-to-one correspondence with the control circuit;

the driving output circuit is further configured to provide a second reference signal of the first reference signal terminal to the driving signal output terminal in response to a signal of the second node, the second reference signal having a level opposite to that of the first reference signal.

9. The shift register of claim 8, wherein the control circuit comprises: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

a gate of the fifth transistor and a first pole of the fifth transistor are both coupled to the corresponding selection signal terminal, and a second pole of the fifth transistor is coupled to a second pole of the sixth transistor;

a gate of the sixth transistor is coupled to the first node, and a first pole of the sixth transistor is coupled to the second reference signal terminal;

a gate of the seventh transistor is coupled to the input signal terminal, a first pole of the seventh transistor is coupled to the second reference signal terminal, and a second pole of the seventh transistor is coupled to the corresponding second node;

a gate of the eighth transistor is coupled to the corresponding second node, a first pole of the eighth transistor is coupled to the second reference signal terminal, and a second pole of the eighth transistor is coupled to the first node.

10. The shift register of claim 8, wherein the drive output circuit comprises: a second capacitor, a ninth transistor, and a tenth transistor in one-to-one correspondence with the second node, wherein,

the second capacitor is coupled between the first node and the driving signal output end;

a gate of the ninth transistor is coupled to the first node, a first pole of the ninth transistor is coupled to the clock signal terminal, and a second pole of the ninth transistor is coupled to the driving signal output terminal;

a gate of the tenth transistor is coupled to the corresponding second node, a first pole of the tenth transistor is coupled to the first reference signal terminal, and a second pole of the tenth transistor is coupled to the driving signal output terminal.

11. The shift register of claim 8, further comprising a cascade output circuit configured to supply a signal of the clock signal terminal to a cascade signal output terminal in response to a signal of the first node, and to supply a signal of a second reference signal terminal to the cascade signal output terminal in response to a signal of the second node.

12. The shift register of claim 11, wherein the cascade output circuit comprises: an eleventh transistor, and a twelfth transistor in one-to-one correspondence with the second node, wherein,

a gate of the eleventh transistor is coupled to the first node, a first pole of the eleventh transistor is coupled to the clock signal terminal, and a second pole of the eleventh transistor is coupled to the cascade signal output terminal;

a gate of the twelfth transistor is coupled to the corresponding second node, a first pole of the twelfth transistor is coupled to the second reference signal terminal, and a second pole of the twelfth transistor is coupled to the cascade signal output terminal.

13. A shift register as claimed in any one of claims 1 to 4, 6, 7 and 9 to 12, wherein said input circuit includes a thirteenth transistor, a gate of said thirteenth transistor, a first pole of said thirteenth transistor being coupled to said input signal terminal, a second pole of said thirteenth transistor being coupled to said first node.

14. A gate drive circuit, comprising: a plurality of cascaded shift registers as claimed in any one of claims 1 to 13;

the input signal end of the first stage shift register is coupled with the frame trigger signal end;

except the first stage shift register, the input signal ends of the other shift registers are respectively coupled with the cascade signal output end of the adjacent shift register of the previous stage;

and the driving signal output end of each stage of shift register is connected with the grid line of the corresponding row.

15. A display device comprising the gate driver circuit according to claim 14.

16. A method of driving a shift register according to any one of claims 1 to 13, comprising:

an input stage, wherein an input circuit responds to a signal of an input signal end and provides the signal of the input signal end to a first node;

in the output stage, the cascade output circuit at least responds to the signal of the first node and provides the signal of the clock signal end as a grid drive signal to a drive signal output end;

in the shutdown stage, the residual charge releasing circuit responds to a signal of a discharging signal end and provides a first reference signal of a first reference signal end to the driving signal output end, and the level of the first reference signal is the same as that of the grid driving signal.

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