CN114880266A - Fault processing method and device, computer equipment and storage medium - Google Patents

Abstract

The present application relates to the field of electronic digital data processing in the Internet industry, and discloses a fault handling method, device, computer equipment and storage medium. The method includes: in response to detecting a failure of an embedded processor in the data processor, entering a pickup mode, wherein the pickup mode includes sending a hot-plug interrupt signal to a computer host to isolate the computer host from the embedded processor failure , the hot-plug interrupt signal is used to indicate that the embedded processor has performed a hot-plug operation; in response to detecting that the embedded processor has been repaired, send a hot-plug signal to the computer host to exit the pickup mode to complete fault recovery. The plug signal is used to indicate that the embedded processor has performed a hot plug operation. By implementing the embodiments of the present application, fault isolation can be effectively achieved, the computer host does not need to be restarted, the impact on the computer host can be minimized, and the normal operation of the computer host can be ensured.

Description

Method, apparatus, computer equipment and storage medium for troubleshooting

technical field

The present application relates to the field of electronic digital data processing in the Internet industry, and in particular, to a method, device, computer equipment and storage medium for troubleshooting.

Background technique

With the rapid development of data centers, communication capabilities and computing capabilities have become two important development directions of data center infrastructure that complement each other. If the data center only pays attention to the improvement of computing power, and the improvement of communication infrastructure cannot keep up, the overall system performance of the data center is still limited and cannot reach its true potential. In order to cope with the increasingly large and complex data volume, the data processing unit (DPU) came into being.

The data processor is located in the cooperative processing unit, which is an implementation of the idea of separating the data plane and the control plane. It cooperates with the central processing unit (CPU), the latter is responsible for general control, and the former focuses on data processing. That is, data processors can offload data processing/preprocessing from the central processor while distributing computing power closer to where the data occurs, reducing traffic. Since data processors need to move computations close to the data, this also means higher demands on the reliability and availability of data processors. In order to meet the network requirements for large data transmission, the data processor needs to use a high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) interface for data transmission. Therefore, the data processor is usually involved in the failure of the PCIe device, and the data processor system is required to assist the PCIe device in failure recovery.

At present, the data processor will simulate a PCIe device on the embedded central processing unit (ECPU) side, and the PCIe-related processing layer packets (transaction layer pocket, TLP) of the host will be forwarded to the embedded processor for processing. This means that when the PCIe emulation program of the embedded processor or the system itself fails, the following two situations may occur: one is to affect the business of the host user, and even cause the host to hang up; the other is to restart the host to restore the data processor. , causing all running programs to be interrupted. Therefore, how to perform fault isolation so as not to affect user service processing is a problem to be solved by those skilled in the art.

SUMMARY OF THE INVENTION

The embodiments of the present application provide a fault handling method, device, computer equipment and storage medium, which can effectively implement fault isolation, do not need to restart the computer host, can minimize the impact on the computer host, and can ensure the safety of the computer host. normal operation.

In a first aspect, an embodiment of the present application provides a fault handling method, which is applied to a programmable logic device, wherein:

In response to detecting a failure of the embedded processor in the data processor, the programmable logic device enters a pickup mode that includes sending a hot-plug interrupt signal to a computer host to cause the computer host to communicate with The embedded processor is fault isolated, and the hot-plug interrupt signal is used to indicate that the embedded processor has performed a hot-plug operation;

In response to detecting that the embedded processor is repaired, the programmable logic device sends a hot-plug signal to the computer host to exit the pickup mode to complete fault recovery, and the hot-plug signal is used to indicate all The embedded processor described above performs a hot-plug operation.

In a second aspect, an embodiment of the present application provides a fault handling apparatus, which is applied to a programmable logic device, wherein:

a fault isolation unit for, in response to detecting that the embedded processor in the data processor fails, the programmable logic device enters a pickup mode, the pickup mode including sending a hot-plug interrupt signal to the computer host to Isolating the computer host from the embedded processor fault, the hot-plug interrupt signal is used to instruct the embedded processor to perform a hot-plug operation;

The fault recovery unit is used for, in response to detecting that the embedded processor is repaired, the programmable logic device sends a hot-plug signal to the computer host to exit the pickup mode, so as to complete the fault recovery, and the thermal The plug signal is used to indicate that the embedded processor has performed a hot plug operation.

In a third aspect, embodiments of the present application provide a computer device, including a processor, a memory, and a communication interface, wherein the memory stores a computer program, the computer program is configured to be executed by the processor, and the computer The program includes instructions for some or all of the steps as described in the first aspect of the embodiments of the present application.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and the computer program causes a computer to execute a part or a part as described in the first aspect of the embodiment of the present application. all steps.

Implementing the embodiments of the present application will have the following beneficial effects:

By adopting the above-mentioned method, device, computer equipment and storage medium for fault handling, after detecting that the embedded processor in the data processor fails, the programmable logic device can enter the answering mode, and send the hot-plugging mode to the computer host by sending the hot-plug The interrupt signal is used to instruct the embedded processor to perform a hot-plug operation, so as to disconnect the communication between the computer host and the embedded processor, and complete the fault isolation simply and efficiently. In this way, in the traditional technical solution, once the embedded processor fails, the computer host must be restarted, causing all running programs to be interrupted, thereby minimizing the impact on the computer host and ensuring the normal operation of the computer host. run. After detecting that the embedded processor is repaired, the programmable logic device sends a hot-plug signal to the computer host, the hot-plug signal is used to instruct the embedded processor to perform a hot-plug operation, and exit the pickup mode, so that the computer host and the computer host The embedded processor re-communicates, thereby completing fault recovery quickly and improving the efficiency of fault handling. In addition, the embodiment of the present application does not require the participation of external tools such as a BMC system and a management and control platform, which can reduce the degree of dependence and achieve higher reliability.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort. in:

FIG. 1 is a schematic diagram of a system architecture provided by an embodiment of the present application;

FIG. 2 is a schematic flowchart of a fault handling method provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a fault handling apparatus provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a computer device according to an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

The terms "first", "second", "preset" and "fourth" in the description and claims of the present application and the accompanying drawings are used to distinguish different objects, rather than to describe a specific order . Furthermore, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally also includes For other steps or units inherent to these processes, methods, products or devices.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor a separate or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

It should also be understood that the term "and/or" in this document is only an association relationship for describing associated objects, indicating that there can be three kinds of relationships, for example, A and/or B, which can mean that A exists alone, and A and B exist at the same time. B, there are three cases of B alone. In addition, the character "/" in this document generally indicates that the related objects are an "or" relationship.

For ease of understanding, the following first introduces several basic concepts involved in the embodiments of the present application.

Data processing unit (DPU) is a major category of newly developed special-purpose processors. After central processing unit (CPU) and graphics processing unit (GPU), data center The third important computing chip in the scene provides a computing engine for high-bandwidth, low-latency, and data-intensive computing scenarios. Data processors mainly have the following three characteristics, namely offloading, acceleration, and isolation. Correspondingly, the three main application scenarios of data processors are network, storage, and security. In terms of offloading, the data processor can be used as the offload engine of the central processing unit, releasing the computing power of the central processing unit to upper-layer applications. For example, the data processor can offload data center network services (virtual switching, virtual routing, etc.), data center storage Services, data center security services (firewall, encryption and decryption, etc.), etc. In terms of acceleration, the data processor will become the sandbox for algorithm acceleration and the most flexible accelerator carrier. The data processor is not entirely a solidified application specific integrated circuit (ASIC), and the data consistency access such as central processing unit, image processor and data processor advocated by standard organizations such as CXL (compute express link) Under the foreshadowing of the agreement, it will further clear the obstacles of data processor programming. Combined with programmable devices such as field programmable gate array (FPGA), customizable hardware will have more room to play, "software hardware" It will become the norm, and the potential of heterogeneous computing will be fully realized due to the popularization of various data processors. In terms of isolation, data processors will become the new data gateways, taking security and privacy to a new level. Asymmetric encryption algorithm SM2, hash algorithm SM3 and symmetric block cipher algorithm SM4 can all be implemented by solidifying them in the data processor.

The high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and the connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It defines slots and connectors of multiple widths: x1, x4, x8, x12, x16, and x32, typically, low-speed peripherals (such as WiFi cards) use single-lane (x1) links, while graphics adapters are more Use faster and wider x16 lane links.

Field programmable gate array (FPGA) is a product of further development on the basis of programmable devices such as programmable logic array (PAL). Fewer problems. The basic structure of FPGA includes programmable input and output units, configurable logic blocks, digital clock management modules, routing resources, embedded dedicated hard cores, and low-level embedded functional units. Because FPGA has the characteristics of abundant wiring resources, reprogrammable and high integration, and low investment, it has been widely used in the field of digital circuit design.

Complex Programmable Logic Device (CPLD), by using programming techniques such as Electrically Erasable Programmable Read-Only Memory (electrically EPROM, EEPROM), Flash Memory, and Static Random Access Memory (static RAM, SRAM) , which constitutes a high-density, high-speed and low-power programmable logic device. A complex programmable logic device is a digital integrated circuit that users construct their own logic functions according to their own needs. The code is transferred to the target chip via a download cable to implement the designed digital system.

Referring to FIG. 1, FIG. 1 is a schematic diagram of a system architecture provided by an embodiment of the present application. As shown in FIG. 1 , the system architecture may include a computer host 100 and a data processor 200 . The computer host 100 may include computer equipment with multiple architecture processors such as Intel x86 architecture CPU, ARM architecture CPU, MIPS architecture CPU, etc. as the computing core, including but not limited to industrial computers, servers, vehicle-mounted computers, mobile workstations and other application forms , the embodiment of the present application does not impose any limitation on the type of the computer host.

In this embodiment of the present application, the data processor 200 may include a programmable logic device 201 and an embedded processor 202 . The data processor 200 may use the PCIe standard protocol for data transmission. Therefore, the data processor 200 may be a PCIe device. The programmable logic device 201 may be an FPGA, a system on chip (system on chip, SOC), an ASIC, etc., or a multi-core processor, etc., or may also be other programmable logic devices, which are not limited in this embodiment of the present application . The programmable logic device 201 may communicate with the computer host 100 through a PCIe interface. The programmable logic device 201 may communicate with the embedded processor 202 through the first interface. The first interface may be a PCIe interface, a common flash interface (CFI) or a serial peripheral interface (SPI), a peripheral component interconnect (PCI) interface, a local bus ( LocalBus) interface, etc., which are not limited in this embodiment of the present application.

The programmable logic device 201 may include a status register, and the status register may be used to record the running status of the embedded processor 202 or other devices in the data processor 200. whether the processor 202 is faulty. Optionally, a first-in-first-out (FIFO) channel may be established between the computer host 100 , the programmable logic device 201 and the embedded processor 202 , so that the computer host 100 , the programmable logic device 201 and the embedded processor 202 The controller 202 can perform data interaction through the FIFO channel, so as to improve the data transmission speed.

The data processor 200 may include a complex programmable logic device not shown in FIG. 1 , and the complex programmable logic device may communicate with the programmable logic device 201 through the first interface, and may also communicate with the embedded processor 202 through the first interface. to communicate. That is, the complex programmable logic device may communicate with the programmable logic device 201 and the embedded processor 202, respectively. The data processor 200 may also include a memory (eg, a Flash memory) not shown in FIG. 1 , the memory may be used to store programs to be executed, and the memory may communicate with the programmable logic device 201 through a CFI interface. In addition, the data processor 200 may further include a PCIe switch (Switch), a GPU, a digital signal processor (DSP), a redundant array of independent disks (RAID), etc., which are not shown in FIG. 1 , This embodiment of the present application does not limit this.

With the rapid development of data centers, communication capabilities and computing capabilities have become two important development directions of data center infrastructure that complement each other. If the data center only pays attention to the improvement of computing power, and the improvement of communication infrastructure cannot keep up, the overall system performance of the data center is still limited and cannot reach its true potential. In order to cope with the increasingly large and complex data volume, the data processing unit (DPU) came into being.

The data processor is located in the cooperative processing unit, which is an implementation of the idea of separating the data plane and the control plane. It cooperates with the central processing unit (CPU), the latter is responsible for general control, and the former focuses on data processing. That is, data processors can offload data processing/preprocessing from the central processor while distributing computing power closer to where the data occurs, reducing traffic. Since data processors need to move computations close to the data, this also means higher demands on the reliability and availability of data processors. In order to meet the network requirements for large data transmission, the data processor needs to use a high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) interface for data transmission. Therefore, the data processor is usually involved in the failure of the PCIe device, and the data processor system is required to assist the PCIe device in failure recovery.

At present, the data processor will simulate a PCIe device on the embedded central processing unit (ECPU) side, and the PCIe-related processing layer packets (transaction layer pocket, TLP) of the host will be forwarded to the embedded processor for processing. This means that when the PCIe emulation program of the embedded processor or the system itself fails, the following two situations may occur: one is to affect the business of the host user, and even cause the host to hang up; the other is to restart the host to restore the data processor. , causing all running programs to be interrupted. Therefore, how to perform fault isolation so as not to affect user service processing is a problem to be solved by those skilled in the art.

In order to solve the above problem, an embodiment of the present application provides a fault handling method. By implementing the method, fault isolation can be effectively achieved, the computer host does not need to be restarted, the impact on the computer host can be minimized, and the computer can be guaranteed normal operation of the host.

Please refer to FIG. 2 . FIG. 2 is a schematic flowchart of a fault handling method provided by an embodiment of the present application. It can be understood that the method can be used in the system architecture shown in FIG. 1, and can be specifically executed by the programmable logic device shown in FIG. 1, and the method can include the following steps S201-S202, wherein:

Step S201: In response to detecting the failure of the embedded processor in the data processor, the programmable logic device enters a pickup mode, and the pickup mode includes sending a hot-plug interrupt signal to the computer host, so that the computer host can communicate with the embedded processor. device fault isolation.

As the number of PCIe devices connected to the host computer increases, the probability of the PCIe device failure also increases. The failure of the PCIe device may affect the normal operation of the computer host, and in severe cases, even cause the computer host to hang up. Therefore, the processing of the faulty PCIe device is an important part of maintaining the normal operation of the computer host. Since the data processor may use the PCIe standard protocol for data transmission, the data processor may be a PCIe device. As shown in FIG. 1, a data processor may include a programmable logic device and an embedded processor. The programmable logic device may be an FPGA, an SOC, an ASIC, etc., or a multi-core processor, etc., or may also be other programmable logic devices, which are not limited in this embodiment of the present application. For the data processor, the data processor can simulate a PCIe device on the embedded processor side, and the embedded processor can be used to process PCIe-related TLP packets forwarded to the computer host therein. This means that when the PCIe emulation program of the embedded processor or the system itself fails, the failure of the embedded processor may affect the normal operation of the computer host.

In order to prevent the failure of the embedded processor from affecting the normal operation of the computer host, it is necessary to isolate the faulty embedded processor from the computer host. In this embodiment of the present application, a programmable logic device may be used to isolate a faulty embedded processor from a computer host. Specifically, after detecting the failure of the embedded processor, the programmable logic device enters a pickup mode to complete the fault isolation. A possible implementation manner for the programmable logic device to enter the pickup mode may be: the programmable logic device sends a hot-plug interrupt signal to the computer host, and the hot-plug interrupt signal is used to instruct the embedded processor to perform a hot-plug interrupt signal. plug-in operation. When the computer host receives the hot-plug interrupt signal, it will consider that the embedded processor has been hot-plugged, and the computer host will no longer conduct business interactions with the embedded processor, thereby disconnecting the computer host from the embedded processor. communication connection to complete fault isolation.

It can be seen that after detecting the failure of the embedded processor, the programmable logic device sends a hot-plug interrupt signal to the computer host in response, so that the fault isolation between the computer host and the embedded processor can be realized. This method of fault isolation is more thorough, so it can avoid spreading the fault to the entire computer host. In addition, this method of fault isolation does not need to restart the computer host, which is simple and efficient, thereby minimizing the impact on the computer host, and ensuring that other services of the computer host run normally without interference.

In a possible implementation, before step S201, a fault detection stage may also be included, which may specifically include the following steps:

In response to reading the preset flag bit from the computer host, the programmable logic device determines that the embedded processor is faulty, and the preset flag bit is used to indicate that the embedded processor is faulty.

In the embodiments of the present application, a FIFO channel may be established between the computer host, the programmable logic device, and the embedded processor, and the computer host, the programmable logic device, and the embedded processor may perform data interaction through the FIFO channel. Specifically, the computer host can send a heartbeat packet to the embedded processor according to a predetermined time period, and send the heartbeat packet to the embedded processor through the FIFO channel. After receiving the heartbeat packet, the embedded processor returns a heartbeat packet to the computer host. Heartbeat packets to maintain mutual communication between the computer host and the embedded processor. If the computer host receives the heartbeat packet sent by the embedded processor within a preset time period, it can be determined that the embedded processor is in a normal working state, that is, the embedded processor is not faulty. If the computer host does not receive the heartbeat packet sent by the embedded processor for more than a preset time period, it can be determined that the embedded processor is faulty, that is, the embedded processor may have died.

In a possible implementation manner, the computer host may be provided with a preset program, and after detecting a failure of the embedded processor, a preset flag bit may be set in the preset program, where the preset flag bit is used to indicate the embedded processor The processor has failed. After detecting the preset flag bit, the programmable logic device can determine that the embedded processor is faulty and enter the fault isolation stage, for example, step S201 can be performed to complete fault isolation between the computer host and the embedded processor.

In a possible implementation, the computer host may be provided with a first status register, and the first status register may be used to store the operating status of the embedded processor. The state value of the first state register may be set as: "00" indicates that the embedded processor is working normally, and "10" indicates that the embedded processor is faulty. The preset flag bit may be an identifier used to indicate that the embedded processor is faulty. In this embodiment of the present application, the preset flag bit may be understood as the state value "10" of the first state register. When the computer host detects that the embedded processor is working normally, the state value of the first state register remains "00" unchanged. After detecting that the embedded processor is faulty, the computer host can modify the state value of the first status register from "00" to "10", which means that the embedded processor is faulty. The programmable logic device can poll and read the state value of the first state register. When the state value of the first state register is read as "10", that is, when the preset flag bit is read, the embedded processor is determined. error occured. After detecting that the embedded processor is faulty, the programmable logic device enters a fault isolation stage, for example, step S201 may be performed to complete fault isolation between the computer host and the embedded processor.

It can be seen that a FIFO channel is established between the computer host, the programmable logic device and the embedded processor, and the computer host, the programmable logic device and the embedded processor can exchange data through the FIFO channel. After the computer host detects that the embedded processor is faulty, it can set a preset flag to indicate that the embedded processor is faulty. After the programmable logic device reads the preset flag, it can determine the embedded processor. error occured. In this fault detection method, the burden of the programmable logic device is small, and it is simple and efficient.

In a possible implementation manner, the specific implementation manner of fault detection can also be implemented through steps A1-A2:

Step A1: The programmable logic device acquires the register information of the status register, and the register information is used to record the running state of the embedded processor.

Step A2: The programmable logic device determines whether the embedded processor is faulty according to the register information.

In this embodiment of the present application, the programmable logic device may be provided with a status register, where the status register is used to store the running status of the embedded processor. The register information stored in the status register is used to record the running status of the embedded processor.

Taking the programmable logic device including a 32-bit status register as an example, the meaning of each bit of the status register can be shown in Table 1:

Table 1

Bit0 Bit1 Bit2-Bit3 Bit4-Bit8 Bit9-Bit31 first flag second flag reserve fault information code reserve

The specific instructions are as follows:

Bit0: The programmable logic device judges whether the embedded processor is working normally. When the embedded processor is working normally, the first flag bit in the status register is set within a preset time. Among them, setting can be understood as setting the corresponding flag position to 0 or 1.

Bit1: The second flag bit is used to store the running state of the embedded processor fed back by the complex programmable logic device, and the programmable logic device can store the information fed back by the complex programmable logic device in Bit1.

Bit2-Bit3: reserved bits.

Bit4-Bit8: If the programmable logic device detects that the embedded processor is faulty, it can store the corresponding fault information code to Bit4-Bit8 according to the fault source and fault type of the embedded processor.

Bit9-Bit31: Reserved bits.

After obtaining the register information of the status register, it can be determined whether the embedded processor is faulty or not according to the register information. The specific implementation can refer to the description below, which will not be repeated here.

It can be seen that, by obtaining the register information of the status register, and then judging whether the embedded processor fails or not according to the register information. The state register provided by the programmable logic device realizes the self-detection of the embedded processor, which is simple and efficient, with fewer devices involved in the detection and higher fault detection accuracy.

In a possible implementation manner, step A2 may specifically include the following steps:

The programmable logic device reads the state value of the first flag bit in the status register from the register information according to a preset cycle; the programmable logic device determines whether the first flag bit is set according to the read state value of the first flag bit; The programmable logic device determines that the embedded processor is faulty in response to the arrival of the preset time when the first flag bit is not set.

In this embodiment of the present application, the state register provided by the programmable logic device can be used to implement the self-test of the embedded processor. Specifically, the operating state of the embedded processor may be associated with the first flag bit of the status register (for example, Bit0 shown in Table 1). The programmable logic device periodically (eg, 1 minute) sends discovery requests to the embedded processor. If the embedded processor that receives the discovery request works normally, it will reply a discovery response to the programmable logic device, that is, to respond to the discovery request sent by the programmable logic device, and at this time, the first flag bit can be set. Among them, setting can be understood as setting the corresponding flag position to 0 or 1. For example, the programmable logic device responds to the discovery request sent by the embedded processor. If the state value of the first flag bit in the previous cycle is "0", the state value of the first flag bit is set to 1; If the state value of the first flag bit is "1" in one cycle, the state value of the first flag bit is set to 0. That is to say, if the embedded processor works normally, the state value of the first flag bit of the state register in the programmable logic device will change periodically. If the embedded processor fails, it cannot respond to the discovery request sent by the embedded processor, and the first flag bit cannot be set at this time. For example, the programmable logic device cannot respond to the discovery request sent by the embedded processor. If the state value of the first flag bit in the previous cycle is "0", the state value of the first flag bit this time is still "0". ; Or if the state value of the first flag bit in the previous cycle is "1", the state value of the first flag bit this time is still "1". That is, if the embedded processor fails, the state value of the first flag bit of the state register in the programmable logic device will not change periodically. Therefore, in the embodiment of the present application, the programmable logic device can read the state value of the first flag bit in the status register from the register information according to the preset cycle, and then judge the first flag bit according to the read state value of the first flag bit. Whether a flag is set, if the first flag is not set at the preset time, it can be determined that the embedded processor is faulty. The preset period and the preset time may be determined according to actual application scenarios, which are not limited in this embodiment of the present application.

It can be seen that the programmable logic device can read the state value of the first flag bit in the status register from the register information according to the preset cycle, and then judge whether the first flag bit is set according to the read state value of the first flag bit If the first flag bit is not set at the preset time, it is determined that the embedded processor is faulty. The state register provided by the programmable logic device realizes the self-detection of the embedded processor, which is simple and efficient, with fewer devices involved in the detection and higher fault detection accuracy.

In a possible implementation manner, step A2 may further include the following steps:

The programmable logic device reads the state value of the second flag bit in the status register from the register information, the state value of the second flag bit is associated with the first signal fed back by the complex programmable logic device, and the complex programmable logic device is used to detect running state of the embedded processor, and feeding back the first signal to the programmable logic device according to the running state of the embedded processor; in response to reading the state value of the second flag bit as a preset value, the programmable logic device determines the embedded The processor has failed.

In this embodiment of the present application, the programmable logic device may detect whether the embedded processor is faulty through a complex programmable logic device connected to the embedded processor. Among them, the complex programmable logic device can communicate with the embedded processor and the programmable logic device respectively, and the complex programmable logic device can have a built-in watchdog module for monitoring the operation of the embedded processor. When the embedded processor is working normally, it will send a feedback signal to the timer of the watchdog module within a preset time (for example, 1 second or 0.5 seconds, etc.) to clear the timer, so as to realize the function of feeding the dog. If the embedded processor does not feed the timer within the preset time, the complex programmable logic device may feed back the first signal to the programmable logic device to indicate that the embedded processor does not respond within the preset time. When the programmable logic device receives the first signal, the state value of the bit corresponding to the complex programmable logic device in the status register (for example, Bit1 shown in Table 1) can be modified to a preset value to represent the embedded The processor has failed.

For example, the status value of the second flag bit (see Bit1 shown in Table 1) in the status register can be set as: "00" indicates that the embedded processor is working normally, and "10" indicates that the embedded processor is faulty. The preset value may be a flag used to indicate that the embedded processor is faulty, and in this embodiment of the present application, the preset value may be understood as the state value "10" of the second flag bit. When the programmable logic device does not receive the first signal for feeding back the failure of the embedded processor, the state value of the second flag bit remains "00" unchanged. After receiving the first signal, the programmable logic device can modify the state value of the second flag bit from "00" to "10", which means that the embedded processor is faulty. When the programmable logic device reads the state value of the second flag bit as "10", that is, when the preset flag bit is read, it is determined that the embedded processor is faulty. In a possible implementation manner, the second flag bit and the first flag bit may also be the same flag bit, that is, the same bit bit is used to implement the functions of the first flag bit and the second flag bit. For example, Bit1 can be used to store the information of the running state of the embedded processor fed back by the complex programmable logic device, and can also be used to store the information of the programmable logic device to judge whether the embedded processor is working normally. After detecting that the embedded processor is faulty, the programmable logic device enters a fault isolation stage, for example, step S201 may be performed to complete fault isolation between the computer host and the embedded processor.

It can be seen that the fault detection of the embedded processor is performed through the complex programmable logic device, and then the detection result of the complex programmable logic device is associated with the status register of the programmable logic device. If the state value of the second flag bit in the read state register is a preset value, it is determined that the embedded processor is faulty. In this way, the use of complex programmable logic devices for fault detection of embedded processors expands the means of fault detection for embedded processors, and the burden of programmable logic devices is relatively small, which can improve the accuracy of fault detection.

In a possible implementation, the pickup mode further includes that the programmable logic device sends a first processing layer data packet for reporting an error to the computer host, so as to isolate the computer host from the embedded processor fault.

In the embodiment of the present application, when the computer host performs business interaction with the embedded processor, the computer host may first send the business data to the programmable logic device, and then the programmable logic device forwards the business data to the embedded processor for processing. deal with. These business data cannot be processed if the embedded processor fails. At this time, after the computer host sends the service data to the programmable logic device, the programmable logic device can enter the pickup mode to prompt the computer host that the embedded processor is faulty, so as to realize the fault between the computer host and the embedded processor. isolation. Specifically, the programmable logic device can send a first processing layer data packet to the computer host, where the first processing layer data packet is used to report an error to the computer host to prompt the embedded processor to fail, thereby realizing the connection between the computer host and the embedded processor. The processor is fault isolated.

It can be seen that, after detecting the failure of the embedded processor, the programmable logic device sends the first processing layer data packet to the computer host for error reporting, which can realize fault isolation between the computer host and the embedded processor. This fault isolation method does not need to restart the computer host, can reduce the impact on the computer host, and can ensure that other services of the computer host run normally without interference.

In a possible implementation manner, the programmable logic device sends the first processing layer data packet for reporting an error to the computer host, which may include the following steps:

Obtain the register information of the status register, which is used to record the running state of the embedded processor; read the fault source and fault type of the embedded processor from the register information; generate the first error message according to the fault source and fault type. Processing layer data packet; sending the first processing layer data packet to the computer host.

In the PCIe standard protocol, the fault types of PCIe devices are divided into correctable errors (correctable errors, CE), non-fatal uncorrectable errors (NFE) and fatal uncorrectable errors according to the severity of the fault. Error (fatal uncorrectable error, FE). Among them, correctable errors can be automatically identified and corrected or recovered by hardware; non-fatal uncorrectable errors are generally handled directly by device driver software; fatal uncorrectable errors are usually handled by system software, and generally require operations such as reset. The fault source can be understood as the specific faulty equipment.

In this embodiment of the present application, there may be multiple embedded processors. Taking the presence of embedded processor A and embedded processor B as an example, the embedded processor A and embedded processor B may be connected to the programmable logic Each bit of the status register in the device establishes a one-to-one correspondence. As shown in Table 1, the running state of the embedded processor A can be stored in Bit4, and the running state of the embedded processor B can be stored in Bit5. Correspondingly, the status values of Bit4 and Bit5 in the status register can be set to "00" to indicate normal operation, "01" to indicate a correctable error, "10" to indicate a non-fatal uncorrectable error, and "11" to indicate a fatal uncorrectable error. For example, when the status value of Bit4 is read in the programmable logic device as "00", it can be determined that the embedded processor A is working normally. When the status value of Bit5 read from the programmable logic device is "01", it can be determined that the source of the fault is the embedded processor B, and the fault type is a correctable error; or when the status of Bit5 is read from the programmable logic device When the value is "10", it can be determined that the source of the fault is embedded processor B, and the fault type is a non-fatal uncorrectable error. Then, a first processing layer data packet can be generated according to the fault source and fault type of the processor in the register information, and the first processing layer data packet can be fed back to the computer host for error reporting, thereby completing fault isolation. The first processing layer data packet may also include the PCIe device identifier of the faulty embedded processor, and the PCIe device identifier may be an identifier that identifies the PCIe device in the PCIe bus system. Specifically, the PCIe device identifier may be the bus of the PCIe device. Device function (bus device function, BDF) or PCIe device address information, etc., in order to quickly locate the faulty embedded processor.

It can be seen that the programmable logic device reads the fault source and fault type of the embedded processor from the register information, and then generates the first processing layer data packet according to the fault source and fault type, and feeds back the first processing layer to the computer host. data packets, help to quickly locate the faulty embedded processor, and can improve the accuracy of fault location.

Step S202: In response to detecting that the embedded processor is repaired, the programmable logic device sends a hot-plug signal to the computer host, and exits the pickup mode to complete fault recovery.

In the embodiment of the present application, the fault repairing manner may be self-repairing or restarting the faulty embedded processor, which is not limited in the embodiment of the present application. After the fault repair of the embedded processor is completed and it can work normally, a recovery request can be sent to the programmable logic device, and the recovery request is used to indicate that the fault repair of the embedded processor is completed. After receiving the restoration request, the programmable logic device determines that the restoration of the embedded processor is completed according to the restoration request, and can send a hot-plug signal to the computer host, where the hot-plug signal can be used to instruct the embedded processor to perform a hot-plug operation. After receiving the hot-plug signal, the computer host considers that the embedded processor has performed the hot-plug, and the computer host can normally perform business interaction with the embedded processor. At this time, the programmable logic device exits the pickup mode, the computer host can re-communicate with the embedded processor, and the fault recovery is completed.

As can be seen in the method shown in Figure 2, after detecting the failure of the embedded processor in the data processor, the programmable logic device can enter the pickup mode, and by sending a hot-plug interrupt signal to the computer host, the The hot-plug interrupt signal is used to instruct the embedded processor to perform a hot-plug operation, so as to disconnect the communication between the computer host and the embedded processor, and complete fault isolation simply and efficiently. In this way, in the traditional technical solution, once the embedded processor fails, the computer host must be restarted, causing all running programs to be interrupted, thereby minimizing the impact on the computer host and ensuring the normal operation of the computer host. run. After detecting that the embedded processor is repaired, the programmable logic device sends a hot-plug signal to the computer host, the hot-plug signal is used to instruct the embedded processor to perform a hot-plug operation, and exit the pickup mode, so that the computer host and the computer host The embedded processor re-communicates, thereby completing fault recovery quickly and improving the efficiency of fault handling. In addition, the embodiment of the present application does not require the participation of external tools such as a BMC system and a management and control platform, which can reduce the degree of dependence and achieve higher reliability.

The methods of the embodiments of the present application are described in detail above, and the apparatuses of the embodiments of the present application are provided below.

Please refer to FIG. 3 , which is a schematic structural diagram of a fault handling apparatus provided by an embodiment of the present application. The device is applied to a programmable logic device. As shown in FIG. 3 , the fault processing device 300 includes a fault isolation unit 301 and a fault recovery unit 302. The detailed description of each unit is as follows:

The fault isolation unit 301 is configured to enter a pickup mode in response to detecting that the embedded processor in the data processor fails, and the pickup mode includes sending a hot-plug interrupt signal to a computer host, so that the computer host Being isolated from the embedded processor fault, the hot-plug interrupt signal is used to indicate that the embedded processor has performed a hot-plug operation;

The fault recovery unit 302 is configured to, in response to detecting that the embedded processor is repaired, send a hot-plug signal to the computer host to exit the pickup mode to complete fault recovery, where the hot-plug signal is used to indicate The embedded processor performs a hot-plug operation.

In a possible implementation manner, the apparatus 300 for fault handling may further include a fault detection unit not shown in FIG. 3 , and the fault detection unit may be specifically configured to acquire register information of the status register, and the register information uses to record the running state of the embedded processor; to determine whether the embedded processor is faulty according to the register information.

In a possible implementation manner, the fault processing apparatus 300 may further include a fault detection unit not shown in FIG. 3 , and the fault detection unit may be specifically configured to read the register information from the register information according to a preset period. The state value of the first flag bit in the status register; according to the read state value of the first flag bit, determine whether the first flag bit is set; in response to reaching the preset time, the first flag bit is not Set to determine that the embedded processor has failed.

In a possible implementation manner, the apparatus 300 for fault handling may further include a fault detection unit not shown in FIG. 3 , and the fault detection unit may be specifically configured to read the status register from the register information. the state value of the second flag bit, the state value of the second flag bit is associated with the first signal fed back by the complex programmable logic device, and the complex programmable logic device is used to detect the running state of the embedded processor, and feeding back the first signal to the programmable logic device according to the running state of the embedded processor; in response to reading the state value of the second flag bit as a preset value, determine the embedded processor device is faulty.

In a possible implementation manner, the fault isolation unit 301 is further configured to send a first processing layer data packet for reporting an error to the computer host, so as to isolate the computer host from the embedded processor fault.

In a possible implementation manner, the fault isolation unit 301 is specifically configured to acquire register information of the status register, where the register information is used to record the running state of the embedded processor; read from the register information A fault source and a fault type of the embedded processor; generating a first processing layer data packet for reporting an error according to the fault source and the fault type; sending the first processing layer data packet to the computer host.

In a possible implementation manner, a first-in-first-out queue channel exists between the computer host, the programmable logic device and the embedded processor, and the apparatus 300 for fault handling may further include a method not shown in FIG. 3 . The fault detection unit is specifically configured to determine that the embedded processor is faulty in response to reading a preset flag bit from the computer host, and the preset flag bit is used to indicate the The embedded processor has failed.

It should be noted that, the implementation of each unit may also correspond to the corresponding description with reference to the method embodiment shown in FIG. 2 .

Please refer to FIG. 4 , which is a schematic structural diagram of a computer device provided by an embodiment of the present application. As shown in FIG. 4 , the computer device 400 includes a processor 401 , a memory 402 and a communication interface 403 , wherein the memory 402 stores a computer program 404 . The processor 401 , the memory 402 , the communication interface 403 and the computer program 404 can be connected through a bus 405 .

When the computer device is a programmable logic device, the above-mentioned computer program 404 is used to execute the instructions of the following steps:

In response to detecting a failure of the embedded processor in the data processor, enter a pickup mode, the pickup mode comprising sending a hot-plug interrupt signal to a computer host to cause the computer host to communicate with the embedded processor Fault isolation, the hot-plug interrupt signal is used to indicate that the embedded processor has performed a hot-plug operation;

In response to detecting that the embedded processor is repaired, a hot-plug signal is sent to the computer host to exit the pickup mode to complete fault recovery, and the hot-plug signal is used to instruct the embedded processor to execute hot-plug operation.

In one possible implementation, the programmable logic device includes a status register, and before the programmable logic device enters a pickup mode in response to detecting a failure of the embedded processor in the data processor, The computer program 404 is also used to perform instructions for the following steps:

Obtain register information of the status register, where the register information is used to record the running state of the embedded processor;

Whether the embedded processor is faulty is determined according to the register information.

In a possible implementation manner, in the aspect of judging whether the embedded processor is faulty according to the register information, the computer program 404 is specifically configured to execute the instructions of the following steps:

Read the state value of the first flag bit in the state register from the register information according to a preset cycle;

According to the read state value of the first flag bit, determine whether the first flag bit is set;

In response to the arrival of a preset time when the first flag bit is not set, it is determined that the embedded processor is faulty.

In a possible implementation manner, in the aspect of judging whether the embedded processor is faulty according to the register information, the computer program 404 is specifically configured to execute the instructions of the following steps:

The state value of the second flag bit in the status register is read from the register information, and the state value of the second flag bit is associated with the first signal fed back by the complex programmable logic device. The complex programmable logic The device is configured to detect the running state of the embedded processor, and feed back the first signal to the programmable logic device according to the running state of the embedded processor;

In response to reading that the state value of the second flag bit is a preset value, it is determined that the embedded processor is faulty.

In a possible implementation manner, the pickup mode further includes:

A first processing layer packet for error reporting is sent to the computer host to isolate the computer host from the embedded processor fault.

In a possible implementation manner, in that the programmable logic device includes a status register, and the first processing layer data packet for reporting an error is sent to the computer host, the computer program 404 is specifically configured to execute the following Instructions for steps:

Obtain register information of the status register, where the register information is used to record the running state of the embedded processor;

Read the fault source and fault type of the embedded processor from the register information;

generating a first processing layer data packet for reporting an error according to the fault source and the fault type;

The first processing layer data packet is sent to the computer host.

In a possible implementation, there is a first-in-first-out queue channel between the computer host, the programmable logic device and the embedded processor, and in the response to detecting the embedded processor in the data processor When the processor fails, before the programmable logic device enters the pickup mode, the computer program 404 is further used to execute the instructions of the following steps:

In response to reading a preset flag bit from the computer host, it is determined that the embedded processor is faulty, and the preset flag bit is used to indicate that the embedded processor is faulty.

Those skilled in the art can understand that, for the convenience of description, only one memory and processor are shown in FIG. 4 . In an actual terminal or server, there may be multiple processors and memories. The memory 402 may also be referred to as a storage medium or a storage device, etc., which is not limited in this embodiment of the present application.

It should be understood that, in this embodiment of the present application, the processor 401 may be a central processing unit (central processing unit, CPU), and the processor may also be other general-purpose processors, digital signal processors (digital signal processing, DSP), application-specific integrated circuits (application specific integrated circuit, ASIC), off-the-shelf programmable gate array (fieldprogrammable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

It should also be understood that the memory 402 mentioned in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically programmable Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory. Volatile memory may be random access memory (RAM), which acts as an external cache. By way of illustration, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double datarate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synchronize link DRAM, SLDRAM) And direct memory bus random access memory (direct rambus RAM, DR RAM).

It should be noted that when the processor 401 is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components, the memory (storage module) is integrated in the processor.

It should be noted that the memory 402 described herein is intended to include, but not be limited to, these and any other suitable types of memory.

In addition to the data bus, the bus 405 may also include a power bus, a control bus, a status signal bus, and the like. However, for the sake of clarity, the various buses are labeled as buses in the figure.

In the implementation process, each step of the above-mentioned method can be completed by a hardware integrated logic circuit in a processor or an instruction in the form of software. The steps of the methods disclosed in conjunction with the embodiments of the present application may be directly embodied as executed by a hardware processor, or executed by a combination of hardware and software modules in the processor. The software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media mature in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware. To avoid repetition, detailed description is omitted here.

In various embodiments of the present application, the size of the sequence numbers of the above-mentioned processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, rather than the implementation process of the embodiments of the present application. constitute any limitation.

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware . Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

In the above-mentioned embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented in software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer may be a general purpose computer, special purpose computer, computer network, or other programmable device. The computer instructions may be stored in or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server or data center Transmission to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line) or wireless (eg, infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes an integration of one or more available media. The usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVDs), or semiconductor media (eg, solid state drives), and the like.

Embodiments of the present application further provide a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement any one of the fault handling methods described in the foregoing method embodiments. some or all of the steps of the method.

Embodiments of the present application further provide a computer program product, the computer program product comprising a non-transitory computer-readable storage medium storing a computer program, the computer program being operable to cause a computer to execute the methods described in the foregoing method embodiments Some or all of the steps in any method of troubleshooting.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims (10)

1. A method for fault handling is applied to a programmable logic device, and is characterized by comprising the following steps:

in response to detecting that an embedded processor in a data processor fails, the programmable logic device enters a solution mode, wherein the solution mode comprises sending a hot plug interrupt signal to a computer host to isolate the computer host from the embedded processor, and the hot plug interrupt signal is used for indicating that the embedded processor executes a hot plug operation;

and in response to detecting that the embedded processor is repaired, the programmable logic device sends a hot plug signal to the computer host, exits the answer mode and completes fault recovery, wherein the hot plug signal is used for indicating the embedded processor to execute hot plug operation.

2. The method of claim 1, wherein the programmable logic device includes a status register, and wherein prior to the programmable logic device entering the solution mode in response to detecting a failure of an embedded processor in the data processor, further comprising:

the programmable logic device acquires register information of the status register, wherein the register information is used for recording the running status of the embedded processor;

and the programmable logic device judges whether the embedded processor has a fault according to the register information.

3. The method of claim 2, wherein the determining, by the programmable logic device, whether the embedded processor is malfunctioning based on the register information comprises:

the programmable logic device reads a state value of a first zone bit in the state register from the register information according to a preset period;

the programmable logic device judges whether the first flag bit is set according to the read state value of the first flag bit;

in response to the first flag bit not being set by a preset time, the programmable logic device determines that the embedded processor is malfunctioning.

4. The method of claim 2, wherein the determining, by the programmable logic device, whether the embedded processor is malfunctioning based on the register information comprises:

the programmable logic device reads a state value of a second flag bit in the state register from the register information, the state value of the second flag bit is associated with a first signal fed back by a complex programmable logic device, and the complex programmable logic device is used for detecting the running state of the embedded processor and feeding back the first signal to the programmable logic device according to the running state of the embedded processor;

and in response to reading that the state value of the second zone bit is a preset value, the programmable logic device determines that the embedded processor fails.

5. The method of claim 1, wherein the pick-up mode further comprises:

and the programmable logic device sends a first processing layer data packet for error reporting to the computer host so as to isolate the computer host from the embedded processor in a fault manner.

6. The method of claim 5, wherein the programmable logic device comprises a status register, and wherein sending a first processing layer packet for error reporting to the host computer by the programmable logic device comprises:

the programmable logic device acquires register information of the status register, wherein the register information is used for recording the running status of the embedded processor;

the programmable logic device reads the fault source and the fault type of the embedded processor from the register information;

the programmable logic device generates a first processing layer data packet for error reporting according to the fault source and the fault type;

and the programmable logic device sends the first processing layer data packet to the computer host.

7. The method of claim 1, wherein a first-in-first-out queue path exists between the computer host, the programmable logic device, and the embedded processor, and wherein prior to the programmable logic device entering a solution mode in response to detecting a failure of the embedded processor in the data processor, further comprising:

and in response to reading a preset flag bit from the computer host, the programmable logic device determines that the embedded processor fails, wherein the preset flag bit is used for indicating that the embedded processor fails.

8. A fault handling apparatus for a programmable logic device, comprising:

the fault isolation unit is used for responding to the detection that the embedded processor in the data processor has a fault, and the programmable logic device enters a solution mode, wherein the solution mode comprises the step of sending a hot plug interrupt signal to the computer host so as to isolate the computer host from the embedded processor in a fault mode, and the hot plug interrupt signal is used for indicating the embedded processor to execute hot plug operation;

and the fault recovery unit is used for responding to the detection that the embedded processor is repaired, the programmable logic device sends a hot plug signal to the computer host and exits from the answering mode to complete fault recovery, and the hot plug signal is used for indicating the embedded processor to execute hot plug operation.

9. A computer device, characterized in that it comprises a processor, a memory and a communication interface, wherein the memory stores a computer program configured to be executed by the processor, the computer program comprising instructions for carrying out the steps in the method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, the computer program causing a computer to execute to implement the method of any one of claims 1-7.

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