CN1148876C - Fast locking double-track digital delay phase-locked circuit - Google Patents

Abstract

The invention discloses a circuit for generating a delay signal, which comprises: a first delay circuit generating a first delayed signal; a second delay circuit for generating a second delayed signal; a delay unit generating an internal delay signal; a first phase detector generating a first control signal; a second phase detector for generating a second control signal. The present invention has a delay circuit monitor for generating the first delay control signal and the second delay control signal, and a DTC delay unit for generating the delay signal.

Description

Fast-locking dual-rail digital delay-locked circuit

The present invention relates to a digital circuit design, in particular to a digital circuit design with a phase alignment circuit.

REFERENCE DATA US Patent Documents: US Patent No. 6,060,928; US Patent No. 6,144,713; US Patent No. 6,166,572; and US Patent No. 6,125,157.

Delayed locked loops are usually used in high-speed phase correction circuits, such as double data rate synchronous dynamic random access memory DDR SDRAM. In a system using DDR SDRAM as a memory storage device, a data strobe phase control (data strobe phase control) is required to lock (latch) the read data sent back by DDR SDRAM (hereinafter referred to as DDR). DDR sends data pulses and data on the edge of each clock pulse, so it is called "edge aligned"; and when DDR performs writing data pulses and data in the center of each clock pulse, it is called "central alignment" (center -aligned). This method of triggering with different clock pulse positions for reading and writing is to simplify the design and obtain better yield during DDR manufacturing. Therefore, when the DDR performs a write cycle, the system must generate an exact quarter-one delay for the center alignment pulse and data.

Figure 1 shows a typical dual-rail digital delay-locked (DLL) circuit. The phase detector 130 compares the ext_clk signal with the delay_clk signal generated by the T/4 delay circuit 115 . The delay circuit monitor 140 responds to the increment_or_decrement (increment or decrement) signal from the phase detector 130, and outputs a delay_control_number (delay_control_number) signal to the delay circuits 115 and 116 to adjust the delay amount. Finally the system converges and a T/4 delay clock 150 is obtained. However, the results from phase detector 130 may drift due to changes in temperature, causing delay circuit monitor 140 to provide inappropriate information to T/4 delay circuits 115 and 116 . Furthermore, process variations may also affect the phase detector 130 results. Therefore, the present invention proposes a digital delay-locked circuit with dual-lock mechanism and dynamic delay control to solve the above-mentioned problems. It should be noted that the present invention may generate any desired delayed signal. So the present invention can be used in any circuit using DLL mechanism.

The present invention provides an accurate time delay generator using a dual-rail digital delay-locked circuit (DLL). The dual-rail digital DLL includes a first delay circuit, a second delay circuit, a delay unit, a first phase detector, a second phase detector, a delay circuit monitor, and a digital time converter (DTC) delay unit.

The first delay circuit receives an external clock signal and a first delay control signal to generate a first delay signal. And the second delay circuit receives the second delay control signal and the external clock signal to generate the second delay signal. The delay unit uses the external clock signal, the first delay signal and the second delay signal to generate the internal delay signal. The first phase detector receives the internal delay signal and the first delay signal to generate a first control signal; and the second phase detector uses the internal delay signal and the second delay signal to generate a second control signal. The delay circuit monitor generates a first delay control signal and a second delay control signal in response to the first and second control signals. The delay signal is generated by a DTC delay unit, wherein the input of the DTC delay unit is an external clock signal and a first delay control signal.

The present invention provides a dual-rail delay-locked circuit to generate desired delayed signals. The dual-rail DLL design presented here dynamically changes the delay of the DTC delay unit in response to changes in voltage and temperature. The circuit provided here can be applied to any high-speed phase correction system, and the delay amount can be extended to 1/N cycle time by introducing N DTC delay units into the delay circuit.

Fig. 1 shows a known DLL circuit which can generate a T/4 delayed clock.

FIG. 2 shows a dual-rail DLL circuit designed according to the present invention, which can generate a T/N delayed clock.

FIG. 3 shows a specific embodiment of the DTC delay unit as in FIG. 2 .

FIG. 4 shows a dual-rail DLL circuit designed according to the present invention, which can generate a T/4 delayed clock.

Figure 5 shows an example of locking for a dual-rail DLL circuit.

Figure 6 shows a leading example of a dual-rail DLL circuit.

Figure 7 shows a backward example of a dual-rail DLL circuit.

Figure 8 shows the non-linear behavior of a DTC delay cell due to process variations.

Figure 9 shows a delay circuit with 4 DTC delay units, the non-linear characteristics due to process changes.

Referring to FIG. 2, it shows a dual-rail DLL circuit designed according to the present invention, which can generate a T/N delayed clock, where T is a clock cycle time and N is a predetermined number. The dual-rail DLL circuit of the present invention includes: a first delay circuit 200, a second delay circuit 220, a delay unit, preferably a half-resolution delay unit 235, a first phase detector 245, and a second phase detector 255 , a delay circuit monitor 265 and a DTC delay unit 270 .

The first delay circuit 200 generates a first delay signal 215 in response to an external clock signal (ext_clk) and a first delay control signal 210 . The second delay circuit generates a second delay signal 230 in response to the second delay control signal 225 and (ext_clk) 220 . Preferably, the first delay circuit 200 and the second delay circuit 220 respectively have N DTC delay units, wherein N is a predetermined number. The half-resolution delay unit 235 generates an internal delay signal 240 in response to (ext_clk). Preferably, the half-resolution delay unit 235 is further responsive to the first delayed signal 215 and the second delayed signal 230 . The first phase detector 245 compares the internal delayed signal 240 with the first delayed signal 215 to generate a first control signal 250 .

The second phase detector 255 compares the internal delay signal 240 with the second delay signal 230 to generate a second control signal 260 . The delay circuit monitor 265 generates the first delay control signal 210 and the second delay control signal 225 in response to the first and second control signals (250 and 260). For a description of further functions of the delay circuit monitor 265, please refer to the description of FIG. 4 . The DTC delay unit 270 generates a delay signal 275 in response to (ext_clk) and the first delay control signal 210 .

FIG. 3 shows how the DTC delay unit converts the 4-bit delay control digital input 305 into a delayed signal output 310 . The DTC delay unit includes a digital delay number encoder 320 . Digital delay number encoder 320 receives 4-bit delay control digital input 305 and generates signals from D0, D1... to D15. There are 16 delay scales (Tscale) in DTC delay unit. When D(n)=1, it means a A corresponding delay exists. Thus, the DTC delay unit receives the input signal 315 and outputs the delayed signal output 310 according to the 4-bit delay control digital input 305 .

Please refer to Figure 4. In a preferred embodiment of the present invention, the number of DTC delay units in the first delay circuit 400 and the second delay circuit 420 is equal to four, respectively. That is, N=4. The first delay circuit 400 responds to the first delay control signal (delay_control_count) having a value of k and the ext_clk signal to generate a first delay signal (delay_clk(k)), which is at least a function of k. The second delay circuit 420 responds to the second delay control signal (delay_control_count_1) having a value of k+1 and the ext_clk signal to generate a second delay signal (delay_clk(k+1)), which is at least a function of (k+1). The time difference between delay_clk(k) and delay_clk(k+1) is defined as a minimum resolution Tres, which is also the minimum resolution of the first delay circuit 400 and the second delay circuit 420 . So delay_clk(k) is one Tres ahead of delay_clk(k+1).

Furthermore, the internal delay signal (int_clk) generated by the half-resolution delay unit 435 is delayed by 1/2Tres from ext_clk. The first phase detector 445 compares int_clk with delay_clk(k), and outputs a first control signal (decrement); the second phase detector 455 compares int_clk with delay_clk+1, and outputs a second control signal (increment). In a preferred embodiment, the first phase detector 445 and the second phase detector 455 are D-flip-flops respectively.

In order for the first phase detector 445 and the second phase detector 455 to lock delay_clk(k) and delay_clk(k+1) correctly, int_clk should fall between delay_clk(k) and delay_clk(k+1). It is necessary to provide sufficient setup time (Tsetup) to the first phase detector 445 and sufficient hold time (Thold) to the second phase detector 455 . Therefore, Tres should be greater than the sum of Tsetup and Thold. That is, Tres≥(Tsetup+Thold). However, it is known that Tsetup is larger than Thold in most instances. Therefore, in a preferred embodiment, set:

Tres≥2*Tsetup...Equation (1).

In a preferred embodiment of the present invention, all the DTC delay units in the first delay circuit 400 and the second delay circuit 420 are the same. The minimum resolution Tres of the DTC delay unit is defined by twice the Tsetup of the above-mentioned D flip-flop. If the Tsetup of the D flip-flop is 0.2ns (nanosecond), then Tres can be selected to be 0.5ns, which is greater than 2*Tsetup, and the delay generated by the half-resolution delay unit is 0.25ns.

Refer to Figure 5. When delay_clk(k) is calibrated with ext_clk, it is locked. delay_clk(k) is exactly one clock cycle later than ext_clk, and delay_clk(k+1) is one clock cycle later than ext_clk plus Tres. In the locked condition, the first phase detector 445 sets the decrement signal to zero, and the second phase detector 455 sets the increment signal to zero. Then the delay circuit monitor 465 will not change the values of delay_control_count and delay_control_count_1.

The DTC delay unit 470 generates a delay signal 475 in response to ext_clk and delay_control_count. Therefore, in the example of N=4, a quarter-period delayed clock signal 475 can be obtained from the DTC delay unit 470 .

In the leading example shown in Figure 6, delay_clk(k) leads ext_clk by less than one clock cycle. In the leading example, the first phase detector 445 sets the decrement signal to zero, and the second phase detector 455 sets the increment signal to one. Then the delay circuit monitor 465 increases the values of delay_control_count and delay_control_count_1 respectively with an increment of 1. The first delay circuit 400 generates delay_clk(k) in response to ext_clk and delay_control_count. The second delay circuit 420 generates delay_clk(k+1) in response to ext_clk and delay_control_count_1. Therefore, the delays of the first delay circuit 400 and the second delay circuit 420 increase. If delay_clk(k) still leads ext_clk by less than one clock cycle, the dual-rail DLL circuit continues the steps described above until reaching the locked instance shown in FIG. 5 .

For the lag example shown in Figure 7, delay_clk(k) lags ext_clk by an amount less than one clock cycle. In the backward example, the first phase detector 445 sets the decrement signal to 1, and the second phase detector 455 sets the increment signal to 0. Then the delay circuit monitor 465 decreases the values of delay_control_count and delay_control_count_1 by taking 1 as the decrement amount. The first delay circuit 400 generates delay_clk(k) in response to ext_clk and delay_control_count. The second delay circuit 420 generates delay_clk(k+1) in response to ext_clk and delay_control_count_1. Therefore, the delays of the first delay circuit 400 and the second delay circuit 420 are reduced. If delay_clk(k) is still behind ext_clk by less than one clock cycle, the dual-rail DLL circuit continues the steps described above until the locked instance shown in FIG. 5 is reached.

In addition, if there are nonlinear characteristics in the circuit part of the DTC delay unit, it will not affect the convergence of the system. Because the two delay circuits 400 and 420 are symmetrical circuit structures, both of them will change in the same way and by the same percentage as the process, temperature, and supply voltage change. FIG. 8 shows the non-linearity of the delay scale (Tscale) of a single DTC unit occurring in the range of 8 (ie, 1000) to 9 (ie, 1001) of the delay control digital input 305 . Changing the value of Tscale from 0.125ns to 0.25ns results in a non-linear condition. Accordingly, as shown in FIG. 9 , the minimum resolution (ie, Tres) of the first delay circuit 400 and the second delay circuit 420 changes from 0.5 ns to 1 ns. Int_clk has a drift of 0.25ns relative to ext_clk. So int_clk still falls between delay_clk(k) and delay_clk(k+1), and the dual-rail DLL circuit can allow PVT (process, voltage, temperature) variation.

In addition, the dual-rail digital DLL design can easily generate T/N time delays, where N is the number of DTC delay units in the first delay circuit 400 and the second delay circuit 420 respectively, and T is the clock cycle time. Referring to the embodiment of FIG. 3 , it is assumed that the single DTC delay unit in the present invention does not have 16 delay scales, but has L Tscales. Then the equation derived below satisfies the locking condition, as shown in equation (2).

T=Tscale*L*N...Equation (2).

Then, Tres=delay_clk(K+1)-delay_clk(K)=Tscale*(K+1)*N-Tscale*L*N=Tscale*N...Equation (3).

From the above equations (1), (2) and (3), when the locked situation occurs, T=L*Tres≥2L*Tsetup...Equation (4).

From equation (2), Tscale≥(2/N)*Tsetup...Equation (5).

In a preferred embodiment, assuming that Tsetup=0.2ns, then from equation (1), Tres can be selected as 0.5ns, if the target cycle time (T) is 7.5ns (i.e. real clock frequency 133MHz), from equation (4) L = 15 can be selected in .

In another preferred embodiment, assuming that N=4 in equation (5), if Tsetup is selected to be 0.2ns, then Tscale≥0.5*Tsetup=0.1ns. Therefore Tscale should be larger than 0.1ns to allow PVT variation.

Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the appended claims.

Claims (10)

1. A circuit for generating a delayed signal, comprising: a first delay circuit, responsive to an external clock signal and a first delay control signal, to generate a first delay signal; a second delay circuit, in response to a second delay control signal and the external clock signal, to generate a second delay signal; a delay unit, responsive to the external clock signal, to generate an internal delay signal; a first phase detector, responsive to the internal delay signal and the first delay signal, to generate a first control signal; a second phase detector, responsive to the internal delay signal and the second delay signal, to generate a second control signal; a delay circuit monitor responsive to the first and the second control signals to generate the first delay control signal and the second delay control signal; and The DTC delay unit responds to the external clock signal and the first delay control signal to generate the delay signal. 2. The circuit as claimed in claim 1, wherein the first delay circuit and the second delay circuit respectively have N DTC delay units, and N is a predetermined number. 3. The circuit of claim 2, wherein N is equal to four. 4. The circuit of claim 1, wherein the internal delay signal generated by the delay unit is delayed by a 1/2Tres time compared to the external clock signal, where Tres is the time difference between the first delay signal and the second delay signal . 5. The circuit of claim 1, wherein the delay unit is further responsive to the first delay signal and the second delay signal. 6. The circuit as claimed in claim 1, wherein the first delay control signal and the second delay control signal have an initial value k and k+1 respectively, k is a number, and the delay circuit monitor is generated by the following steps The first and the second delay control signal: If the first control signal is 1 and the second control signal is 0, reduce the values of the first delay control signal (k) and the second delay control signal (k+1) by 1; and If the first control signal is 0 and the second control signal is 1, the values of the first delay control signal (k) and the second delay control signal (k+1) are incremented by 1. 7. The circuit of claim 2, wherein the delay signal generated by the DTC delay unit is delayed by a T/N time compared to the external clock signal, T is a cycle time of the external clock signal, and N is a predetermined number . 8. The circuit of claim 3, wherein the delay signal generated by the DTC delay unit is delayed by T/4 time compared with the external clock signal. 9. The circuit of claim 1, wherein the first phase detector is a D flip-flop. 10. The circuit of claim 1, wherein the second phase detector is a D flip-flop.

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