CN1148873C - Communication system, single-chip RF communication system and control method for RF communication system - Google Patents

Abstract

A single chip RF communication system and method and a VCO-mixer structure are provided. The RF communication system in accordance with the present invention includes a transmitter, a receiver, an antenna for receiving transmitting RF signals, a PLL for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signal having the carrier frequency, a demodulation-mixing unit for mixing the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The VCO in accordance with the present invention includes a plurality of differential delay cells, and the mixer includes a differential amplifying circuit and a combining circuit. The differential amplifying circuit of the multi-phase mixer includes two load resistors coupled to two differential amplifiers, respectively. The combining circuit includes bias transistors, first and second combining units coupled to the bias transistors, respectively, and a current source coupled to the first and second combining units. The first and second combining units include a first and second plurality of transistor units, respectively. Preferably, each of the plurality of transistor units includes a plurality of serially connected transistors, wherein the serially connected transistors are coupled in parallel with the serially connected transistors of the plurality of transistor units.

Description

Communication system, single-chip RF communication system and control method for RF communication system

field of invention

The present invention relates to a communication system, and more particularly to a CMOS radio frequency (RF) communication system. The present invention also relates to a voltage controlled oscillator (VCO) and mixer, and more particularly, to a multiphase VCO and mixer.

Related Technology Background

Currently, an RF communication system has various communication applications including PCS communication and IMT systems. Therefore, a CMOS chip integration of the system is pursued to reduce cost, size and power consumption.

Generally, the RF communication system is composed of RF front-end blocks and a baseband digital signal processing (DSP) block. Currently, the baseband DSP block can be implemented in low-cost and low-power CMOS technology. However, the RF front-end block cannot be realized by CMOS technology due to limitations in speed and noise characteristics, which are lower than the speed and noise specifications of currently used RF communication systems.

For example, the PCS cell phone system operates at frequencies in excess of 2.0 GHz, but current CMOS technology reliability can only operate up to about 1.0 GHz from a speed and noise standpoint. Therefore, the RF front-end block can be implemented using diode or dual CMOS technology, which has better speed and noise characteristics than CMOS technology, but is more expensive and consumes more power.

Currently, two different types of RF structures called "direct conversion" and "double conversion" are used in CMOS RF communication systems. Both structures have advantages and disadvantages of implementing CMOS.

1 shows a related art direct conversion complementary metal oxide semiconductor RF communication system 100, which includes an antenna 105, an RF filter 110, a low noise amplifier (LNA) 120, a first mixer 140, a second Mixer 145, a phase-locked loop (PLL) 130, a first low-pass filter (LPF) 150, a second LPF 155, a first analog/digital (A/D) converter 160, a second analog /digital converter 165 , a third mixer 160 and a power amplifier 170 .

The antenna 105 receives RF signals, and the selected RF signals are then filtered at the RF filter 110 . The filtered RF signal is amplified at the gain of the LNA 120, and the RF signal passing through the LNA 120 is directly demodulated into a baseband signal by multiplying with a 90 degree phase difference at the first and second mixers 140, 145. The PLL 130 ideally uses a voltage controlled oscillator (VCO) to generate two types of clock signals, the I signal and the Q signal. Except for the phase difference, the I clock and Q clock signals are identical. The I signal ideally has a 90 degree phase difference from the Q signal. That is, the Q signal is 90 degrees out of phase with the I signal. The two sets of signals I, Q are ideally used to increase the ability of the RF system to identify or maintain received data despite noise and interference. Transmitting two types of signals with different phases reduces the possibility of data loss or alteration. The demodulation frequency fo of Fig. 1 is equal to the modulation frequency fo.

The frequency of the demodulated baseband signal is the original frequency minus the frequency f _o to pass through the first and second LPFs 150, 155 and finally become analog at the first and second analog/digital converters 160, 165 /Digital conversion required for each signal. This digital signal is then transferred to a baseband discrete-time signal processing (PSP) block (not shown in the figure). Channel selection is performed by changing the frequency f _o on a phase locked loop (PLL) 130 .

One possible reason for the approximately 1 GHz limit in CMOS technology reliability is the structure of the VCO and mixer in the PLL 130 . FIG. 2 is a circuit diagram showing a background voltage controlled oscillator-mixer, wherein the VCO 10 includes four differential delay units 12, 14, 16 and 18, and has a structure similar to a ring oscillator. The four delay units 12, 14, 16, 18 are connected in series and generate a clock signal LO+ and an inverted clock signal LO-, each clock signal has a frequency f _o . The VCO 10 control circuit that generates a frequency control signal includes a phase frequency detector 4, a charge pump 6 that outputs the frequency control signal to each of the delay elements 12, 14, 16, 18 and a loop filter 8. The phase frequency detector 4 receives a reference clock signal f _ref from a reference clock divider circuit 2 and a VCO clock signal f _VCO from a VCO clock divider circuit 3 , respectively. The frequency f _o of the clock signals LO+ and LO- is represented by M/K(f _ref )=f _o . Therefore, the frequency f _o is based on the reference clock signal f _ref and the divider circuit 2 , 3 .

For example, mixer 20 of a Gilbert-multiplier multiplies the input signal, eg, RF signals RF+ and RF-, by clock signals LO+ and LO-. The mixer 20 includes two load resistors R1, R2 coupled to a source voltage VDD, eight NMOS transistors (NMOS) 21-28, and a current source _IS1 . The gates of the NMOS transistors 21, 22 are coupled to receive the clock signal LO+, while the gates of the NMOS transistors 23, 24 are coupled to receive the inverse clock signal LO−. The gates of the NMOS transistors 25 and 26 receive a common bias voltage V _Bias . The gates of the NMOS transistors 27, 28 respectively receive RF signals RF+, RF-. Therefore, the clock signal LO+, LO- will be multiplied by the RF signal RF+, RF- only when the transistors 25, 27 or transistors 26, 28 are switched to "ON" state at the same time. The frequency of the output signal OUT+, OUT- of the mixer 20 is lower than the original frequency by the frequency f _o of the clock signal LO+, LO-.

Although a wide frequency range and a low phase noise are required for various applications, the VCO-mixer architecture 10, 20 can only support frequencies up to about 1 GHz with reliable phase noise and frequency range. The performance of the VCO-mixer structure 10, 20 is degraded by phase noise and frequency range, and is unacceptable when the frequency of the clock signal LO+, LO- from the VCO increases. Therefore, when the frequency f _o of the clock signals LO+, LO- exceeds about 1 GHz, the VCO 10 and the mixer 20 cannot be realized.

As mentioned above, the related art direct conversion RF system 100 has the advantage of CMOS RF integration because it is simpler. In related art direct conversion RF systems, only a single PLL is required, and high quality filters are not required. However, the direct conversion structure of this related art has the disadvantage of making single-chip integration difficult or impossible.

As shown in Figure 3A, the clock signal cos ω _LO t from a local oscillator (LO) such as a VCO can leak to the mixer input or antenna, where radiation can occur because the local oscillator (LO) is connected to the RF the same frequency as the carrier. The unwanted transmit clock signal Δ(t)cos ω _LO t is reflected near the object and "re-received" by the mixer. The low-pass filter will output a signal M(t)+Δ(t) due to the leaked clock signal. As shown in Figure 3B, self-mixing of local oscillators can cause problems such as time-varying or "wandering" DC biases on the output of the mixer.

Figure 3B is a graph depicting the time variation versus DC bias. "A" indicates the signal before the mixer, and "B" indicates the signal after the mixer. The time-varying DC bias, along with the inherent circuit bias, can significantly reduce the dynamic range of the receiver section. Furthermore, direct conversion RF systems require a high frequency, low phase noise PLL for channel selection, which is not easily achieved using an integrated CMOS voltage controlled oscillator (VCO), for at least part of the reasons discussed above.

FIG. 4 is a block diagram showing a related art RF communication system 300 based on a doubling conversion structure of transistors considering all potential channels and frequencies. The RF communication system 300 includes an antenna 305, an RF filter 310, an LNA 320, a first mixer 340, a second mixer 345, and a first LPF 350, a second LPF 355, and a second stage mixer 370 - 373, a first adder 374, and a second adder 375. The RF communication system 300 further includes a third LPF380, a fourth LPF385, a first analog/digital converter 390, a second analog/digital converter 395, first and second PLL330, 335, a third hybrid device 360 and a power amplifier 370.

The mixers 340, 345, 370-373 are all used for demodulation, while the third mixer 360 is used for modulation. The first and second mixers 340, 345 are used for a selected RF frequency, while the second stage mixers 370-373 are selected for an intermediate frequency (IF). The first PLL 330 can generate a clock signal at a high frequency or RF frequency, and the second PLL 335 can generate a clock signal with a low frequency or an intermediate frequency (IF).

The transmit data is multiplied with the clock signal having the RF frequency from the PLL 330 to have a frequency that has the RF frequency subtracted from the frequency of the original transmit data. The output signal of the third mixer 360 is amplified by the power amplifier 370 and then transmitted through the antenna 305 .

For receiving data, the antenna 305 receives RF signals, and the filter RF 310 filters the RF signals. The filtered RF signal is amplified by LNA 320 and converted to an intermediate frequency signal by 90 degree phase difference mixers 340, 345 and a single frequency local oscillator, usually a VCD. The PLL 330 can generate clock signals of the I signal and the Q signal of the RF signal. The first mixer 340 may multiply the RF signal with a clock signal of the I signal having an RF frequency, and the second mixer 345 may multiply the RF signal with a Q signal having an RF frequency. The LPF 350, 355 is used at the IF stage (i.e., first stage) to remove any unconverted frequency components when converted to an IF signal, which allows all channels to pass through the third stage mixer 370-373. All channels at the IF stage can then be frequency converted directly to baseband frequency signals by an adjustable PLL 335 for channel selection.

The demodulated baseband signal C is passed through filters (LPF) 380, 385 and converted into digital data by analog/digital converters 390, 395. The digital data is then converted to a baseband discrete-time processing (DSP) block (not shown in the figure).

As described above, the related art double conversion RF system 300 has various advantages. The related art double-converted RF system 300 can perform channel modulation using a lower frequency, ie, intermediate frequency, second PLL 335, rather than a high frequency, ie, RF, first PLL 330. As a result, the high frequency RF PLL 330 may be a fixed frequency PLL that can be optimized more efficiently. Furthermore, since the channel modulation is performed at lower frequency operation using the intermediate frequency PLL 335, the phase noise generation of the channel selection can be reduced.

However, the related art double conversion RF system 300 has various disadvantages. The double-switching RF system of this related art has two PLLs 300 that are not easily integrated in a single chip. In addition, the frequency of the first PLL is maintained to be implemented in CMOS technology, more specifically, using a CMOS VCD. The structure of the VCD and mixer has about 1 GHz limit on the reliability of CMOS technology. Also, a self-mixing problem still occurs because the second PLL is on the same frequency as the desired IF carrier. FIG. 5A depicts the clock signal leakage in the RF communication system 300, while FIG. B depicts the time variation and "wandering" of the DC bias due to the leakage clock signal Δ(t)cos in the RF communication system 300 of FIG. 4 ω _LO2 (t) (eg, self-mixing).

In FIG. 5A, the first mixer multiplies the RF signal with the clock signal cos ω _Lo1 of RF having frequency W _LO1 and outputs an RF signal of M(t) cos ω _LO2 t having frequency W minus The frequency of _LO1 . The second mixer multiplies the RF signal from the first mixer with a clock signal cos ω _LO2 having an intermediate frequency of frequency ω _LO2 . However, before the LPF, since the output signal frequency of the second mixer is the same as the required RF carrier frequency. Thus, the output signal of the second mixer can leak to a substrate or leak back to the second mixer. This time-varying DC bias, along with the inherent circuit bias, can significantly reduce the dynamic range of the receiver section.

The aforementioned references are hereby incorporated by reference for full descriptions of additional or optional details, features, and technical background.

Summary of the invention

An object of the present invention is to at least substantially avoid the problems and disadvantages of the related art.

A further object of the present invention is to manufacture a CMOS RF front-end and method of using the front-end, which allow a chip integration of an RF communication system.

It is a further object of the present invention to provide an RF communication system and method that reduces cost and power requirements.

Still another object of the present invention is to provide a reliable high speed, low noise CMOS RF communication system and methods of using the same.

It is a further object of the present invention to increase the frequency range of an RF front end of an RF communication system.

A further object of the present invention is to fabricate a VCO-mixer on a single substrate.

Another object of the present invention is to increase the frequency range of a VCO-mixer structure.

Still another object of the present invention is to reduce the noise of a VCO structure.

Another object of the invention is to increase the performance of the VCO-mixer architecture.

To achieve at least all or part of the above objects and advantages according to the purpose of the present invention, as specifically expressed and broadly described, a communication system of the present invention includes: a receiver unit, which receives a A signal for selecting a signal; a single phase-locked loop that generates more than two multiphase clock signals having a frequency different from the carrier frequency, wherein the multiphase clock signals are combined to generate a signal having a frequency higher than the carrier frequency a plurality of local oscillator signals at a second frequency of frequency; and a demodulation mixer that mixes said received selection signal and said more than two multiphase clock signals to output a signal having a frequency minus the carrier frequency frequency selection signals, wherein each of said local oscillator signals demodulates one of an I carrier frequency signal and a Q carrier frequency signal.

To further achieve the whole or part of the purpose according to the purpose of the present invention, a single-chip RF communication system includes: a transceiver for receiving and transmitting RF signals; a single phase-locked loop for generating A plurality of 2N phase clock signals of substantially the same frequency 2*f ₀ /N of the carrier frequency f ₀ , wherein N is a positive integer, which is regarded as the phase number; a demodulation mixing unit is used to convert the RF signal from the transceiver mixed with a plurality of 2N phase clock signals from the phase-locked loop to output an RF signal having a frequency minus the carrier frequency, wherein the demodulation mixer comprises a plurality of two-input mixers; wherein the plurality of 2N a phase clock signal combined to demodulate at least one of the I carrier frequency signal and the Q carrier frequency signal; and an analog/digital conversion unit for converting the RF signal from the demodulation mixing unit into a digital signal.

Still further according to the purpose of the present invention to achieve the whole or part of the purpose, a control method of an RF communication system, comprising: receiving a signal including a selection signal having a carrier frequency; generating more than two multi-phase clocks signals, each multiphase clock signal having a substantially identical frequency different from the carrier frequency, said multiphase clock signals being combined to generate a plurality of local oscillator signals having a second frequency higher than the frequency; and The received carrier frequency selection signal is mixed with said more than two multi-phase clock signals to output a demodulated selection signal having a frequency subtracted from the carrier frequency so as to obtain from said more than two multiphase clock signals The corresponding local oscillator signal combined with the clock signal demodulates one of the first carrier frequency signal and the second carrier frequency signal.

Additional advantages, objects, and features of the present invention will be apparent in part from the following description and in part in the description of the state of the art, or can be learned by practice of the present invention. The objects and advantages of the invention will be apparent from and particularly pointed out in the appended claims.

A brief description of the drawings

The present invention will be described in detail with reference to the following drawings, in which like reference numerals indicate like elements, in which:

FIG. 1 is a circuit diagram showing a related art RF communication system;

Fig. 2 is a circuit diagram of a related art voltage-controlled oscillator-mixer structure;

Figure 3A is a clock signal leakage shown in the circuit of Figure 1;

Figure 3B is a "self-mixing" diagram showing the circuit of Figure 3A;

4 is a circuit diagram showing another related art RF communication system;

Figure 5A is a diagram showing clock signal leakage in the circuit of Figure 4;

Figure 5B is a "self-mixing" scheme shown in the circuit of Figure 5A;

6 is a diagram showing a first embodiment of a polyphase low frequency (MPLF) RF communication system in accordance with the present invention;

FIG. 7 is a block diagram showing an example of a PLL circuit;

8 is a block diagram showing a receiving part of an RF communication system according to another embodiment of the present invention;

9 is a block diagram showing the RF communication system of FIG. 8 with 6 phases;

10 is a block diagram showing a receiving portion of an RF communication system still according to an embodiment of the present invention;

11 is a block diagram showing the RF communication system of FIG. 10 with 6 phases;

FIG. 12 is a block diagram showing a receiving part of an RF communication system still according to an embodiment of the present invention;

13A is a block diagram showing an example of a VCO-mixer structure;

FIG. 13B is a circuit diagram showing the VCO-mixer structure of FIG. 13A;

14 is a circuit diagram showing another example of a VCO-mixer; and

15A-15H are waveform diagrams showing the operation timing of FIG. 14 .

Detailed Description of the Preferred Embodiment

A single-chip RF communication system using CMOS technology has various requirements. A complementary metal oxide semiconductor voltage controlled oscillator (VCO) has poor noise characteristics. Therefore, a complementary metal-oxide-semiconductor phase-locked loop (PLL) integration is required, however, the number of PLLs should be small, and the intermediate frequency of a PLL should ideally be sufficiently different from a transmitted RF frequency (e.g., ideally ground is low enough) to use the CMOS VCO to control a phase noise result. High quality filters can ideally be eliminated because of the associated disadvantage areas and power specifications. Also, many components in a CMOS RF system should be small or reduced without reducing efficiency.

The first preferred embodiment of the present invention is a "multiphase low frequency" (MPLF) switching RF communication system 500 shown in FIG. 6, and ideally can be formed on a single CMOS chip. The first preferred embodiment is capable of operating at frequencies in excess of about 1 GHz. The term "multiphase low frequency conversion" will be used because a single phase periodic signal with high frequency can ideally be obtained by multiplying a multiphase low frequency periodic signal. The first preferred embodiment of the MPLF converted RF communication system 500 includes a front-end MPLF RF block 502 and a digital signal processing (DSP) block 504, which is ideally baseband. As mentioned above, related art DSP blocks can be formed in CMOS technology. Therefore, a detailed description of the DSP block including a digital signal processor 550 will be omitted.

The MPLF conversion RF block 502 includes an antenna 505 , an RF filter 510 (eg, bandpass filter), a low noise amplifier (LNA) 520 and first and second mixers 530 , 560 . The MPLF conversion RF block 502 further includes a phase-locked loop (PLL) 540, a low-pass filter (LPF) 580, an analog/digital (A/D) converter 590, and an A power amplifier 570 coupled between 505. The PLL 540 can generate a modulation and demodulation clock, ie, a local oscillator (LO), whose frequency is determined by a reference clock (REF f ₀ ).

FIG. 7 is a block diagram showing an embodiment of the PLL 540 . The PLL 540 includes reference and main dividers 610, 620, a phase comparator 630, a loop filter 640, and a voltage controlled oscillator (VCO) 650, respectively. The VCO 650 outputs an LO frequency f ₀ , which is compared by a phase comparator 630 to a reference clock signal. The output signal of the phase comparator 630 will pass through the loop filter 640 and be used as a control signal (eg, frequency) of the VCO 650 . Depending on the communication system, the frequency of the LO is ideally variable. For example, the LO frequency of a personal communication system (PCS) can be about 1.8 GHz, while the LO frequency of an IMT 2000 system is about 2.0 GHz.

In the first preferred embodiment of the MPLF converted RF communication system 500 shown in FIG. 6, the transmission data is received by the MPLF RF block 502 from the DSP block 504. The transmit data is modulated by an ideally modulated second mixer 560 at the LO frequency. The modulated data is amplified by the power amplifier 570 and output by the antenna 505 .

The low noise amplifier (LNA) 520 can receive an input signal from the antenna 505 and amplify the signal level to output an RF signal. The RF BPF 520 is ideally coupled between the antenna 505 and the LNA 520. The RF signal is ideally demodulated by a demodulation first mixer 530 at the same frequency as the modulation frequency. The output of the demodulation mixer 530 becomes received data by passing through the LPF 580. The received data is ideally converted to a digital signal by analog/digital converter 590 and output to DSP 550.

In order to use a single PLL with an intermediate frequency sufficiently lower than the transmit RF frequency, the first preferred embodiment of the MPLF-converted RF communication system 500 uses a single-phase high-frequency periodic signal obtained by multiplying a multi-phase low-frequency periodic signal (ie, RF frequency). In particular, although the invention is not intended to be limiting, a high frequency "sine" and "cosine" signal needs to be used in RF systems. The sine and cosine signals with ω _RF frequency can be obtained by multiplying the N-phase sine signal with 2 ω _RF /N frequency as shown in Equations 1 and 2 below:

$\mathrm{<span\; class="notranslate">\; cos</span>}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; RF</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\frac{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}\underset{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\frac{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; II</span>}}}\mathrm{<span\; class="notranslate">\; sin</span>}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; RF</span>}}}{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; k\&pi;</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; \&pi;</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

$\mathrm{<span\; class="notranslate">\; sin</span>}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; RF</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\frac{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}\underset{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\frac{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; II</span>}}}\mathrm{<span\; class="notranslate">\; sin</span>}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; RF</span>}}}{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; k\&pi;</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

A multiplication factor is not "N" but "N/2" because the remaining N/2 sinusoids can be an inverse of the first N/2 sinusoids. The inverted signal is ideally used to create a differential signal for a differential input mixer.

FIG. 8 shows a receiving section 700 of the second preferred embodiment of an RF block according to the present invention, which can be used in the first preferred embodiment of the MPLF converted RF communication system. The receiving part 700 includes an antenna 715 , an RF filter 720 , an LNA 725 and a demodulation mixer 730 . The receiving part 700 of the RF block further includes a PLL 740 , a low-pass filter 780 and an analog/digital converter 790 . The PLL 740 can generate a demodulation clock, ie, a local oscillator (LO) equal to 2*f ₀ /N, whose frequency is determined by a reference clock (not shown in the figure). The operation of the antenna 715, the RF filter 720, the LNA 725, the LPF 780, and the analog/digital converter 790 is similar to that of the first preferred embodiment, so detailed descriptions are omitted.

The receiving part 700 of the RF block uses a PLL 740 . The PLL 740 uses 2*f ₀ /N frequency and generates a total of 2N phase clock signals. The PLL 740 can generate N-phase ± LO cos (k, t) and N-phase ± LO _sin (k, t) signals, which are ideally determined as in Equations 3-4 below.

$<span\; class="notranslate">\; \&PlusMinus;</span>\mathrm{<span\; class="notranslate">\; L</span>}{\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; cos</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; \&PlusMinus;</span>\mathrm{<span\; class="notranslate">\; sin</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; RF</span>}}}{\mathrm{<span\; class="notranslate">\; N</span>}}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; k\&pi;</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; \&pi;</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; wxya</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0,1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; \&CenterDot;</span>\frac{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

$<span\; class="notranslate">\; \&PlusMinus;</span>\mathrm{<span\; class="notranslate">\; L</span>}{\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; sin</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; \&PlusMinus;</span>\mathrm{<span\; class="notranslate">\; sin</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; RF</span>}}}{\mathrm{<span\; class="notranslate">\; N</span>}}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; k\&pi;</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; wxya</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0,1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; \&Center\; Dot;</span>\frac{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

As shown in FIG. 8, the receive portion 700 of the RF block has a demodulation mixer 730 divided into upper and lower mixer arrays 732,734. The upper and lower mixer arrays 732 , 734 each include a plurality of conventional 2-input mixers 735 . The upper mixer array 732 multiplies a sinusoidal signal of N phases (N/2: non-reverse, N/2 reverse) (frequency is (2ω _RF )/N) with an RF signal, which is equivalent to multiplying a single The cosine signal at ω _RF frequency is multiplied with the RF signal. The non-inverted and inverted sinusoidal signals need to be fed into a single mixer since the conventional 2-input mixer requires differential inputs. The lower mixer array 734 is to combine N-phase (N/2 non-inverted, N/2 inverted) sinusoidal signals at frequency ω _RF /N with RF signals, which is equal to single-phase ω _RF sinusoidal signals and The RF signal is multiplied. Therefore, the receiving portion 700 of the RF block is functionally similar to the direct conversion structure shown in FIG. 1 . However, the receiving part 700 according to the present invention is demodulated using N-phase, 2ω _RF /N frequency sinusoidal signals instead of single-phase ω _RF sinusoidal signals.

As mentioned above, the PLL 740 can generate 2N phase clock signals. The N-phase clock signal is an N-phase sine signal and an N-phase cosine signal. The two N-phase signals include N/2 non-inverted signals and N/2 inverted signals. The N-phase sinusoidal signal is input to the upper mixer array 732 along with the RF signal, and the N-phase sinusoidal signal is input to the lower mixer array 734 along with the RF signal. The upper and lower mixer arrays 732 and 734 respectively have a plurality of mixers 735 and M stages. The M stages include a first stage, (e.g., 735), a second stage (e.g., 735'), ..., an M-1th stage, and an Mth stage (e.g., 735"). Each mixer array Each stage of E includes at least one mixer with two inputs. The number of mixers K1 on the first stage is the highest number of stages. The last stage Mth stage has the least number of mixers (KM) in the whole stage. The relative number of mixers among the stages can be expressed as inequality K1>K2>K3>K4... KM-1>KM.

Each mixer 735 has two inputs. Each input has an inverted signal and a non-inverted signal of the inverted signal because each input of the mixer 735 inputs two different signals. As mentioned above, the RF signal from the LNA 725 and the N signal from the PLL 746 are input signals to the mixer 735 at the first stage. The output signal of mixer 73 on the first stage is used as the input signal of mixer 735' on the second stage. In the same way, the mixer output signal on stage M-1 is used as the two input signals of mixer 735", which is on the Mth stage of the upper mixer array 732 and the lower mixer array 734 single mixer.

FIG. 9 is a 6-phase example showing a receive section 700 of an MPLF converted RF communication system using a conventional 2-input mixer. A PLL 840 generates a 12-phase sinusoidal signal that can be sent to mixer 830 . The phase difference between two adjacent signals is π/6 (ie, 2π/12). The phases (0, 2, 4, 6, 8, 10) are used as input to the above mixer 832 and are multiplied with ideally the RF input, which is equal to the product of cos(ω _RF t) times the RF input. The phases (1, 3, 5, 7, 9, 11) are input to the mixer 834 below and are ideally multiplied by the RF input to be equal to sin(ω _RF t) times the RF input. Therefore, when the clock signal is multiplied by the RF signal, the frequency of the clock signal is f ₀ .

The PLL 840 includes a clock generator such as a voltage controlled source (VCO), and thus generates a 12-phase clock signal multiplied by RF when modulated. The generated clock signal has a frequency 2*f ₀ /P (P=number of phases) lower than frequency f ₀ to be multiplied with the RF signal. The clock signal from PLL 840 has a lower frequency 2*f ₀ /P because PLL 840 generates a multi-phase clock signal phase 0, . . . , phase 12. The filtered RF signal is gain-amplified at LNA 725 and multiplied with the multiphase clock signal to generate 12 sinusoidal signals at mixer array 830 for modulation. The frequency of the RF signal multiplied by the clock signal is lower than the initial frequency by the final frequency f ₀ of the clock signal.

The original frequency 2*f ₀ /P of the clock signal from PLL 840 is changed to f ₀ for multiplication with the RF signal at mixer (eg, mixer array) 830 . Therefore, the upper mixer array 832 and the lower mixer array 834 can be combined into a clock signal with 2*f ₀ /P, and the clock signal with frequency f ₀ can be multiplied by the RF signal. As a result, an RF signal having a frequency reduced by the frequency f ₀ may pass through the LPF 780 and the A/D converter 790, and be transferred to a DSP section (not shown in the figure). The 12-phase sinusoidal signal generated by PLL 840 is as follows:

Phase 0: $\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t+\frac{\mathrm{\&Pi;}}{6})$

Phase 1: $\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{<figure-callout\; id="3"\; label="RF"\; filenames="C9980876400291.png,C9980876400361.png"\; state="\{\{state\}\}">RF</figure-callout>}}}{3}\&Center\; Dot;t)$

Phase 2: $\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{\mathrm{\&Pi;}}{6})$

Phase 3: $\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{2\mathrm{\&Pi;}}{6})$

Phase 4: $\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{3\mathrm{\&Pi;}}{6})$

Phase 5: $\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{4\mathrm{\&Pi;}}{6})$

Phase 6: $-\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t+\frac{\mathrm{\&Pi;}}{6})$

Phase 7: $-\sin \left(\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t\right)$

Phase 8: $-\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{\mathrm{\&Pi;}}{6})$

Phase 9: $-\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{2\mathrm{\&Pi;}}{6})$

Phase 10: $-\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{3\mathrm{\&Pi;}}{6})$

Phase 11: $-\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{4\mathrm{\&Pi;}}{6})$

FIG. 10 shows an MPLF conversion receiving part 900 of an RF block according to the third preferred embodiment of the present invention, which can be used in the first preferred embodiment of the MPLF conversion RF communication system. The receiving part 900 includes an antenna 915 , an RF filter 920 , an LNA 925 and a mixer 930 . The receiving part 900 of the RF block further includes a PLL 940 , an LPF 90 and an analog/digital converter 990 . The PLL 940 ideally generates a demodulation clock, ie, a local oscillator (LO) ideally equal to 2*f _RF /N, whose frequency is determined by a reference clock (not shown in the figure). The antenna 915, RF filter 920, LNA 925, LPF 980, and analog/digital converter 990 are similar in operation to the first preferred embodiment, and thus detailed descriptions will be omitted.

The receiving part 900 of the RF block uses only one PLL. The PLL 940 includes a clock generator 942 ideally using a frequency of 2*f ₀ /N. The clock generator 942 can ideally generate N-phase ±LO _cos (k,t) and N-phase ±LO _sin (k,t) signals, which collectively have 2N phase signals. The clock generator 942 is ideally a multiphase VCO, and the mixing section 930 is also a multiphase mixer.

As shown in FIG. 10 , the receive portion 900 of the RF block uses multiphase mixers 932 and 934 . The upper multiphase mixer 932 takes over the function of the upper mixer array 732 and the lower multiphase mixer 934 takes over the function of the lower mixer array 734 .

The PLL 940 generates clock signals for modulation and demodulation. The clock generator 942 of the PLL 940 can generate a clock signal having a frequency of 2*f ₀ /N (N=number of phases) for demodulation and modulation. The clock generator 942 can generate a clock signal with a frequency of 2*f ₀ /N because of the frequency limit implemented by CMOS devices. For a CMOS implementation of an RF communication system, the frequency of the clock generator 942 should be different and lower than that of the mixing section 930 .

FIG. 11 is a 6-phase example showing the receive section 1000 of an MPLF-converted RF communication system using multi-phase input mixers. A PLL 1040 generates 12-phase sinusoidal signals, which are sent to a multiphase mixer 1030 . Phase (0, 2, 4, 6, 8, 10) is used as an input to an upper mixer 1032 and is multiplied with ideally the RF input, which is equal to the product of cos(ω _RF t) and RF input. The phases (1, 3, 5, 7, 9, 11) are input to the mixer 1034 below and are ideally multiplied with the RF input, which is equal to the product of sin(ω _RF t) times the RF input.

FIG. 12 shows an MPLF conversion transmission part 1100 of an RF block according to the fourth preferred embodiment of the present invention, which can be used in the first preferred embodiment of the MPLF conversion RF communication system. The receiving section 1100 includes an antenna 1105, a mixer 1160, a PLL 1140, a plurality of LPFs 1180, a plurality of digital/analog (D/A) converters 1190, and a power coupled between the mixer 1160 and the antenna 1105. Amplifier 1170. The PLL 1140 can use a clock generator 1142 to generate clock signals. The clock generator 1142 ideally uses a local oscillator (LO) to generate a modulation and demodulation clock signal whose frequency is determined by a reference clock (f _RF ).

In a fourth preferred embodiment of the transmitting part 1100 of an RF block, digital data is received from a DSP block (not shown in the figure), and converted into an analog signal by a digital/analog converter 1190, and transmitted by an LPF 1180 filtering. The mixer 1160 ideally receives a polyphase low frequency (ie, 2*f ₀ /N) clock signal from the PLL 1140 and a baseband signal from the LPF 1180 to generate a modulated RF signal at frequency f _RP . The mixer 1160 desirably includes a multiphase upconverting mixer 1165 . FIG. 12 also shows a block diagram of an embodiment of the multiphase upconverting mixer 1165 . The mixer 1165 uses two control circuit blocks 1162 and 1164, which receive clock signals LO(0, . . . , N-1), /LO(0, . . . , N-1) to generate the modulated RF signal. The modulated RF data is amplified by the power amplifier 1170 and then output by the antenna 1105 .

As described above, the demodulating mixer can reduce a high frequency RF signal having the frequency of the clock signal by multiplying the RF signal by the clock signal. In the fourth preferred embodiment, the mixer 1160 ideally modulates the transmit data so as to increase the frequency of the low frequency transmit data in increments of the combined clock signal frequency. When modulating, the effect of noise on the transmitted data is not as significant as when demodulating. However, reducing the frequency of the clock signal LO(0, . . . , N-1) does reduce or remove noise such as parasitic capacitance. Furthermore, the frequency limit of CMOS technology of around 1 GHz can be overcome. Therefore, the fourth preferred embodiment has the same advantages as the third preferred embodiment.

FIG. 13A is a block diagram of a VCO-mixer structure according to a preferred embodiment of the present invention. This Voltage Controlled Oscillator-Mixer circuit is described in Kyeongho Lee's US Patent Application Serial No. 09/121,863, entitled "VOC-MIXERSTRUCTURE", which is listed here for reference only. The architecture includes a multiphase voltage controlled oscillator VCO 1250 and a multiphase mixer 1200. The multiphase mixer 1200 includes a differential amplifier circuit 1200A and a combination circuit 1200B.

When using a reference frequency signal with f _REF =f ₀ reference clock, the multi-phase VCO 1250 can generate a plurality of N-phase clock signals LO (i=0 to N-1) with a frequency of 2*f ₀ /N , where N= _ND *2, and _ND is equal to the number of delay cells in the multiphase VCO 1250 . In other words, the VCO 1250 can reduce the frequency f ₀ to 2*f ₀ /N. This reduces the phase noise of the polyphase VCO and increases the frequency range.

A plurality of N-phase intermediate clock signals LO(0), _LO (1), . Input signals of signals RF+, RF- are input to this differential amplifier circuit 1200A. The differential amplifier circuit 1200B can differentially amplify the radio frequency signals RF+, RF-. The combining circuit 1200B is responsive to a bias voltage V _bias and combines the N-phase intermediate clock signals LO(0)-LO(N-1) to generate output clock signals LOT+, LOT- with an initial frequency f ₀ . The mixer 1200 can then effectuate the multiplication of the output clock signal LOT+, LOT- by the RF signal RF+, RF-. FIG. 13B is an example circuit diagram depicting a VCO-mixer structure 1250 , 1200 . Multi-phase VCO 1250 includes a number of delay cells 1250 ₁ -1250 _ND connected in series. Based on this configuration, the multiphase VCO can generate a plurality of N-phase intermediate clock signals LO(0)-LO(N-1) having a frequency of 2*f ₀ /N. The VCO 1250 control circuit for generating a frequency control signal includes a phase frequency detector 1254, a charge pump 1256 and a loop filter 1258, which can output the frequency control signal to each of the delay units _{12501-1250 ND} . The phase frequency detector 1254 can receive a reference clock signal f _ref and a VCO clock signal from a reference clock divider circuit and a VCO clock divider circuit 1253 respectively. The frequency of the clock signal LO(φ)-LO(N-1) is represented by M'/K'(f _ref )=2f ₀ /N. Thus, the frequency f ₀ is based on the reference clock signal f _ref and the divider circuit 1252 , 1253 . In other words, f _VCO may be 2f ₀ /N setting M′/K′ of the divider circuits 1252 , 1253 .

The differential amplifier circuit 1200A of the multiphase mixer 1200 includes two load resistors R1 ′, R2 ′, and these load resistors are respectively coupled to two differential amplifiers 1200A ₁ , 1200A ₂ . The first differential amplifier _1200A1 includes two NMOS transistors 1210 , 1212 , and the second differential amplifier 1200A2 also includes two NMOS transistors 1214 , 1216 . The drains of the NMOS transistors 1210, 1216 are respectively coupled to the load resistors R1', R2', and the gates of the NMOS transistors 1210, 1216 are coupled for receiving the RF signal RF+. In addition, the drains of the NMOS transistors 1212, 1214 are respectively coupled to the load resistors R2', R1', and the gates are coupled to receive the RF signal RF-. The sources of NMOS transistors 1210, 1212 and NMOS transistors 1214, 1216 are coupled to each other and to the combinational circuit 1200B of the multiphase mixer.

The differential amplifiers 1200A ₁ , 1200A ₂ differentially amplify the RF signals RF+, RF- respectively, so as to obtain more accurate output signals OUT-, OUT+. In addition, the differential amplification removes noise that may be added to the RF signals RF+, RF-. In the current preferred embodiment, two differential amplifiers 1200A ₁ and 1200A ₂ are included. However, alternative embodiments of the invention may also be implemented using only one of the differential amplifiers.

The combination circuit 1200B includes bias voltage NMOS transistors 1232, 1234, a first combination unit 1200B, and a second combination unit 1200B ₂ , the latter two are respectively coupled to bias voltage NMOS transistors 1232, 1234, and a current source I _s1 coupled to to the first and second combination units 1200B ₁ , 1200B ₂ . The first combination unit 1200B ₁ includes a plurality _of transistor units 1220 ₀ , 1220 ₂ , _{. . . 1} .

Ideally, each of the plurality of transistor cells comprises a plurality of series transistors, wherein the series transistors are coupled in parallel with the series transistors of the plurality of transistor cells. Ideally, each transistor cell includes two (2) transistors in series. Therefore, in a preferred embodiment, there are N/2 transistor units in each combination unit 1200A or 1200B, so that the total number of NMOS transistors is 2*N.

The gates of the biased NMOS transistors 1232, 1234 are coupled to receive a bias voltage V _Bias , and the gates of the transistors in the first and second plurality of transistor cells are coupled to receive a corresponding voltage of 2*f ₀ / N-phase intermediate clock signals LO(i) and /LO(i) of N frequency, where /LO(i)=LO(N/2+i), i=0, 1..., N/2-1. In the presently preferred embodiment, the bias NMOS transistors 1232, 1234 are included to avoid errors. However, such transistors may be omitted in alternative embodiments. In addition, the sequential on-off operation of 2*N NMOS transistors of the combinational circuit 1200B corresponds to a NAND logic circuit, which can be replaced by an equivalent logic circuit and structure in another embodiment.

The structure of FIG. 13B allows the integration of the multiphase VCO 1250 and the multiphase mixer 1200 on a single chip, ie, using CMOS technology on a single semiconductor substrate. This structure and design can reduce the noise including that generated by the parasitic capacitance. As mentioned above, using the differential amplification of the RF signals RF+ and RF− in the differential amplifier circuit 1200A can reduce noise.

Dividing the N-phase intermediate clock signal LO(i) with a frequency of 2*f ₀ /N by the reference frequency f ₀ can also reduce noise. When multiple transistors are formed on the same substrate, such as CMOS technology semiconductor substrates, multiple PN junctions can be formed on the substrate. Most of this parasitic capacitance exists in the PN junction. If the frequency applied to the gate of the transistor is very high, the higher frequency f ₀ will cause more noise than the reduced frequency of 2*f ₀ /N.

In addition, the operation of the differential amplifier circuit 1200A and the combining circuit 1200B is determined by the output clock signals LOT+, LOT- having frequency f0, the latter two signals are respectively provided by the first and second combining units 1200B ₁ , 1200B ₂ , which means This is achieved by combining an N-phase intermediate clock signal LO(i) with a frequency of 2*f ₀ /N. When the bias voltage V _Bias is applied, the NMOS transistors 1232 and 1234 are turned on and off based on the output signals LOT+ and LOT−. Although the NMOS transistors 1210, 1212, 1214, and 1216 are turned on by the PF signals RF+, RF- provided to the gates, when the bias NMOS transistors 1232, 1234 are turned on by the clock signals LOT+, LOT- , the amplification of the RF signals RF+, RF- for generating the output signals OUT+, OUT- and the amplification of the output clock signals LOT+, LOT- will be performed.

Fig. 14 is another preferred embodiment describing the multiphase VCO and multiphase mixer when _ND = 3 and N = 6, and Figs. 15A-15H describe the preferred embodiment circuit shown in Fig. 14 operation sequence diagram. The multi-phase VCO 1250 includes 3 delay units 12501-12503 to generate 6-phase intermediate clock signals LO(0)-LO(5). A circuit example of 5 transistors including delay cells 1250 ₁ -1250 ₃ (ie, the delay cell 1250 ₁ ) is also shown. To illustrate, if the input clock signal has a frequency f ₀ =1.5 GHz, the 6-phase intermediate clock signals LO(0)-LO(5) have a frequency of 0.5 GHz.

The 6-phase mixer 1280 includes a differential amplifier circuit 1280A and a combination circuit 1280B. The differential amplifier circuit 1280A includes a first differential amplifier _1280A1 having NMOS transistors 1260 and 1262; a second differential amplifier _1280A2 having NMOS transistors 1264 and 1266 coupled to load resistors R3 and R4 respectively . The combining circuit 1280B includes a first and a second combining unit 1280B ₁ , 1280B ₂ , both of which are commonly coupled to a current source I _s2 . The first and second combination units 1280B ₁ , 1280B ₂ are respectively coupled to the first and second differential amplifiers 1280A ₁ , 1280A ₂ via bias NMOS transistors 1282 , 1284 , which are biased by a bias voltage V _Bias . pressure. Repeatedly, the first and second combination cells 1250B ₁ , 1250B ₂ include 6 transistor cells 1270 ₀ -1270 ₅ , and there are 10 transistors in total.

As shown in Figures 15A-15F, the 6-phase VCO 1250 can generate 6-phase intermediate clock signals LO(1)-LO(5) with a reduced frequency f ₀ /3. The 6-phase mixer 1250 receives 6-phase intermediate clock signals LO(1)-LO(5) and the RF signals RF+ and RF-. Each intermediate clock signal LO(1)-LO(5) and /LO(0)-/LO(2) (where /LO(0)=LO(3), /LO(1)=LO(4) and /LO(2)=LO(5)) is applied to a corresponding transistor of the first and second combinational cells 1280B ₁ , 1280B ₂ . The first and second combining units 1280B ₁ , 1280B ₂ combine 6-phase intermediate clock signals LO(0), LO(1), . . . , LO(4), LO(5) with frequency f ₀ /3 to generate The output clock signals LOT+ and LOT- have a frequency f ₀ .

When LO(0) is high and LO(1) is low (LO(4): high), the two output signals LOT+, LOT- are low and high respectively. When LO(1) is high and LO(2) is low (LO(5): high), the output signals LOT+, LOT- are high and low, respectively. When LO(2) is high and LO(3) is low (LO(0): high), the output signals LOT+, LOT- are low and high, respectively. When LO(3) is high and LO(4) is low (LO(1): high), the output signals LOT+, LOT- are high and low, respectively. When LO(4) is high and LO(5) is low (LO(2): high), the output signals LOT+, LOT- of the mixer 503 are low and high, respectively. When LO(5) is high and LO(0) is low (LO(3): high), the output signals LOT+, LOT- are low and high, respectively.

Each pair of NMOS transistors in the combinational circuit is sequentially turned on, thereby generating output signals LOT+ and LOT- as shown in FIGS. 15G and 15H.

As mentioned above, the preferred embodiment has various advantages. The preferred embodiment of the MPLF converted RF communication system does not require any high quality filters and uses only 1 PLL. Therefore, the MPLF switching structure can be easily integrated on a CMOS chip. In addition, the frequency of the channel selection PLL is reduced from F _RP to (2f _RP )/N, which results in a reduction in phase noise of a clock generation circuit of the VCO and ease of channel selection. In particular, the PLL frequency (LO) is different from (eg smaller than) the carrier frequency. As a result, the preferred embodiment of the MTLF RF communication system includes at least the advantages of direct conversion and double conversion communication systems of the related art, while eliminating the disadvantages of both architectures.

Furthermore, a robust and low noise CO and mixer can be fabricated on a single substrate, ideally implemented on a semiconductor substrate using CMOS technology. The interference caused by the input signal and the input clock signal can be significantly reduced because the frequency of the intermediate clock signal is offset from the modulation frequency list. The phase-locked loop (PLL) frequency range can be increased because the PLL frequency range can be easily increased at low frequencies. Moreover, the result will improve the channel selection capability of RF front-ends in RF communication systems.

The preceding examples are for illustration only, and do not constitute limitations of the present invention. The teachings of the present invention can be readily applied to other types of devices. The description of the present invention is intended to illustrate, not to limit the scope of patent claims. Many substitutions, modifications, and variations are known in the art. In the claims, means-plus-function recitations are intended to cover the functional structures described herein and not only structural equivalents but also equivalents.

structure.

Claims (18)

1. A communication system comprising: a receiver unit, which receives a signal comprising a selection signal with a carrier frequency; A single phase locked loop generating more than two multiphase clock signals having a frequency different from the carrier frequency, wherein the multiphase clock signals are combined to generate a second frequency higher than the frequency Multiple local oscillator signals of ; and a demodulation mixer that mixes said received selection signal and said more than two multiphase clock signals to output a selection signal having a frequency minus the carrier frequency, wherein each of said local oscillators demodulates one of the I carrier frequency signal and the Q carrier frequency signal. 2. The communication system of claim 1, wherein the frequency is less than the carrier frequency, the RF communication system operates at a carrier frequency greater than 1 GHz, and wherein the RF communication system is formed on a single CMOS chip, and wherein the The phase locked loop includes a clock generator. 3. The communication system of claim 1, wherein the receiver unit is a transceiver further comprising: a modulation mixer for mixing said multi-phase clock signal with transmission data to modulate the transmission data, said multi-phase clock signal serving as a local oscillator signal; and A power amplifier amplifies the modulated transmission data and sends the data to the transceiver for transmission. 4. The communication system of claim 1, further comprising: an RF filter coupled to the receiver unit for filtering the received selection signal; a low noise amplifier coupled to the RF filter for amplifying the filtered select signal with a gain; a low-pass filter, coupled to the demodulation mixer, for filtering a selected signal having a frequency minus the carrier frequency; an analog/digital conversion unit, which converts the selection signal from the demodulation mixer into a digital signal; and A discrete-time signal processing unit receives the digital signal. 5. The communication system of claim 1, wherein: The communication system is part of an RF receiver; the selection signal is an RF signal; The multi-phase clock signal has a frequency of (2*carrier frequency/N), where N is a positive integer greater than 2; The RF communication system is formed on a single CMOS chip. 6. The communication system as claimed in claim 1, wherein the demodulation mixer comprises a first array of mixers and a second array of mixers, each of the first and second arrays of mixers comprising a plurality of Enter the mixer. 7. The communication system of claim 1, wherein the demodulation mixer comprises a first array of mixers and a second array of mixers, each of the first and second arrays of mixers has a plurality of hybrid each of said mixer stages has at least one multiple-input mixer, wherein an output signal from at least one multiple-input mixer of a first stage of said multiple stages is input to a second of said multiple stages stage of at least one multi-input mixer. 8. The communication system of claim 1 , wherein the more than two multiphase clock signals comprise multiple pairs of multiphase clock signals, each pair of the multiple pairs of multiphase clock signals comprising an I carrier frequency signal and a Q carrier frequency signal. 9. The communication system of claim 1, wherein a reference signal is formed by combining the more than two multi-phase clock signals. 10. A single-chip RF communication system comprising: A transceiver for receiving and transmitting RF signals; A single phase-locked loop for generating a plurality of 2N phase clock signals having substantially the same frequency 2*f ₀ /N less than the carrier frequency f ₀ , where N is a positive integer as the number of phases; A demodulation mixing unit for mixing the RF signal from the transceiver with a plurality of 2N phase clock signals from the phase-locked loop to output an RF signal with a frequency minus the carrier frequency, wherein the demodulation The modulation mixer comprises a plurality of two-input mixers; wherein the plurality of 2N phase clock signals are combined to demodulate at least one of the I carrier frequency signal and the Q carrier frequency signal; and An analog/digital conversion unit is used to convert the RF signal from the demodulation mixing unit into a digital signal. 11. The single-chip RF communication system of claim 10 , wherein the demodulation mixing unit comprises a first mixer array comprising half of the two-input mixers; and a second mixer array comprising Comprising the other half of the two-input mixers, each array of mixers inputs a corresponding N-phase clock signal of 2N-phase clock signals together with the RF signal. 12. The single-chip RF communication system of claim 11 , wherein each mixer array comprises multiple stages of mixers, each stage comprising at least one two-input mixer, a first stage of said multiple stages inputting said RF signal and N-phase clock signal. 13. The single-chip RF communication system of claim 12, wherein the multi-stages have a correspondingly reduced number of mixers K1>K2>K3>...>Ki, where K1 is the first stage, K2 is the second level, K3 is the third level, and Ki is the i-th level. 14. The single-chip RF communication system as claimed in claim 10, wherein the demodulation mixing unit comprises a first mixer array and a second mixer array, each of the first and second mixer arrays comprising A plurality of multiple input mixers, wherein a local oscillator signal is formed by combining the plurality of 2N phase clock signals. 15. The single-chip RF communication system of claim 10 , wherein the plurality of 2N phase clock signals is divided into a first plurality of clock signals and a second plurality of clock signals, the first plurality of clock signals being divided into Combined to form an I carrier frequency, the second plurality of clock signals are combined to form a Q carrier frequency. 16. A control method for an RF communication system, comprising: receiving a signal comprising a selection signal having a carrier frequency; generating more than two multiphase clock signals, each multiphase clock signal having a substantially identical frequency different from the carrier frequency, said multiphase clock signals being combined to generate a multiphase clock signal having a second frequency higher than the frequency multiple local oscillator signals; and mixing the received carrier frequency selection signal with said more than two multiphase clock signals to output a demodulated selection signal having a frequency minus the carrier frequency, so as to obtain from said more than two A corresponding local oscillator signal of the multi-phase clock signal combination demodulates one of the first carrier frequency signal and the second carrier frequency signal. 17. The method of claim 16, further comprising: performing RF filtering on the received selection signal; amplifying the filtered selection signal with a gain; and low-pass filtering the demodulated selection signal with frequencies reduced to baseband; performing analog/digital conversion on the low-pass filtered frequency-reduced selection signal to convert it into a digital signal; and Perform discrete-time signal processing on the digital signal. 18. The method of claim 16, further comprising: modulating the transmission data by mixing the multiphase clock signal combined into the local oscillator signal with the transmission data; and The modulated transmission data is power amplified, and the data is sent to the transceiver for transmission.

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