CN1148600C - Liquid crystal display using organic insulating material and manufacturing methods thereof - Google Patents

Abstract

The invention discloses a thin film transistor substrate and a manufacturing method thereof. Wherein, a passivation layer is formed by coating a flowable insulating material on the substrate, and thin film transistors, storage capacitor electrodes and pixel electrodes are formed on the passivation layer. A part of the passivation layer is etched using the pixel electrode as a mask to form a trench on the thin film transistor, and then a black matrix is formed by filling the trench with an organic black photoresist. To increase the storage capacitor, a part of the passivation layer is removed or a metal pattern is formed on the storage capacitor electrode. A flowable insulating material is used as the gate insulating layer to planarize the substrate surface. In the etch stop type thin film transistor, a photosensitive material is used as the etch stop layer to reduce the parasitic capacitance between the gate electrode and the drain electrode.

Description

Thin film transistor substrate and manufacturing method thereof

The present invention relates to a thin film transistor liquid crystal display, more specifically, relates to a thin film transistor liquid crystal display whose black matrix is formed on a thin film transistor substrate and its manufacturing method.

Most liquid crystal displays include a thin film transistor (TFT) substrate and a color filter substrate. The black matrix is generally formed on the color filter substrate to block part of light leakage between pixels. However, the misalignment between the TFT substrate and the color filter substrate makes it difficult to well block light leakage. Therefore, a method of forming a black matrix on a thin film transistor has recently been proposed, which is called a black matrix on TFT (BM on TFT).

Figure 1 shows a conventional BM on TFT TFT substrate.

As shown in FIG. 1, a gate electrode 2 and a storage capacitor electrode 3 are formed on a transparent substrate 1. As shown in FIG. A gate insulating layer 4 is formed on the gate electrode 2 and the storage capacitor electrode 3 . An amorphous silicon layer 5, an etch stop layer 6 and an n ⁺ amorphous silicon layer 7 are sequentially deposited on the gate insulating layer 4 on the gate electrode 2. A source 8 and a drain 9 are formed on the n ⁺ amorphous silicon layer 7 , and the source 8 is connected to a data line (not shown). The gate electrode 2, the gate insulating layer 4, the amorphous silicon layer 5, the n ⁺ amorphous silicon layer 7, the source 8 and the drain 9 form a thin film transistor (TFT). A passivation layer 10 is formed on the TFT and the gate insulating layer 4; a black matrix is formed on the passivation layer 10 on the TFT. A pixel electrode 12 made of ITO (Indium Tin Oxide) is formed on the passivation layer 10 in the pixel region, and is connected to the drain electrode 9 through a contact hole in the passivation layer 10 .

Because the pixel electrode 12 is close to the data line, when the liquid crystal display is in an operating state, a coupling capacitance is generated between the pixel electrode 12 and the data line, and the coupling capacitance distorts the display signal.

Since the black matrix 11 is formed on the TFT, the height difference between the portion near the TFT and the pixel electrode 12 becomes larger, which causes defects in the calibration layer, thereby causing leakage. Although the light leakage can be reduced by increasing the width of the black matrix, the aperture ratio is reduced in this way.

On the other hand, a liquid crystal display comprises two mutually parallel substrates with a certain distance and a liquid crystal layer between them. A spacer is inserted between the substrates to keep the cell (also known as liquid crystal cell) gap constant. The cell gap is the thickness of the liquid crystal layer injected between the two substrates. Generally, spherical spacers having a uniform size are used, and the spacers are placed flat on the pixel electrodes 12 . Due to the height difference between the color filter substrate and the TFT substrate, it is difficult to form a uniform cell gap. Therefore, the thickness of the liquid crystal layer becomes non-uniform, and the display characteristics deteriorate. Also, the spacer on the pixel electrode 12 may cause defects in the alignment layer and may cause scattering of light of the backlight unit, thereby causing low transmittance of the liquid crystal unit and light leakage.

Accordingly, an object of the present invention is to reduce coupling capacitance generated between a data line and a pixel electrode.

Another object of the invention is to reduce the defects of the alignment layer.

Another object of the present invention is to increase the aperture ratio of a liquid crystal display.

Another object of the present invention is to keep the cell gap uniform in a liquid crystal display.

Another object of the present invention is to increase transmittance and reduce light leakage by reducing scattering of backlight.

According to the present invention, these and other objects, features and advantages are provided by a liquid crystal display having a passivation layer made of a flowable insulating material. The flowable insulating material is preferably an organic insulating material, and its dielectric constant is preferably between 2.4-3.7. A passivation layer having a flat surface is formed on the gate line, the data line and each thin film transistor in the TFT substrate to prevent the signal of the pixel electrode formed on the passivation layer and the data line formed under the passivation layer interference between signals.

A part of the passivation layer on the gate line, the data line and each thin film transistor is removed to form a groove, and the black matrix made of organic black photoresist is filled in the groove.

The thickness of the passivation layer is 2.0-4.0 μm (micrometer), which has sufficient insulating properties, and the thickness of the black matrix is 0.5-1.7 μm.

In the pixel area, the storage capacitor electrode is formed on a transparent substrate, thereby forming a storage capacitor with the pixel electrode on the passivation layer. To increase the storage capacity, portions of the passivation layer on the electrodes of the storage capacitor are thinned or removed.

Another way to compensate the storage capacitance is, for example, to make the gate insulating layer between the storage capacitor electrode and the pixel electrode thinner. In another example, a contact hole exposing the storage capacitor electrode is formed in the gate insulating layer, and a metal pattern is formed on the gate insulating layer and connected to the storage capacitor electrode through the contact hole. In another embodiment, a metal pattern connected to the pixel electrode may be formed on the portion of the gate insulating layer on the storage capacitor electrode.

A flowable insulating layer is also used as the gate insulating layer so that the gate insulating layer has a flat surface, which reduces the parasitic capacitance between the gate and the drain. A silicon nitride layer may be formed between the flowable gate insulating layer and the semiconductor layer made of amorphous silicon to prevent deterioration of interface characteristics of the amorphous silicon layer. An organic insulating material is preferably used, and the thickness of the organic gate insulating layer is preferably 2,500-5,500 angstroms. The thickness of the silicon nitride layer is preferably 500-800 angstroms.

For an etch-stop type TFT substrate, a photo definable material is used as an etch-stop layer to reduce the parasitic capacitance between the gate and the drain and simplify the process. Organic materials are preferably used, and the etch stop layer preferably has a thickness of 3,000-5,000 angstroms.

In order to maintain the cell gap between the TFT substrate and the color filter substrate, spacers made of photosensitive organic materials are formed on the color filter substrate. Spacers are formed between the color filters, and their positions correspond to the thin film transistors on the TFT substrate.

To manufacture the TFT substrate of the present invention, a flowable insulating layer for forming a gate insulating layer is coated on a substrate having a gate electrode. A silicon nitride layer is deposited on the flowable insulating layer. A semiconductor layer is formed on the silicon nitride layer, and the silicon nitride layer is etched away except for the portion under the semiconductor layer.

In the case where the etch stop layer is made of a photosensitive material, a photosensitive organic layer is coated on the semiconductor layer and patterned to form the etch stop layer. A method of patterning an etch stop layer comprising the steps of: exposing an organic layer from the backside of a substrate; exposing the organic layer from the front side of the substrate using an etch stop mask; developing the organic layer; and thermally treating the organic layer .

Next, an ohmic contact layer and a data pattern are sequentially formed. A flowable insulating material is applied for the passivation layer, the part of the passivation layer lying on the electrodes of the storage capacitor being removed.

Then, an ITO (Indium Tin Oxide) layer is deposited and patterned to form a pixel electrode in the pixel area, and the passivation layer is etched to a depth using the pixel electrode as a mask, and the organic black photoresist is filled flatly In the etching area, a black matrix is formed.

Preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. In the attached picture:

Fig. 1 is a sectional view of an existing BM on TFT substrate;

Fig. 2 has shown the plan view of a TFT substrate of the first embodiment of the present invention;

Fig. 3 shows the sectional view of the TFT substrate shown in Fig. 2 along the line III-III';

4-11 are cross-sectional views of the TFT substrates of the second to ninth embodiments, respectively;

Figure 12 shows a cross-sectional view of a color filter substrate according to an embodiment of the present invention;

Figure 13 shows a cross-sectional view of a liquid crystal display unit according to an embodiment of the present invention;

Figure 14A shows a plan view of the color filter substrate shown in Figure 12 to show the location of the spacers;

Figure 14B is a cross-sectional view of the color filter substrate shown in Figure 14A along line XIV-XIV';

15A, 16A and 17A show a plan view of the intermediate structure of the first embodiment of the present invention, in order to illustrate a method of manufacturing a TFT substrate;

Figure 15B, 16B and 17B show the cross-sectional view of the TFT substrate along the line XV-XV' of Figure 15A, the line XVI-XVI' of Figure 16A and the line XVII-XVII' of Figure 17A;

18 and 19 show cross-sectional views of an intermediate structure of a sixth embodiment of the present invention, for explaining a method of manufacturing a TFT substrate.

20 and 21 show cross-sectional views of an intermediate structure of an eighth embodiment of the present invention, for explaining a method of manufacturing a TFT substrate.

The invention will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the present invention can be implemented in different forms and is not limited to the examples presented here. Rather, these embodiments are provided to fully disclose the present invention and enable those skilled in the art to more fully understand the scope of the present invention. In the drawings, the thickness of layers and regions are exaggerated for clarity.

According to an embodiment of the present invention, a liquid crystal display includes a liquid crystal cell composed of a TFT substrate and a color filter substrate; liquid crystal material injected into the cell; driving integrated circuits (ICs) and auxiliary devices.

FIG. 2 shows a plan view of the TFT substrate of the first embodiment of the present invention, and FIG. 3 shows a cross-sectional view of the TFT substrate shown in FIG. 2 along the line III-III'.

As shown in FIGS. 2 and 3 , a gate line 21 for transmitting a scan signal from the outside, a gate electrode 20 as a branch of the gate line 21 and a storage capacitor electrode 30 parallel to the gate line 21 are formed on a transparent insulating substrate 10. , such as on glass. A gate insulating layer 40 is formed thereon.

Data lines 81 perpendicular to the gate lines 21 and transmitting display signals from the outside are formed on portions of the gate insulating layer 40 . An amorphous silicon (a-Si) layer 50 is formed on the gate insulating layer 40 on the gate electrode 20 . An etch stopper layer 60 and ohmic contact layers 71 and 72 made of heavily doped amorphous silicon with n-type ions (n ⁺ a-Si) are sequentially formed on the a-Si layer 50 . A source electrode 80 and a drain electrode 90 are formed on the ohmic contact layers 71 and 72 , respectively, and connect the source electrode 80 to the data line 81 .

Here, the gate electrode 20, the source electrode 80, the drain electrode 90, the gate insulating layer 40, the ohmic contact layers 71 and 72, and the a-Si layer 50 form a TFT, and the channel of the TFT is generated between the source electrode 80 and the drain electrode 90. a-Si layer 50 part. When a scan signal is applied to the gate electrode 20 through the gate line 21 , the TFT is turned on, and the display signal reaching the source electrode 80 through the data line 81 flows into the drain electrode 90 through the channel in the a-Si layer 50 .

A passivation layer 100 with a flat surface is formed on the TFT and the gate insulating layer 40, the passivation layer 100 is made of a flowable organic insulating material, it has a low dielectric constant of 2.4-3.7, and its thickness is 2.0- 4.0 μm.

An organic insulating layer 10 times thicker than a silicon nitride layer has almost the same transmittance compared to a silicon nitride layer generally used as a passivation layer. For example, a 2.5 micron organic insulating layer has the same transmittance as a 0.2 micron silicon nitride layer with respect to visible light.

The flowable insulating material may be, for example, photo-BCB, BCB, or PFCB produced by Dow Chemical Co.; polypropylene photoresist produced by JSR Co.; and polyimide and SOG (Spin on glass). Since these materials are flowable, the passivation layer can be given a flat surface by using the spin-coating method.

The passivation layer 100 has a contact hole 130 exposing the drain electrode 90 , and a portion of the passivation layer 100 on the storage capacitor electrode 30 is thinned to form a trench or removed to expose the gate insulating layer 40 . In a pixel region defined by the gate line 21 and the data line 81 , a pixel electrode 140 made of ITO (Indium Tin Oxide) is formed on the passivation layer 100 . The pixel electrode 140 is connected to the drain electrode 90 through the contact hole 130, and receives a display signal from the drain electrode 90 to drive the liquid crystal molecules.

The part of the passivation layer not covered by the pixel electrode 140 is located on the TFT, the gate line 21 and the data line 81, and is etched to a certain depth to form a groove. A black matrix 110 made of organic black photoresist is filled in the trench and has a flat surface. The thickness of the black matrix 110 is 0.5-1.7 micrometers, and the optical density of the black matrix 110 is equal to or greater than 2.5 so as to have sufficient light shielding properties. The thickness of the black base 110 can vary with available materials, in particular its thickness depends on the optical density of the material. If a material with high optical density is used, the thickness of the black substrate can be reduced. Since the pixel electrode 140 is in contact with the passivation layer 100, it is preferable that the black substrate 110 has relatively high resistance, for example, its surface resistance is preferably equal to or greater than 10 ¹⁰ Ω/square.

A carbon-based organic material or a pigment-based organic material can be used as the black base 110, and since the optical density of the carbon-based organic material is higher than that of the pigment-based material, it is preferable to use the carbon-based organic material. However, graphite-type organic materials with high optical density are less suitable for black matrix due to its low surface resistance.

The storage capacitor electrode 30 and the pixel electrode 140 form a storage capacitor. Due to the thick passivation layer 100 between the electrodes 30 and 140, the storage capacitance is not large enough. In order to compensate for the storage capacitance, the portion of the passivation layer between the electrodes 30 and 140 can be removed or thinned.

The TFT substrate can also have some other modified structures to compensate for storage capacitance. 4-6 show cross-sectional views of the TFT substrates of the second to fourth embodiments of the present invention, and these embodiments compensate the storage capacitance through improvement.

According to the second embodiment of the present invention, as shown in FIG. 4 , the part of the passivation layer 100 on the storage capacitor electrode 30 is removed, and the part of the gate insulating layer 40 on the storage capacitor electrode 30 is thinner than other parts. To keep the thickness of the portion of the gate insulating layer 40 on the storage capacitor electrode 30 uniform, the gate insulating layer 40 may include two layers with different etch rates, and the upper layer portion on the storage capacitor electrode 30 may be removed.

According to the third embodiment of the present invention, as shown in FIG. 5 , a metal pattern 31 is formed on a portion of the gate insulating layer 40 located on the storage capacitor electrode 30 . The metal pattern 31 is connected to the storage capacitor electrode 30 through the contact hole 32 in the gate insulating layer 40 and is covered by the passivation layer 100 .

According to the fourth embodiment of the present invention, as shown in FIG. 6 , a metal pattern 31 is formed on a portion of the gate insulating layer 40 located on the storage capacitor electrode 30 . A portion of the passivation layer 100 on the metal pattern 31 is removed to form a contact hole 120 through which the pixel electrode 140 covers the metal pattern 31 .

As mentioned above, since the organic passivation layer 100 with a low dielectric constant is formed between the pixel electrode 140 and the data line 81, the coupling capacitance between the pixel electrode 140 and the data line 81 is reduced, so the pixel electrode 140 may cover the data. line 81 and gate line 21. Accordingly, by reducing the area occupied by the black matrix and increasing the area occupied by the pixel electrode, the aperture ratio of the TFT can be increased.

In addition, since the black matrix 110 is formed on the TFT substrate, light-induced leakage current caused by backlight reflection of the black matrix is reduced. Furthermore, since the surface of the TFT substrate is flat, the problem of alignment layer defects caused by pattern height differences is prevented or reduced.

FIG. 7 shows a cross-sectional view of an etch-back TFT substrate according to a fifth embodiment of the present invention, and the planar layout of the TFT is substantially the same as that in FIG. 2 . The structure of the TFT substrate of this embodiment is basically the same as that of the first embodiment shown in FIG. However, the TFT of this embodiment has no etch stopper.

Therefore, the channel region of the a-Si layer 50 of the TFT is directly in contact with the organic insulating layer. However, it turned out that the characteristics of the TFT were not affected.

In addition to the structure of TFTs, similar to the second to fourth embodiments of the present invention, the TFT substrate may have some other modified structures to compensate for storage capacitance.

A flowable insulating layer is also used as the gate insulating layer so that the gate insulating layer has a flat surface. According to a sixth embodiment of the present invention, a gate insulating layer is a double-layer structure including a flowable insulating layer and a silicon nitride layer. FIG. 8 shows a cross-sectional view of a TFT substrate according to a sixth embodiment of the present invention, and the layout of the TFT is basically the same as that in FIG. 2 .

A flowable organic insulating layer 41 having a thickness of 2,500-5,500 angstroms is formed on the substrate having a gate electrode and a storage capacitor electrode. A silicon nitride layer 42 having a thickness of 500-800 angstroms is formed between the flowable organic insulating layer 41 and the amorphous silicon layer 50 .

When only a flowable organic insulating layer is used as the gate insulating layer, the gate insulating layer has a flat surface. However, the characteristics of the amorphous silicon layer formed thereon deteriorate. Therefore, by interposing the silicon nitride layer 42 between the flowable organic insulating layer 41 and the a-Si layer 50, it is possible to make the thickness of the a-Si layer less than 1,000 angstroms, thereby reducing light-induced leakage current. However, the silicon nitride layer 42 may not be formed.

As shown in FIG. 8 , silicon nitride (SiN _x ) layer 42 is formed only under a-Si layer 50 . If the _SiNx layer is formed on the entire organic insulating layer, the flowable organic insulating layer, the silicon nitride layer and the passivation layer are all formed in the gate pad region. Since the etching rate of the organic insulating layer is different from that of SiN _X , it is not easy to form a contact hole in the gate wiring area. Therefore, the _SiNx layer is previously removed except for the portion located under the a-Si layer to simplify the process of forming the contact hole.

Structures not described above are similar to the TFT substrate of the fifth embodiment of the present invention.

In addition to the structure of each thin film transistor, similar to the second to fourth embodiments of the present invention, the TFT substrate may have some other improved structures to compensate for the storage capacitance,

The seventh embodiment of the present invention shown in FIG. 9 proposes a TFT substrate, which has a metal layer formed on a part of the organic insulating layer 41 on the storage capacitor electrode 30, as in the fourth embodiment of the present invention. 31. Other structures are similar to those of the TFT shown in FIG. 8 .

According to an eighth embodiment of the present invention, the etch stop layer is made of an organic material.

FIG. 8 shows a cross-sectional view of an etch-stop type TFT substrate according to an eighth embodiment of the present invention. According to the eighth embodiment of the present invention, like the sixth embodiment of the present invention, the gate insulating layer includes an organic insulating layer and a _SiNx layer.

An etch stopper layer 61 made of a photosensitive organic material is formed between the a-Si layer 50 and the ohmic contact layers 71 and 72 . Other structures are similar to the TFT substrate shown in FIG. 9 . Since the dielectric constant of the organic material is relatively low, the parasitic capacitance between the gate electrode and the drain that causes the inversion is reduced. In addition, since the a-Si layer 50 and the _SiNx layer 42 are etched using the etch stop layer 61 as a mask, the manufacturing process is relatively simple.

Structures not described above are similar to the TFT substrate of the sixth embodiment of the present invention.

In addition to the structure of each thin film transistor, similar to the second to fourth embodiments of the present invention, the TFT substrate may have some other modified structures to compensate for storage capacitance.

The ninth embodiment of the present invention shown in FIG. 11 proposes a TFT substrate that has a metal layer 31 formed on a portion of an organic insulating layer 41 on a storage capacitor electrode 30 as in the fourth embodiment of the present invention. . Other structures are similar to the TFT shown in FIG. 10 .

Fig. 12 shows a cross-sectional view of a color filter substrate according to an embodiment of the present invention. As shown in FIG. 12, a color filter layer 160 is formed on a transparent insulating substrate 150, a passivation layer 170 and a common electrode 180 are sequentially formed thereon.

FIG. 13 shows a cross-sectional view of a liquid crystal display unit according to an embodiment of the present invention. The TFT substrate and the color filter substrate are arranged such that the color filter 160 corresponds to the pixel electrode 140 . In order to maintain the cell gap between the TFT substrate and the color filter substrate, a cylindrical spacer 190 is formed on the color filter substrate. The spacer 190 is made of a photosensitive organic material, and is disposed at a position corresponding to the TFT on the TFT substrate. Since the planarization layers 100 and 110 are sufficiently thick on the channel of the TFT, the spacer 190 does not affect the characteristics of the TFT.

14A shows a plan layout of the color filter substrate to show the position of spacers, and FIG. 14B is a cross-sectional view of the color filter substrate shown in FIG. 14A along line XIV-XIV'. In Figs. 14A and 14B, R, G and B denote red, green and blue color filter layers, respectively. As shown in FIG. 14A , the color filter layer 160 has a concave portion, and the spacer 190 is formed in the concave portion.

Since the spacer 190 is made of a photosensitive organic material through a photolithography process, it is easy to place the spacer 190 at a desired position and make it have a uniform thickness. For example, as shown in FIGS. 14A and 14B, a spacer 190 can be formed at an exact position corresponding to each thin film transistor on a TFT substrate, and it has a uniform height so that a uniform grain gap can be obtained. In addition, since the TFTs are covered by the black matrix and they do not affect the aperture ratio, the spacer 190 does not reduce the aperture ratio. Moreover, since the spacers 190 are not placed on the color filter layers R, G, and B, the color filter layers may have different thicknesses in order to obtain different cell gaps to optimize color adjustment and transmittance.

Since the spacer 190 has a certain height, a shadow area may be generated, causing quality degradation during the rubbing process. However, since the width of the spacer 190 can be made sufficiently small, the shaded area is narrower than each thin film transistor and can be shielded by the black matrix 110 .

Next, a method of manufacturing a liquid crystal display in an embodiment of the present invention will be described with reference to FIGS. 15A-17B.

15A, 16A and 17A are planar views showing intermediate structures for explaining the manufacturing method of the TFT substrate of the first embodiment shown in FIGS. 2 and 3. FIGS. 15B, 16B and 17B show cross-sectional views of the TFT substrate along the line XV-XV' of FIG. 15A, the line XVI-XVI' of FIG. 16A and the line XVII-XVII' of 17A.

As shown in FIGS. 15A and 15B, a metal pattern with a thickness of about 3,000 Å (angstroms) is deposited and patterned to form a gate electrode 20 on a transparent insulating substrate 10, a gate line 21 and a storage capacitor electrode 30. . A gate insulating layer 40, an a-Si layer 50 and a silicon nitride layer 60 are sequentially deposited thereon using CVD (Chemical Vapor Deposition). The gate insulating layer 40 has a thickness of 3,000-6,000 angstroms, the a-Si layer 50 has a thickness of 500-1,000 angstroms, and the silicon nitride layer 60 serving as an etching stopper has a thickness of 1,000-2,000 angstroms.

Next, a layer of photoresist is coated on the silicon nitride layer 60 and exposed from the back side of the substrate 10 to form a photoresist pattern. Using this photoresist pattern as a mask, the silicon nitride layer 60 is etched to form an etch stop layer 60 .

Next, heavily doped n ⁺ a-Si layers 71 and 72 are deposited and etched on the a-Si layer 50 . Next, a metal pattern with a thickness of about 3,000 angstroms is deposited and patterned to form a source electrode 80, a drain electrode 90 and a data line 81, and the n ⁺ a-Si layers 71 and 72 are formed using the source electrode 80 and the drain electrode 90 And the data line 81 is used as a mask for etching to form ohmic contact layers 71 and 72 .

Next, as shown in FIGS. 16A and 16B, a passivation layer 100 made of an organic insulating material having a low dielectric constant and high transmittance is coated by spin coating so that the passivation layer 100 has a flat surface. The dielectric constant of the passivation layer is preferably 2.4-3.7, and its thickness is preferably 2.0-4.0 µm. By etching the passivation layer 100 , a contact hole 130 exposing the drain electrode 90 and a trench 120 exposing the storage capacitor electrode 30 are formed. The contact hole 130 and the trench 120 are formed by a dry etching method using O ₂ , SF ₆ and CF ₄ . In case the organic insulating material is a photosensitive material, only the steps of exposing with a mask and developing the passivation layer 100 may be performed.

Next, as shown in FIGS. 17A and 17B , an ITO layer is deposited and patterned to form a pixel electrode 140 in the pixel region defined by the gate line 21 and the data line 81 .

Finally, as shown in FIGS. 2 and 3 , the passivation layer 100 is etched to a certain depth using the pixel electrode 140 as a mask, and the organic black photoresist is filled in the trenches in the passivation layer 100 to form a flat surface. Surface black matrix. The etching thickness is preferably 0.5-1.7 μm, and the surface resistance of the organic black photoresist is equal to or greater than 10 ¹⁰ Ω/square. The optical density of the black matrix 110 is equal to or greater than 2.5.

A method of manufacturing a liquid crystal display having various storage capacitors will be described below with reference to FIGS. 4-6.

As shown in FIG. 4 , in order to manufacture the TFT substrate of the second embodiment of the present invention, after etching the passivation layer 100 to form a trench 120 , dry etching is performed on the exposed portion of the gate insulating layer 40 . Accordingly, a portion of the gate insulating layer 40 on the storage capacitor electrode 30 becomes thinner, so that the storage capacity increases. At this time, in order to etch the gate insulating layer 40 to a uniform depth, the gate insulating layer may include two layers with greater etching selectivity, and only the upper layer may be removed.

As shown in FIG. 5, in order to manufacture the TFT substrate of the third embodiment of the present invention, before depositing a metal layer for forming the data lines, source and drain electrodes, the part of the gate insulating layer 40 located on the storage capacitor electrode 30 is etch to form a contact hole 32 . Next, a metal pattern 31 is formed over a portion of the gate insulating layer 40 on the storage capacitor electrode 30 simultaneously with the source electrode 80 and the drain electrode 90 . The metal pattern 31 is connected to the storage capacitor electrode 30 through the contact hole 32 .

As shown in FIG. 6, in order to manufacture the TFT substrate of the fourth embodiment of the present invention, a metal pattern 31 is formed on a portion of the gate insulating layer 40 located on the storage capacitor electrode 30 simultaneously with the source electrode 80 and the drain electrode 90.

Next, referring to FIGS. 18 and 19, a method of manufacturing the TFT substrate of the sixth embodiment shown in FIG. 8 is shown.

As shown in Figure 18, an organic insulating layer 41 with a thickness of 2,500-5,500 angstroms is spin-coated on the transparent insulating substrate 10 with gate electrodes 20, gate lines (not shown) and storage capacitor electrodes 30, and a thickness of A 500-800 Angstrom layer of _SiNx is deposited thereon using CVD. The organic insulating layer 41 and the _SiNx layer 42 form a gate insulating layer 40 . An a-Si layer 50 and an n ⁺ a-Si layer 70 are sequentially deposited on the _SiNx layer 42 . The thickness of a-Si layer 50 is less than 1,000 Angstroms.

Next, a photoresist layer is formed and patterned. The n ⁺ a-Si layer 70, the a-Si layer 50 and the _SiNx layer 42 are sequentially etched using the photoresist pattern as a mask.

Next, as shown in Figure 19, a metal is deposited and patterned to form a source 80, a drain 90 and a data line (not shown), using the source 80 and the drain 90 as a mask to etch n ⁺ a- The Si layer 70 forms an ohmic contact layer 71 and 72 .

The rest of the process is similar to the manufacturing method of the TFT substrate of the first embodiment.

To manufacture the TFT substrate of the seventh embodiment of the present invention, as shown in FIG. 9, a metal pattern 31 is formed on the portion of the gate insulating layer 40 located on the storage capacitor electrode 30, and a source electrode 80 is formed at the same time. The metal pattern 31 is connected to the pixel electrode 140 .

20 and 21 show a method of manufacturing the TFT substrate of the eighth embodiment shown in FIG. 10.

As shown in Figure 20, an organic insulating layer 41 with a thickness of 2,500-5,500 angstroms is spin-coated on a transparent insulating substrate 10 having a gate electrode 20, a gate line (not shown) and a storage capacitor electrode 30, and the thickness is obtained by CVD. A _SiNx layer 42 of 500-800 Angstroms is deposited thereon. An a-Si layer 50 with a thickness of less than 1,000 angstroms is deposited on the _SiNx layer 42, and a layer of positive photosensitive organic material with a thickness of 3,000-5,000 angstroms is coated thereon. Photo BCB, photosensitive polypropylene can be used as organic material. Next, from the back of the substrate 10, the substrate 10 is exposed from the back of the substrate 10 with 200-600 mJ (millijoules) of energy, and then exposed from the front of the substrate 10 with 50-100 mJ of energy using a mask. , the mask exposes a portion of the organic insulating layer that becomes an etch stop layer. Next, the organic insulating layer is developed to form an etching stopper layer 61, and annealed in a N ₂ environment at a temperature of 200-230°C.

Using the etch stop layer 61 as a mask, the a-Si layer 50 and the _SiNx layer 42 are etched. Then deposit an n ⁺ a-Si layer and a metal layer, and pattern to form a source 80, a drain 90, and a data line (not shown). n ⁺ a-Si layers 71 and 72 are therebeneath them.

Other steps of the manufacturing method are similar to the manufacturing method of the TFT substrate of the first embodiment.

In the manufacturing method of the TFT substrate of the ninth embodiment shown in FIG. 11, the method of forming the TFT is similar to the manufacturing method of the TFT substrate of the eighth embodiment. The rest of the process is similar to the TFT substrate manufacturing method of the fourth embodiment.

Now, referring to Fig. 12, a method of manufacturing a color filter substrate according to an embodiment of the present invention will be described below. As shown in FIG. 12, a color resist layer is formed on a transparent substrate 150, and a photolithography process is used on the color resist layer to form a color filter layer 160. Referring to FIG. The passivation layer 170 is formed on the color filter layer 160, and an ITO common electrode 180 is formed thereon.

Next, as shown in FIG. 13 , an organic insulating layer is formed on the common electrode 180 and patterned to form a cylindrical spacer 190 . Spacers 190 are disposed on thin film transistors (TFTs) on the TFT substrate.

Finally, an empty liquid crystal display unit is made by assembling the TFT substrate and the color filter substrate, and the liquid crystal display material is filled in the unit, as shown in Figure 13, and the driving integrated circuit is added to complete the liquid crystal display.

According to the present invention, since the black matrix is formed using the pixel electrode as an etching mask, the aperture ratio is increased. In addition, since the passivation layer and/or the gate insulating layer are made of an organic material having a flat surface, the level difference between patterns can be reduced.

In the case where the etch stop layer is made of an organic insulating layer with a low dielectric constant, the parasitic capacitance between the gate electrode and the drain electrode is reduced.

On the other hand, since the spacer is formed of a photosensitive organic material, the position of the spacer can be easily controlled. Correspondingly, by placing the spacer in a suitable position, it is easy to obtain a uniform cell gap and avoid the decrease of the transmittance.

In the drawings and detailed description, there have been shown typically preferred embodiments of the invention and although specific terminology has been used, they are used for purposes of description only and are not limiting. The scope of the invention will be defined in the following claims put forward in the request.

Claims (45)

1. thin-film transistor substrate that is used for LCD comprises:

A transparent insulation substrate;

One on-chip thin film transistor (TFT), it comprises a gate electrode, a drain electrode, a source electrode, a gate insulation layer and a semiconductor layer;

A passivation layer relative with substrate on thin film transistor (TFT), this passivation layer have a flowable insulating material, and it has the groove that closes on thin film transistor (TFT);

Be filled in the black matrix in the groove; With

Be connected to the pixel electrode of drain electrode.

2. thin-film transistor substrate as claimed in claim 1, wherein, passivation layer has first contact hole that exposes drain electrode, and pixel electrode is being connected in the drain electrode on the passivation layer and by first contact hole.

3. thin-film transistor substrate as claimed in claim 2, also comprise an on-chip storage capacitor electrode, wherein, this gate insulation layer extend on the storage capacitor electrode with the substrate opposite side, and wherein pixel electrode extend on the gate insulation layer with the storage capacitor electrode opposite side.

4. thin-film transistor substrate as claimed in claim 3, wherein, passivation layer is made by organic insulator.

5. thin-film transistor substrate as claimed in claim 4, wherein, the specific inductive capacity of passivation layer is 2.4-3.7.

6. thin-film transistor substrate as claimed in claim 3, wherein, black matrix is made by organic black photoresist.

7. thin-film transistor substrate as claimed in claim 6, wherein, the surface resistance of organic black photoresist is equal to or greater than 10 ¹⁰Ohm/side.

8. thin-film transistor substrate as claimed in claim 3, wherein, passivation layer extends on the gate insulation layer on the storage capacitor electrode.

9. thin-film transistor substrate as claimed in claim 8 also comprises the metal pattern on the gate insulation layer that is positioned on the storage capacitor electrode, and

Wherein, gate insulation layer has second contact hole that exposes storage capacitor electrode, and metal pattern is connected to storage capacitor electrode by second contact hole.

10. thin-film transistor substrate as claimed in claim 8, wherein, the passivation layer part that is positioned on the storage capacitor electrode is thinner than the other parts of passivation layer.

11. thin-film transistor substrate as claimed in claim 3, wherein, the gate insulation layer part on the storage capacitor electrode is thinner than the other parts of gate insulation layer.

12. thin-film transistor substrate as claimed in claim 11, wherein, gate insulation layer comprises different two-layer of etching rate, and the part of the gate insulation layer on storage capacitor electrode only has one deck.

13. thin-film transistor substrate as claimed in claim 3 also comprises one at the metal pattern on the storage capacitor electrode and be connected on the pixel electrode.

14. a thin-film transistor substrate that is used for LCD comprises:

A transparent insulation substrate;

An on-chip thin film transistor (TFT), this thin film transistor (TFT) comprise a grid, a drain electrode, a source electrode, a gate insulation layer and a semiconductor layer;

A passivation layer relative with substrate on thin film transistor (TFT) has the groove that faces mutually with thin film transistor (TFT) on this passivation layer; And

Black matrix in groove.

15. thin-film transistor substrate according to claim 14 also comprises a pixel electrode that is connected to drain electrode, wherein, passivation layer comprises first contact hole that exposes drain electrode, and pixel electrode and is connected to drain electrode by first contact hole on passivation layer.

16. thin-film transistor substrate according to claim 15, also comprise an on-chip storage capacitor electrode, wherein, gate insulation layer extends on the storage capacitor electrode and is relative with substrate, and wherein, pixel electrode extends on the gate insulation layer, and is relative with the storage capacitor electrode that is covered by gate insulation layer, and is positioned under the pixel electrode.

17. thin-film transistor substrate according to claim 16, wherein, black matrix comprises an organic black photoresist.

18. thin-film transistor substrate according to claim 17, wherein, the surface resistance of organic black photoresist is equal to or greater than 10 ¹⁰Ohm/side.

19. a thin-film transistor substrate that is used for LCD comprises:

A transparent insulation substrate;

An on-chip grid;

Gate insulation layer on grid, this gate insulation layer comprises organic insulation;

Semiconductor layer on gate insulation layer; And

A source electrode and a drain electrode on the semiconductor, they separate each other.

20. thin-film transistor substrate according to claim 19, wherein, semiconductor layer comprises unsetting silicon.

21. thin-film transistor substrate according to claim 19, it also is included in the silicon nitride layer between gate insulation layer and the semiconductor layer.

22. a manufacture method that is used for the thin-film transistor substrate of LCD, it may further comprise the steps:

Form a gate pattern, it comprises the on-chip gate line of transparent insulation and a grid;

Form one at on-chip gate insulation layer, be included in the gate insulation layer on gate line and the grid;

Be formed on the semi-conductor layer on the gate insulation layer;

Form a data pattern, a source electrode and a drain electrode, this data pattern comprises one and gate line data line crossing, and this source electrode is a branch of data line;

Use a flowable insulating material to be coated with one deck passivation layer to form flat surfaces;

Form first contact hole that exposes drain electrode by the etching passivation layer;

On by the passivation layer in gate line and the determined zone of data line, form a pixel electrode;

Use pixel electrode to make the mask etching passivation layer to form a groove;

In groove, form a black matrix.

23. method as claimed in claim 22, wherein, passivation layer is to be made by organic insulator.

24. method as claimed in claim 23, wherein, the specific inductive capacity of passivation layer is 2.4-3.7.

25. method as claimed in claim 22, wherein, black matrix is to be made by organic black photoresist.

26. method as claimed in claim 25, wherein, the surface resistance of organic black photoresist is greater than 10 ¹⁰Ohm/side.

27. method as claimed in claim 22 also comprises a step that forms a storage capacitor electrode on the substrate under the pixel electrode.

28. method as claimed in claim 27 also comprises the passivation layer step partly on the etching storage capacitor electrode.

29. method as claimed in claim 28 also comprises the step that is positioned at the part on the storage capacitor electrode in the etching gate insulation layer.

30. method as claimed in claim 28, wherein, gate insulation layer has double-decker, comprises a lower floor and a upper strata, only has the top section on the storage capacitor electrode to be etched away.

31. method as claimed in claim 27 also comprises the following steps:

The part that is positioned in gate insulation layer on the storage capacitor electrode forms a metal pattern;

In passivation layer, form second contact hole to expose metal pattern;

Wherein pixel electrode is connected to metal pattern by second contact hole.

32. method as claimed in claim 27 also comprises the following steps:

In gate insulation layer, form second contact hole to expose storage capacitor electrode;

Form a metal pattern, it is connected on the storage capacitor electrode by second contact hole on the gate insulation layer.

33. method as claimed in claim 22, wherein, gate insulation layer is made by the organic insulation with flat surfaces.

34. method as claimed in claim 33 also is included in the step that forms a silicon nitride layer on the gate insulation layer.

35. method as claimed in claim 34, wherein, silicon nitride layer only is positioned under the semiconductor layer.

36. method as claimed in claim 35, wherein, semiconductor layer is made by unsetting silicon.

37. method as claimed in claim 22 also comprises the step of using the sensitization organic material to form an etching restraining barrier on semiconductor layer.

38. method as claimed in claim 37, wherein, the step that forms etching barrier layer comprises the following steps:

Be coated with one deck photosensitive material;

The mask that use has the etching barrier layer pattern exposes to photosensitive material layer from the substrate front portion;

Photosensitive material layer is developed to form an etching restraining barrier.

39. method as claimed in claim 38 also is included in before the anterior step of exposing of substrate from the step of the backside exposure of substrate.

40. method as claimed in claim 38 also comprises development step annealing steps afterwards.

41. method as claimed in claim 40 also comprises the step of using etching barrier layer to make the mask etching semiconductor layer.

42. a manufacture method that is used for the thin-film transistor substrate of LCD comprises the following steps:

Form a gate pattern, it comprises a gate line and a gate electrode, and gate electrode is a branch of the on-chip gate line of transparent insulation;

Use flowable insulating material to form a gate insulator;

On gate insulation layer, form a silicon nitride layer;

On silicon nitride layer, form semi-conductor layer;

Form a data pattern, it comprises one with the gate line data line crossing, as source electrode and a drain electrode of a branch of data line.

43. method as claimed in claim 42, wherein, gate insulation layer is to be made by organic insulation.

44. method as claimed in claim 43, wherein, silicon nitride layer only is positioned under the semiconductor layer.

45. method as claimed in claim 44, wherein, semiconductor layer comprises unsetting silicon.

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