CN114864815A - A kind of resistive memory with low SET and RESET instantaneous power and preparation method thereof - Google Patents

Abstract

The invention relates to a resistive random access memory with low SET and RESET instantaneous power and a preparation method thereof ₂ ) An adhesion layer (Ti), a bottom electrode layer (Pt), a current limiting layer (SiO) ₂ ) A resistance change layer (TaON) and an upper electrode layer (TiN). The invention provides a low SET and RESET instantaneous power resistive random access memory with a TiN/TaON/SiO2/Pt structure. SiO prepared by PECVD ₂ As a current limiting layer, the resistance change layer is prevented from forming thick conductive wires, and the generation of large current is prevented. SiO prepared by PECVD ₂ Contains more defects, and electrons can be injected into SiO ₂ In thin films, SiO ₂ Defects in the film act as traps to trap electrons, and as the applied electric field is gradually increased, the transitions of the electrons trapped by the traps participate in conduction.

Description

A kind of resistive memory with low SET and RESET instantaneous power and preparation method thereof

technical field

The invention belongs to the field of semiconductor microelectronic devices, and relates to a resistive memory with low SET and RESET instantaneous power and a preparation method thereof, and specifically proposes a resistive memory with a structure of TiN/TaON/SiO2/Pt and relates to the same. Preparation.

Background technique

In the 1960s, Simmons et al. discovered a dramatic change in resistance in SiOx materials. In 2000, Liu et al. reported that a device prepared from a thin metal material under pulsed stimulation exhibited excellent resistance transition characteristics. Subsequently, more and more people began to study resistive memory, and there are many such as Samsung. , IBM, Toshiba large semiconductor electronic design company. Resistive RAM utilizes the mutual conversion between the high resistance state (HRS) and the low resistance state (LRS) of the thin film resistance under the condition of an applied voltage of the thin film material to realize data storage. Due to the external representation of different high and low configurations to represent logic "1" and logic "0", thus realizing data storage, the high resistance state (HRS) and low configuration (LRS) of the resistive memory can be used for a long time after the power is cut off. Keeping this is one of the important properties of resistive memory that can be a non-volatile memory.

The process of changing the resistive memory from a high resistance state (HRS) to a low resistance state (LRS) is called a SET process, or a set process. The transition from a low configuration to a high impedance state is called the RESET process, or it can also be called a reset process. After the preparation is completed, it shows a relatively high resistance. At this time, an initial voltage is required to keep it in the LRS state. This process is called the Forming process. The structure of a common resistive memory is a "sandwich" structure (MIM) - that is, the upper and lower electrodes are metal, and the intermediate layer also becomes a resistive layer and an insulator.

Resistive memory has the advantages of small cell size, fast read and write speed, low programming voltage, low power consumption, compatibility with CMOS fabrication process, and simple device structure. It is one of the most promising new memories in the future.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, a resistive memory with low SET and RESET instantaneous power and a preparation method thereof are provided.

The scheme of the present invention is:

A resistive memory with low SET and RESET instantaneous power, comprising a substrate layer (Si/SiO ₂ ), an adhesion layer (Ti), a bottom electrode layer (Pt), a current limiting layer (SiO ₂ ), a resistive layer and a Alteration layer (TaON) and upper electrode layer (TiN).

底电极层(Pt)厚度为

限流层厚度为

阻变层(TaON)厚度为

上电极层(TiN)厚度为

Preferably, the thickness of the adhesive layer is

Bottom electrode layer (Pt) thickness is

The thickness of the current limiting layer is

The thickness of the resistive layer (TaON) is

The thickness of the upper electrode layer (TiN) is

Preferably, the material of the substrate layer is Si/SiO ₂ conductor substrate, the material of the adhesion layer is Ti, the material of the bottom electrode layer is Pt, the material of the current limiting layer is SiO ₂ ; the material of the resistive layer is TaON, and the material of the upper electrode layer is TaON. The material is TiN.

The preparation method of the resistive memory with low SET and RESET instantaneous power comprises the following steps:

S1. Prepare wafers: prepare silicon wafers, clean the silicon wafers to remove floating dust;

S2. Preparation of SiO ₂ semiconductor substrate after sulfuric acid cleaning: the substrate layer is grown by thermal oxidation process on the surface of the silicon wafer;

S3, prepare the adhesion layer: magnetron sputtering metal Ti, as the adhesion layer connecting the SiO ₂ semiconductor substrate and the bottom electrode Pt;

S4. Preparation of bottom electrode: magnetron sputtering metal Pt is used as the bottom electrode of SiO ₂ /TaON double-layer resistive memory;

S5, PECVD prepares the current limiting layer;

S6. Preparation of resistive switching layer: TaON is sputtered by magnetron-RF;

S7, magnetron sputtering TiN, gas Ar and N ₂ are introduced;

S8, AME etching, the etching gas is Cl ₂ to form a lead-out hole connected to the bottom electrode;

S9, photolithography lift-off to form discrete resistive memory devices.

Preferably, the conditions for magnetron-RF sputtering in the step S3 are: the background vacuum is not greater than 3.2×10 ^-4 Pa, the working pressure is not greater than 0.5Pa, and the sputtering power is 50W-100W;

The conditions of the magnetron-RF sputtering in step S4 are: the background vacuum is not more than 3.2×10 ^-4 Pa, and the working pressure is not more than 2.4Pa.

Preferably, the conditions for magnetron-RF sputtering in step S6 are: inert gases Ar, O ₂ , N ₂ are introduced, and the volume ratio of Ar, O ₂ , and N ₂ is 40: (1.5-10): 20, 3mTorr～10mTorr, sputtering power 50W～100W, target material adopts Ta ₂ O ₅ .

Preferably, the conditions for magnetron-RF sputtering in the step S7 are: the ratio of the gas Ar and N ₂ is (16-20): 2, the background vacuum is not greater than 3.2×10 ^-4 Pa, the working pressure is not greater than More than 2.4Pa, the reaction gas N ₂ flow rate is 20sccm ~ 25sccm, and the target material is Ti.

Beneficial effects of the present invention:

1. Proposed a low SET, RESET instantaneous power resistive memory with TiN/TaON/SiO2/Pt structure. 2. The _SiO2 prepared by PECVD is used as the current limiting layer to prevent the resistive layer from forming thick conductive wires and prevent the generation of large currents. . The _SiO2 prepared by PECVD contains more defects, electrons can be injected into the _SiO2 film, and the defects in the _SiO2 film can be used as traps to capture electrons. With the gradual increase of the applied electric field, these trapped electron transitions participate in conduction.

3. The TiN/TaON/SiO2/Pt resistive switching device has a good coincidence of the graphs under 100 DC scans, indicating that the uniformity of the resistive switching device is better, and the device shows a good resistive switching process, and no degradation occurs. . In addition, the resistive switching device does not perform the Forming process, so it exhibits bipolar resistive switching characteristics and can be stably reversed.

Description of drawings

1 is a schematic diagram of the structure of the resistive memory of the present invention;

Fig. 2 is the preparation flow chart of TiN/TaON/SiO2/Pt resistive memory of the present invention;

Figure 3 DC test results of the TiN/TaON/SiO2/Pt resistive memory prepared in Example 1;

Fig. 4 is the DC test result of the resistive variable memory prepared by embodiment 2;

Fig. 5 is the DC test result of the resistive variable memory prepared by embodiment 3;

Fig. 6 is the LRS statistical distribution of the resistive variable memory prepared in Example 3;

FIG. 7 is the statistical distribution of the HRS of the resistive variable memory prepared in Example 3. FIG.

Detailed ways

The present invention will be further described below in conjunction with the embodiments, but the claimed scope of the present invention is not limited to the scope expressed by the embodiments.

Example 1

As shown in Figure 1, a resistive memory with low SET and RESET instantaneous power includes a substrate layer (SiO ₂ ), an adhesion layer (Ti), a bottom electrode layer (Pt), and a current limiting layer (SiO ₂ ) that are stacked in sequence. , resistive switching layer (TaON) and upper electrode layer (TiN).

The preparation method of the resistive memory of the described low SET and RESET instantaneous power,

1. Prepare wafers: prepare n(100) crystal orientation 4-inch silicon wafers, clean the silicon wafers to remove floating dust;

2. Preparation of SiO ₂ semiconductor substrate after cleaning with sulfuric acid at room temperature: thermal oxidation process growth on the surface of 4-inch silicon wafer

金属Ti，作为粘附层连接SiO₂半导体衬底和底电极Pt，本底真空3.2×10^-4Pa，工作压强0.5Pa，溅射功率100W；3. Preparation of adhesion layer: magnetron sputtering

Metal Ti is used as an adhesive layer to connect the SiO ₂ semiconductor substrate and the bottom electrode Pt, the background vacuum is 3.2×10 ^-4 Pa, the working pressure is 0.5Pa, and the sputtering power is 100W;

的金属Pt作为SiO₂/TaON双层阻变存储器的底电极(BE)，本底真空3.2×10^-4Pa，工作压强2.4Pa,；4. Preparation of bottom electrode: magnetron sputtering

The metal Pt is used as the bottom electrode (BE) of the SiO ₂ /TaON double-layer resistive memory, the background vacuum is 3.2×10 ^-4 Pa, and the working pressure is 2.4Pa,;

5. Using SiH ₄ and N ₂ O to prepare SiO ₂ by PECVD process

通入惰性气体Ar、O₂、N₂，6mTorr，Ar、O₂、N₂的体积比为40：6：20，氧分压比例18％，溅射功率100W，靶材采用为φ60×3mm陶瓷靶材Ta₂O₅；6. Preparation of resistive layer: using physical vapor deposition RF sputtering TaON

Inert gas Ar, O ₂ , N ₂ , 6mTorr, the volume ratio of Ar, O ₂ , N ₂ is 40:6:20, the oxygen partial pressure ratio is 18%, the sputtering power is 100W, and the target material is φ60×3mm Ceramic target Ta ₂ O ₅ ;

通入气体Ar和N₂的比例为18:2，靶材为Ti,本底真空3.2×10^-4Pa，工作压强2.4Pa,反应气体N₂流量20sccm；7. Magnetron sputtering

The ratio of incoming gas Ar and N ₂ is 18:2, the target material is Ti, the background vacuum is 3.2×10 ^-4 Pa, the working pressure is 2.4Pa, and the flow rate of reaction gas N ₂ is 20sccm;

8. AME etching, the etching gas is Cl ₂ (chlorine), forming a lead-out hole connecting the bottom electrode;

9. Photolithographic lift-off to form discrete resistive memory devices.

The TiN/TaON/SiO2/Pt resistive switching device prepared in this example is shown in FIG. 3 under 100 DC scans. The coincidence of the graph lines is relatively good, indicating that the uniformity of the resistive switching device is relatively good, and the device shows a good resistive switching process without degradation. In addition, the resistive switching device does not perform the Forming process, so it exhibits bipolar resistive switching characteristics and can be stably reversed. The VSET of the resistive device is 5.7V, VRESET is -5.4V, the instantaneous power at SET is 28.5μW, and the instantaneous power at RESET is 5.4μW, which means that the resistance of TiN/TaON/SiO2/Pt is higher than that of TiN/TaON/Pt. The variable device has the characteristics of low power consumption.

Example 2

The difference from Example 1 is that there is no SiO ₂ as the current limiting layer. Others are the same as Example 1. The resistive switching device is obtained under 50 DC scans, as shown in FIG. 4 .

As shown in Figure 4, if there is no _SiO2 as the current limiting layer, there is no resistive switching characteristic under the condition of small current limiting, and the resistive switching device can only show the resistive switching characteristic under the current limiting of 1mA.

Example 3

The difference from Example 1 is that the volume ratio of Ar, O ₂ , and N ₂ in the resistive layer prepared in step 6 is changed. The volume ratio of Ar, O ₂ , and N ₂ is respectively 1# sample: 40:1.5:20 , 2# sample: 40:3:20, 3# sample: 40:3:20, others are the same as in Example 1, and the resistive device is obtained under 100 DC scans, as shown in Figure 6-7.

As shown in Figure 6-7. Compared with the samples of 2# and 3#, the uniformity of 1# is relatively high due to the change of gas volume ratio.

Claims (7)

1. A resistive random access memory with low SET and RESET instantaneous power is characterized in that: the device comprises a substrate layer, an adhesion layer, a bottom electrode layer, a current limiting layer, a resistance change layer and an upper electrode layer which are sequentially stacked.

2. The low SET and RESET transient power resistive random access memory of claim 1, wherein: the thickness of the adhesive layer is 100A-300A, the thickness of the bottom electrode layer is 800A-1000A, the thickness of the current limiting layer is 60A-100A, the thickness of the change-blocking layer is 100A-200A, and the thickness of the upper electrode layer is 500A-700A.

3. The low SET and RESET transient power resistive random access memory of claim 1, wherein: the substrate layer is made of Si/SiO ₂ A conductor substrate, an adhesion layer made of Ti, a bottom electrode layer made of Pt, and a current limiting layer made of SiO ₂ (ii) a The material of the resistance changing layer is TaON, and the material of the upper electrode layer is TiN.

4. The method for preparing a low SET and RESET transient power resistive random access memory according to any of claims 1-3, characterized in that:

s1, preparing tablets: preparing a silicon wafer, cleaning the silicon wafer to remove floating dust;

s2, cleaning with sulfuric acid to prepare SiO ₂ A semiconductor substrate: growing a substrate layer on the surface of the silicon wafer by a thermal oxidation process;

s3, preparing an adhesion layer: magnetron sputtering of metal Ti as adhesion layer to connect SiO ₂ A semiconductor substrate and a bottom electrode Pt;

s4, preparing a bottom electrode: magnetron sputtering of metal Pt as SiO ₂ A bottom electrode of the TaON double-layer resistive random access memory;

s5, preparing a flow limiting layer by PECVD;

s6, preparing a resistance change layer: adopting magnetron-RF sputtering TaON;

s7, magnetron sputtering TiN, and introducing Ar and N gases ₂ ；

S8, AME etching, wherein the etching gas is Cl ₂ Forming a bottom electrode leading-out hole;

and S9, photoetching and stripping to form a discrete resistive random access memory device.

5. The method for preparing a low SET and RESET transient power resistive random access memory according to claim 4, characterized in that: the conditions of the step S3 magnetron-RF sputtering are as follows: background vacuum of not more than 3.2 × 10 ^-4 Pa, working pressure is not more than 0.5Pa, and sputtering power is 50-100W;

the conditions of the step S4 magnetron-RF sputtering are as follows: background vacuum of not more than 3.2 × 10 ^-4 Pa, and the working pressure is not more than 2.4 Pa.

6. The method for preparing a low SET and RESET transient power resistive random access memory according to claim 4, characterized in that: the conditions of the step S6 magnetron-RF sputtering are as follows: inert gases Ar and O are introduced ₂ 、N ₂ ，Ar、O ₂ 、N ₂ Is 40: (1.5-10): 20, 3mTorr to 10mTorr, sputtering power of 50W to 100W, and Ta as a target material ₂ O ₅ 。

7. The method for preparing a low SET and RESET transient power resistive random access memory according to claim 4, characterized in that: the conditions of the step S7 magnetron-RF sputtering are as follows: introducing Ar and N ₂ In a ratio of (16-20):2, and a background vacuum of not more than 3.2X 10 ^-4 Pa, working pressure not more than 2.4Pa, and reaction gas N ₂ The flow rate is 20-25 sccm, and the target material is Ti.

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