CN114822631A - Hybrid NVME SSD storage system based on MRAM main memory - Google Patents
Hybrid NVME SSD storage system based on MRAM main memory Download PDFInfo
- Publication number
- CN114822631A CN114822631A CN202210408210.9A CN202210408210A CN114822631A CN 114822631 A CN114822631 A CN 114822631A CN 202210408210 A CN202210408210 A CN 202210408210A CN 114822631 A CN114822631 A CN 114822631A
- Authority
- CN
- China
- Prior art keywords
- mram
- controller
- application
- nand
- dram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013507 mapping Methods 0.000 claims abstract description 69
- 230000003993 interaction Effects 0.000 claims description 9
- 239000002245 particle Substances 0.000 claims description 8
- 238000012937 correction Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 3
- 230000009191 jumping Effects 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention discloses a hybrid NVME SSD storage system based on an MRAM main memory, which comprises an application layer, a control layer and a storage layer, wherein the application layer comprises n application I, 1 application II and a PCIE interface I, n is a positive integer, the application II adopts a shared cache HMB, and the shared cache HMB is separated from a cache region of the application I; the control layer includes n +1 Name Space managers, PCIE interface II, NVME controller, FTL mapping manager, built-in SRAM, NAND controller, DRAM controller and MRAM controller, PCIE interface II links to each other with the PCIE interface, n +1 Name Space managers respectively with n application I and 1 application II corresponding, NVME controller is connected between PCIE interface II and n +1 Name Space managers. The random performance and reliability of the NVME SSD controller are improved in a targeted manner by combining the advantages of the MRAM, and the data security is guaranteed.
Description
Technical Field
The invention relates to the field of storage, in particular to a hybrid NVME SSD storage system based on an MRAM main memory.
Background
NVME is a host controller interface specification applied to non-volatile memory. The PCI Express bus interface is widely applied to an application layer protocol realized by a PCI Express bus at present and is used for connecting with a nonvolatile storage medium. Compared with the maximum 32 groups of command queues which can be provided by the traditional SATA SSD hard disk, the NVME SSD provides thousands of parallel queues to control IO data streams, so that the delay can be greatly reduced, and the IOPS capability of the SSD is greatly improved.
NAND FLASH is adopted as a nonvolatile memory in the current NVME SSD, but NAND FLASH flash memory needs to be combined with the use limitation of the flash memory to complete the development of SSD software codes when being applied. Meanwhile, as the error rate of 3D TLC NAND is too high, BCH cannot be solved, and LDPC must be used. In addition, if abnormal power failure occurs under the normal working conditions of SSD read, write, delete, etc., it may cause the FTL mapping table to be lost because it is not time to update, so that a failure occurs in which SSD cannot be identified by the system.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a hybrid NVME SSD storage system based on an MRAM main memory, which combines the advantages of the MRAM, purposefully improves the random performance and reliability of an NVME SSD controller, and ensures the data security.
In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a hybrid NVME SSD storage system based on MRAM main memory comprises an application layer, a control layer and a storage layer, wherein the application layer comprises n application I, 1 application II and a PCIE interface I, n is a positive integer, the application II adopts a shared cache HMB, and the shared cache HMB is separated from a cache region of the application I; the control layer comprises n +1 Name Space managers, a PCIE interface II, an NVME controller, an FTL mapping manager, a built-in SRAM, an NAND controller, a DRAM controller and an MRAM controller, the PCIE interface II is connected with the PCIE interface, the device is used for realizing data transmission of an application layer and a control layer, n +1 Name Space managers respectively correspond to n application I and 1 application II, an NVME controller is connected between a PCIE interface II and the n +1 Name Space managers and used for processing an NVME protocol and transmitting the processed NVME protocol to the Name Space managers, the Name Space managers logically divide user spaces of a storage system, each application operates independently under the management of a Name Space manager, an FTL mapping manager is connected between the Name Space manager and a built-in SRAM, a NAND controller, a DRAM controller and an MRAM controller, and the FTL mapping manager is responsible for maintaining the mapping relation from a logical block address LBA to a storage medium physical block address PBA; the storage layer comprises an external NAND, an external DRAM and an external MRAM, the external NAND is connected with the NAND controller and used for storing user data and an FTL mapping table in the application I, the external DRAM is connected with the DRAM controller and used for storing read buffer data, write buffer data, the FTL mapping table, FTL mapping table variable quantity, user data labels, user configuration items and operation logs, and the external MRAM is connected with the MRAM controller and used for storing user data and key log information in the application II; the built-in SRAM is used for caching data in NVME read commands of n Name spaces.
Further, the inter-component data flow path based on the system is as follows: NAND FLASH write data flow in the storage area is from FTL mapping manager to DRAM controller, then from DRAM controller to NAND controller, the read data flow is from NAND controller to built-in SRAM through route third, to FTL mapping manager through route first; the write data flow path in the MRAM memory region is: from the FTL mapping manager to the MRAM controller, and from the MRAM controller to the FTL mapping manager; NAND FLASH storing area key data backup service data flow from NAND controller to FTL mapping manager, then from FTL mapping manager to MRAM controller; the critical data-derived traffic data flow is from the MRAM controller to the FTL mapping manager, and then from the FTL mapping manager to the DRAM controller.
Further, the application I applies for allocating a cache space with continuous logical addresses to the host operating system for use by the control layer, the control layer stores the FTL mapping table in the block area of the host, and after each IO request is sent to the SSD, the controller accesses the block storage space of the host through the PCIE interface so as to extract corresponding entries in the FTL mapping table to search for the physical address to which the corresponding IO target logical address is mapped.
Further, the establishing process of the Name Space corresponding to the application II comprises the following steps:
a) judging whether a Name Space corresponding to the application needs to be newly established or not according to the application requirements, if so, establishing the Name Space through private command negotiation, and if not, jumping to the step e);
b) reading the MRAM particle ID and identifying the particle maker;
c) reading MRAM controller information, identifying capacity and speed;
d) the application layer establishes a shared cache HMB;
e) loading mapping management;
f) the establishment is successful.
Furthermore, the physical address of the shared cache HMB is discontinuous, and the control layer adopts an addressing mode of adding offset to the base address for the memory-proof search of the HMB.
Further, each Name Space has its own ID, and the ID of each Name Space is consistent with the application ID in the application layer.
Further, when the NAND FLASH storage area is used, the FTL mapping manager places the mapping table in the external DRAM through the DRAM controller; when using the MRAM storage area, the FTL mapping manager places the mapping table in the HMB in the upper application layer through the PCIE interface.
Further, the NAND controller comprises a NAND ECC unit and a NAND interface, the NAND interface is responsible for finishing data interaction with an external NAND in a bottom storage medium layer, and the NAND ECC unit adopts a low-density forward check code LDPC error correction algorithm to protect the data block.
Furthermore, the DRAM controller comprises a DRAM ECC unit and a DRAM interface, the DRAM interface is responsible for finishing data interaction with an external DRAM in a bottom storage medium layer, and the DRAM ECC unit adopts Hamming codes to protect according to bytes and supports correcting one bit and detecting two bits.
Furthermore, the MRAM controller comprises an MRAM ECC unit and an MRAM interface, the MRAM interface is responsible for finishing data interaction with the external MRAM in the bottom storage medium layer, and the MRAM ECC unit adopts a BCH error correction algorithm to protect the data block.
The invention has the beneficial effects that:
more efficient I/O management is achieved. MRAM is used as a high-reliability high-performance storage area supplemented in SSD, the I/O performance of SSD can be improved, and SSD manufacturers can better manage I/O flow, so that better delay certainty is realized, and QoS is improved.
The high-reliability and high-performance area writing management is simple, the data block operation is adopted, the complex FTL algorithm management is not needed, and meanwhile, after the data block is integrally protected by adopting the BCH, the reliability of data is improved, the stability of the data reading and writing performance is kept, and the application requirements in key core services such as server application and the like are met.
The atomicity of data written in a high-performance and high-reliability storage area is maintained, the atomicity of IO operation written in the area is guaranteed, one IO is written in completely, or the whole writing fails, and the situations that part of data is written in one IO and part of data is not written in can be avoided. And only when all the data of the IO is written into the MRAM, the writing completion is replied to the upper computer.
In the using process of the high-performance and high-reliability storage area, temporary data generated by the SSD controller are placed in the HMB in the upper computer, the using requirements on the SRAM and the DRAM in the SSD controller are reduced, and the consistency problem caused by the common use of two types of NameSpace is avoided.
The device is used as a host-side peripheral module device and has good compatibility. Because the device is used as a block device, the NameSpace can be created and used only by writing corresponding private instructions without modifying an operating system.
The DRAM is mixed with DRAM to form a new memory system, and the cost is easy to accept. After the specific functions of the unit modules in part of the SSD controller are added, the MRAM particles can be used, and a corresponding common application area or a high-performance and high-reliability area is used according to the service requirements of a user, so that the increase of key service performance is brought, no expensive cost is generated, and the large-scale application becomes practical.
Drawings
FIG. 1 is a functional block diagram of the present invention;
FIG. 2 is a schematic diagram of a process for establishing a network using NameSpace.
Detailed Description
The invention is further described with reference to the following figures and specific examples.
Example 1
The embodiment discloses a hybrid NVME SSD storage system based on an MRAM main memory, which aims to improve the random performance and reliability of an NVME SSD controller and guarantee the data security.
As shown in fig. 1, the present system includes an upper application layer, a middle control layer, and a bottom storage layer.
The application layer comprises n applications I, 1 application II and a PCIE interface I, wherein n is a positive integer. In this embodiment, the application I is a general application, the number of which is not limited, and the application II is a high-performance and high-reliability application. And the application II adopts a shared cache HMB, and the shared cache HMB is separated from a cache region of the application I, so that the cache atomicity of the application is ensured, and the synchronization problem is avoided. The application I applies for allocating a cache space with continuous logical addresses to the host operating system for use by the control layer, the control layer stores the FTL mapping table in the block area of the host, and after each IO request is sent to the SSD, the controller accesses the block storage space of the host through the PCIE interface so as to extract corresponding entries in the FTL mapping table to search for the physical address mapped to the corresponding IO target logical address.
In this embodiment, the physical addresses of the shared cache HMB are not continuous, and the control layer uses an addressing mode of base address plus offset for the save-proof lookup of the HMB.
The control layer includes n +1 Name Space managers, PCIE interface II, NVME controller, FTL mapping manager, built-in SRAM, NAND controller, DRAM controller and MRAM controller, PCIE interface II links to each other with the PCIE interface for realize the data transmission of application layer and control layer, n +1 Name Space managers correspond with n application I and 1 application II respectively, every Name Space has the ID of self, the ID of every Name Space is unanimous with the application ID in the application layer. The NVME controller is connected between a PCIE interface II and n +1 Name Space managers, the NVME controller is used for processing an NVME protocol and transmitting the processed NVME protocol to the Name Space managers, the Name Space managers perform logic division on user spaces of the storage system, each application performs formatting, encryption and other operations independently under the management of the Name Space managers, the FTL mapping managers are connected between the Name Space managers and built-in SRAMs, NAND controllers, DRAM controllers and MRAM controllers, and the FTL mapping managers are responsible for maintaining the mapping relation from the logical block addresses LBA to the physical block addresses PBA of the storage medium.
In this embodiment, the NVME controller includes a standard command parsing unit and a private command parsing unit, where the standard command parsing unit is used to establish and use a Name Space corresponding to the application I; the private command analysis unit is used for establishing and using the Name Space corresponding to the application II.
The storage layer comprises an external NAND, an external DRAM and an external MRAM, the external NAND is connected with the NAND controller and used for storing user data and an FTL mapping table in the application I, the external DRAM is connected with the DRAM controller and used for storing read buffer data, write buffer data, the FTL mapping table, FTL mapping table variable quantity, user data labels, user configuration items and operation logs, and the external MRAM is connected with the MRAM controller and used for storing user data and key log information in the application II; the built-in SRAM is used for caching data in NVME read commands of n Name spaces.
The inter-component data flow path based on the system is as follows: NAND FLASH write data flow in the storage area is from FTL mapping manager to DRAM controller, then from DRAM controller to NAND controller, the read data flow is from NAND controller to built-in SRAM, and from built-in SRAM to FTL mapping manager; the write data flow path in the MRAM memory region is: from the FTL mapping manager to the MRAM controller, and from the MRAM controller to the FTL mapping manager; NAND FLASH storing area key data backup service data flow from NAND controller to FTL mapping manager, then from FTL mapping manager to MRAM controller; the critical data-derived traffic data flow is from the MRAM controller to the FTL mapping manager, and then from the FTL mapping manager to the DRAM controller.
As shown in fig. 2, the establishing process of the Name Space corresponding to the application II is as follows:
a) judging whether a Name Space corresponding to the application layer needs to be newly built or not according to the application requirement, if the Name Space needs to be newly built according to a first request sent by the application layer, starting to build a Name Space flow through private command negotiation, and if the Name Space does not need to be built, jumping to the step e);
b) reading the ID of the MRAM particles, and identifying information such as particle manufacturers, serial numbers, particle health states and the like;
c) reading MRAM controller information, identifying capacity and speed, and configuring corresponding MRAM ECC function;
d) the application layer establishes a shared cache HMB for storing various cache information required in the running process of the middle-layer SSD controller;
e) loading mapping management, namely establishing different physical address mapping relations according to the size of the application layer logical block address;
f) the establishment is successful.
When NAND FLASH storage area is used, the FTL mapping manager places the mapping table in an external DRAM through a DRAM controller; when using the MRAM storage area, the FTL mapping manager places the mapping table in the HMB in the upper application layer through the PCIE interface. And the built-in static memory SRAM is used for storing cache data in the NVME read command of the common Name Space.
The NAND controller comprises a NAND ECC unit and a NAND interface, the NAND interface is responsible for finishing data interaction with an external NAND in a bottom storage medium layer, and the NAND ECC unit adopts a low-density forward check code LDPC error correction algorithm to protect a data block.
The DRAM controller comprises a DRAM ECC unit and a DRAM interface, the DRAM interface is responsible for finishing data interaction with an external DRAM in a bottom storage medium layer, and the DRAM ECC unit adopts Hamming codes to protect according to bytes and supports correcting one bit and detecting two bits.
The MRAM controller comprises an MRAM ECC unit and an MRAM interface, the MRAM interface is responsible for finishing data interaction with an external MRAM in a bottom storage medium layer, and the MRAM ECC unit adopts a BCH error correction algorithm to protect a data block.
The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art are included in the scope of the present invention.
Claims (10)
1. A hybrid NVME SSD storage system based on MRAM host storage, characterized by: the system comprises an application layer, a control layer and a storage layer, wherein the application layer comprises n application I, 1 application II and a PCIE interface I, n is a positive integer, the application II adopts a shared cache HMB, and the shared cache HMB is separated from a cache area of the application I; the control layer comprises n +1 Name Space managers, a PCIE interface II, an NVME controller, an FTL mapping manager, a built-in SRAM, an NAND controller, a DRAM controller and an MRAM controller, the PCIE interface II is connected with the PCIE interface, the device is used for realizing data transmission of an application layer and a control layer, n +1 Name Space managers respectively correspond to n application I and 1 application II, an NVME controller is connected between a PCIE interface II and the n +1 Name Space managers and used for processing an NVME protocol and transmitting the processed NVME protocol to the Name Space managers, the Name Space managers logically divide user spaces of a storage system, each application operates independently under the management of a Name Space manager, an FTL mapping manager is connected between the Name Space manager and a built-in SRAM, a NAND controller, a DRAM controller and an MRAM controller, and the FTL mapping manager is responsible for maintaining the mapping relation from a logical block address LBA to a storage medium physical block address PBA; the storage layer comprises an external NAND, an external DRAM and an external MRAM, the external NAND is connected with the NAND controller and used for storing user data and an FTL mapping table in the application I, the external DRAM is connected with the DRAM controller and used for storing read buffer data, write buffer data, the FTL mapping table, FTL mapping table variable quantity, user data labels, user configuration items and operation logs, and the external MRAM is connected with the MRAM controller and used for storing user data and key log information in the application II; the built-in SRAM is used for caching data in NVME read commands of n Name spaces.
2. The MRAM hosting based hybrid NVME SSD storage system of claim 1, wherein: the inter-component data flow path based on the system is as follows: NAND FLASH write data flow in the storage area is from FTL mapping manager to DRAM controller, then from DRAM controller to NAND controller, the read data flow is from NAND controller to built-in SRAM, then from built-in SRAM to FTL mapping manager; the write data flow path in the MRAM memory region is: from the FTL mapping manager to the MRAM controller, and from the MRAM controller to the FTL mapping manager; NAND FLASH storing area key data backup service data flow from NAND controller to FTL mapping manager, then from FTL mapping manager to MRAM controller; the critical data-derived traffic data flow is from the MRAM controller to the FTL mapping manager, and then from the FTL mapping manager to the DRAM controller.
3. The MRAM hosting based hybrid NVME SSD storage system of claim 1, wherein: the application I applies for allocating a cache space with continuous logical addresses to the host operating system for use by the control layer, the control layer stores the FTL mapping table in the block area of the host, and after each IO request is sent to the SSD, the controller accesses the block storage space of the host through the PCIE interface so as to extract corresponding entries in the FTL mapping table to search for the physical address mapped to the corresponding IO target logical address.
4. The MRAM hosting based hybrid NVME SSD storage system of claim 1, wherein: the establishing process of the Name Space corresponding to the application II comprises the following steps:
a) judging whether a Name Space corresponding to the application needs to be newly established or not according to the application requirements, if so, establishing the Name Space through private command negotiation, and if not, jumping to the step e);
b) reading the MRAM particle ID and identifying the particle maker;
c) reading MRAM controller information, identifying capacity and speed;
d) the application layer establishes a shared cache HMB;
e) loading mapping management;
f) the establishment is successful.
5. The MRAM hosting based hybrid NVME SSD storage system of claim 1, wherein: the physical address of the shared cache HMB is discontinuous, and the control layer adopts an addressing mode of adding offset to the base address for the memory-proof searching of the HMB.
6. The MRAM hosting based hybrid NVME SSD storage system of claim 1, wherein: each Name Space has its own ID, and the ID of each Name Space is consistent with the application ID in the application layer.
7. The MRAM hosting based hybrid NVME SSD storage system of claim 1, wherein: when NAND FLASH memory areas are used, the FTL mapping manager places the mapping table in an external DRAM through a DRAM controller; when using the MRAM storage area, the FTL mapping manager places the mapping table in the HMB in the upper application layer through the PCIE interface.
8. The MRAM hosting based hybrid NVME SSD storage system of claim 1, wherein: the NAND controller comprises a NAND ECC unit and a NAND interface, the NAND interface is responsible for finishing data interaction with an external NAND in a bottom storage medium layer, and the NAND ECC unit adopts a low-density forward check code LDPC error correction algorithm to protect a data block.
9. The MRAM hosting based hybrid NVME SSD storage system of claim 1, wherein: the DRAM controller comprises a DRAM ECC unit and a DRAM interface, the DRAM interface is responsible for finishing data interaction with an external DRAM in a bottom storage medium layer, and the DRAM ECC unit adopts Hamming codes to protect according to bytes and supports correcting one bit and detecting two bits.
10. The MRAM hosting based hybrid NVME SSD storage system of claim 1, wherein: the MRAM controller comprises an MRAM ECC unit and an MRAM interface, the MRAM interface is responsible for finishing data interaction with an external MRAM in a bottom storage medium layer, and the MRAM ECC unit adopts a BCH error correction algorithm to protect a data block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210408210.9A CN114822631B (en) | 2022-04-19 | 2022-04-19 | MRAM (magnetic random Access memory) -based hybrid NVME (storage media management memory) SSD (solid State disk) storage system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210408210.9A CN114822631B (en) | 2022-04-19 | 2022-04-19 | MRAM (magnetic random Access memory) -based hybrid NVME (storage media management memory) SSD (solid State disk) storage system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114822631A true CN114822631A (en) | 2022-07-29 |
| CN114822631B CN114822631B (en) | 2024-10-11 |
Family
ID=82506449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210408210.9A Active CN114822631B (en) | 2022-04-19 | 2022-04-19 | MRAM (magnetic random Access memory) -based hybrid NVME (storage media management memory) SSD (solid State disk) storage system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114822631B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106294226A (en) * | 2016-07-27 | 2017-01-04 | 中电海康集团有限公司 | SSD controller chip based on embedded STT MRAM, solid state hard disc |
| US20180039578A1 (en) * | 2016-08-04 | 2018-02-08 | Samsung Electronics Co., Ltd. | Data storage device using host memory and method of operating same |
| CN111831226A (en) * | 2020-07-07 | 2020-10-27 | 山东华芯半导体有限公司 | Method for accelerating processing of autonomously output NVME protocol command |
| CN111858401A (en) * | 2019-04-28 | 2020-10-30 | 北京忆恒创源科技有限公司 | Storage Device Providing Heterogeneous Namespace and Its Application in Database |
| US20210173786A1 (en) * | 2019-12-09 | 2021-06-10 | Western Digital Technologies, Inc. | Storage System and Method for Caching a Single Mapping Entry for a Random Read Command |
| CN113760796A (en) * | 2021-09-01 | 2021-12-07 | 山东华芯半导体有限公司 | SSD solid state dish based on HBM cache |
-
2022
- 2022-04-19 CN CN202210408210.9A patent/CN114822631B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106294226A (en) * | 2016-07-27 | 2017-01-04 | 中电海康集团有限公司 | SSD controller chip based on embedded STT MRAM, solid state hard disc |
| US20180039578A1 (en) * | 2016-08-04 | 2018-02-08 | Samsung Electronics Co., Ltd. | Data storage device using host memory and method of operating same |
| CN111858401A (en) * | 2019-04-28 | 2020-10-30 | 北京忆恒创源科技有限公司 | Storage Device Providing Heterogeneous Namespace and Its Application in Database |
| US20210173786A1 (en) * | 2019-12-09 | 2021-06-10 | Western Digital Technologies, Inc. | Storage System and Method for Caching a Single Mapping Entry for a Random Read Command |
| CN111831226A (en) * | 2020-07-07 | 2020-10-27 | 山东华芯半导体有限公司 | Method for accelerating processing of autonomously output NVME protocol command |
| CN113760796A (en) * | 2021-09-01 | 2021-12-07 | 山东华芯半导体有限公司 | SSD solid state dish based on HBM cache |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114822631B (en) | 2024-10-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11281601B2 (en) | Multi-device storage system with hosted services on peer storage devices | |
| CN111373362B (en) | Multi-device storage system with distributed read/write processing | |
| US11243837B2 (en) | Data storage drive rebuild with parity generation offload using peer-to-peer data transfers | |
| US10725859B2 (en) | Parity generation offload using peer-to-peer data transfers in data storage system | |
| US8578127B2 (en) | Apparatus, system, and method for allocating storage | |
| US9026845B2 (en) | System and method for failure protection in a storage array | |
| CN112445723A (en) | Apparatus and method for transferring mapping information in memory system | |
| US10108359B2 (en) | Method and system for efficient cache buffering in a system having parity arms to enable hardware acceleration | |
| KR102703983B1 (en) | Storage device storing data in raid manner | |
| US11593000B2 (en) | Data processing method and apparatus | |
| CN103534688B (en) | Data reconstruction method, memory device and storage system | |
| KR20210064359A (en) | How to restore data from storage systems, systems and devices | |
| US11544205B2 (en) | Peer storage devices sharing host control data | |
| US20190114220A1 (en) | Method and apparatus for enhancing data integrity using dual error detection and repair protection for ssd | |
| CN112599170A (en) | Apparatus and method for providing multi-stream operation in a memory system | |
| US20250130728A1 (en) | Storage system and method of operating the same | |
| US20210311654A1 (en) | Distributed Storage System and Computer Program Product | |
| KR20220103378A (en) | Apparatus and method for handling data stored in a memory system | |
| US20200334103A1 (en) | Storage system, drive housing thereof, and parity calculation method | |
| CN116917873A (en) | Data access methods, storage controllers and storage devices | |
| US12423184B2 (en) | Storage system and operating method thereof | |
| CN114822631A (en) | Hybrid NVME SSD storage system based on MRAM main memory | |
| CN118259823A (en) | A distributed storage unit set and related data storage method | |
| EP4394610A1 (en) | Computer device, method for processing data, and computer system | |
| CN103098034B (en) | The apparatus and method of operation are stored for condition and atom |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |