CN114818604A

CN114818604A - Method and device for correcting short-circuit defect on digital layout

Info

Publication number: CN114818604A
Application number: CN202210745722.4A
Authority: CN
Inventors: 曹灿; 彭书涛; 邹京; 曾炎; 曾朵朵
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2022-06-29
Filing date: 2022-06-29
Publication date: 2022-07-29
Anticipated expiration: 2042-06-29
Also published as: CN114818604B

Abstract

The embodiment of the application provides a method and a device for correcting short-circuit defects on a digital layout, wherein the method comprises the following steps: acquiring a plurality of short-circuit defects existing in the digital layout; if at least part of the short-circuit defects are determined to belong to a target type short circuit, taking an area where each short-circuit defect is located in the at least part of the short-circuit defects as a target processing area, wherein the target type short circuit belongs to the short-circuit defects caused by metal cutting processing, and the number of the target processing areas is one or more; and deleting the target object of the target processing area on the digital layout to obtain a target digital layout, wherein the target object is a metal layer causing short circuit of the target type. According to the method and the device, the defect that physical short circuit violation caused by metal cutting treatment is overcome in batches can be effectively guaranteed on the premise that the chip meets design functions and performances, so that the violation repair time of design rules is shortened, and the chip design reliability is improved.

Description

Method and device for correcting short-circuit defect on digital layout

Technical Field

The application relates to the field of chip design and manufacture, in particular to a method and a device for correcting short-circuit defects on a digital layout.

Background

In the manufacturing process of the integrated circuit, the physical characteristics and the manufacturing process of a physical device are limited, a physical design layout (or called a digital layout) must comply with a series of characteristic rules, the rules are a set of geometric dimension design rules for guiding layout design, minimum allowable values such as the width, the interval, the overlapping, the distance between layers and the like of each layer of geometric figures of a mask layout (or called a mask) are specified, the process of the integrated circuit can be realized in the manufacturing process, the problem of a chip cannot be caused, and various constraint conditions for layout design can be met.

In order to make the designed digital layout meet the requirements of the design rules, the layout design rule check is required, and if the design rules are violated, the violation results are modified.

The metal cutting processing Cut metal is a new technology introduced by a 7nm manufacturing process for minimizing the minimum spacing violation, the minimum area violation and the through hole edge binding violation of the same layer metal, for example, the metal cutting processing Cut metal is applied to an M1 metal layer and an M2 metal layer, and a complete metal shape is etched and broken into two independent metal shapes, so that the layout design rule violation is reduced.

Disclosure of Invention

The embodiments of the present application provide a method and an apparatus for correcting a short-circuit defect on a digital layout, which can effectively solve a physical short-circuit violation defect caused by metal cutting in batch on the premise of satisfying chip design functions and performances, thereby shortening a time for violation repair of design rules and improving reliability of chip design.

In a first aspect, an embodiment of the present application provides a method for correcting a short defect on a digital layout, where the method includes: acquiring a plurality of short-circuit defects existing in the digital layout; if at least part of the short-circuit defects are determined to belong to a target type short circuit, taking an area where each short-circuit defect is located in the at least part of the short-circuit defects as a target processing area, wherein the target type short circuit belongs to the short-circuit defects caused by metal cutting processing, and the number of the target processing areas is one or more; and deleting the target object of the target processing area on the digital layout to obtain a target digital layout, wherein the target object is a metal layer causing short circuit of the target type.

Some embodiments of the present application reduce short circuit rule violation repair time and improve chip design reliability by identifying all short circuit defects present on a digital layout caused by a cut metal layer and a metal layer adjacent to the cut metal layer and deleting the metal layers causing the short circuit defects.

In some embodiments, the acquiring the plurality of short defects existing in the digital layout includes: and checking a layout design rule of the digital layout to obtain the plurality of short-circuit defects, wherein each short-circuit defect in the plurality of short-circuit defects is represented by network information and metal level information respectively.

Some embodiments of the present application may obtain all short defects present on a digital layout by performing layout design rule checking on the digital layout.

In some embodiments, the obtaining the plurality of short-circuit defects by performing layout design rule checking on the digital layout includes: acquiring a process rule and the digital layout; and checking the digital layout design rule through electronic design automation software according to the process rule.

Some embodiments of the present application identify all short defects present on a digital layout by process rules and electronic design automation software, namely EDA software.

In some embodiments, the network information is used to characterize a network on the digital layout, and the metal level information is used to characterize a metal layer on which a trace connecting two ports is located.

Some embodiments of the present application record each short-circuit defect through network information and metal level information, so as to subsequently obtain a target type short-circuit defect by traversing each short-circuit defect and ensure that excessive deletion is not performed when deleting a target object causing the short-circuit defect.

In some embodiments, if it is determined that at least some of the short-circuit defects belong to a target type short circuit, taking an area where each short-circuit defect of the at least some short-circuit defects is located as a target processing area includes: judging whether any short-circuit defect in the plurality of short-circuit defects belongs to the target type short circuit or not, if so, marking any short-circuit defect to obtain a marked defect, and if not, skipping, wherein the marked defect belongs to one of at least part of short-circuit defects; recording the position of the mark defect to obtain the target processing area corresponding to the mark defect; the deleting the target object of the target processing area on the digital layout comprises: acquiring the characterization information of all the mark defects; selecting the target object according to the characterization information; and deleting the cutting metal layer and the target object which are positioned in the target processing area from the digital layout.

According to some embodiments of the application, the short circuit defects caused by cutting the metal layer can be deleted in batches subsequently in a mode of traversing and marking short circuits of all target types one by one.

In some embodiments, the characterization information includes: a network name and an overlapping metal hierarchy, wherein the network name is used for characterizing a target network with a short-circuit fault at the position, and the overlapping metal hierarchy is used for characterizing a target metal layer causing the short-circuit fault in the target network; wherein, the obtaining the target object according to the characterization information includes: acquiring the target network; acquiring the target metal layer in the target network; taking the target metal layer as the target object; the deleting the cut metal layer and the target object located in the target processing area from the digital layout includes: and deleting the cutting metal layer and the target metal layer.

Some embodiments of the present application accurately determine metal layers involved in a target type short circuit through a network name and overlapping metal levels, and subsequently delete these metal layers to avoid the defect of open circuit problem in a digital layout due to inaccurate deletion.

In some embodiments, the target network belongs to at least one of a clock network, a power network, and a signal network.

The network of some embodiments of the present application includes various network types on the digital layout, improving the versatility of the technical solution.

In some embodiments, said marking, if any, of said any short defects comprises: and marking any short-circuit defect in the marking area by using a marking characteristic.

Some embodiments of the application mark each target processing region by using a specific marking feature in one region, thereby facilitating subsequent uniform selection of the differences and deletion operations.

In some embodiments, the deleting the cut metal layer and the target object located in the target processing region from the digital layout includes: and selecting the target metal layer and the cutting metal layer included in all the mark areas on the digital layout and deleting the target metal layer and the cutting metal layer.

According to some embodiments of the application, the target type short circuit in the digital layout can be corrected by selecting and deleting the relevant metal layer in the mark region, and the problem of short circuit violation of the digital layout is solved.

In some embodiments, after deleting the target object of the target processing region on the digital layout to obtain a target digital layout, the method further includes: and carrying out design rule checking and winding processing on the target digital layout to determine whether the target digital layout further comprises the target type short circuit defect.

Some embodiments of the present application also require that the revised layout be confirmed again to improve the short circuit violation problem of the finally obtained digital layout.

In a second aspect, some embodiments of the present application provide an apparatus for correcting short defects on a digital layout, the apparatus comprising: the short-circuit defect acquisition modules are used for acquiring a plurality of short-circuit defects existing in the digital layout; a target processing area obtaining module configured to determine that at least some of the plurality of short-circuit defects belong to a target type short circuit, and then use an area where each short-circuit defect of the at least some short-circuit defects is located as a target processing area, where the target type short circuit belongs to a short circuit caused by metal cutting processing, and the number of the target processing areas is one or more; and the deleting module is configured to delete the target object of the target processing area on the digital layout to obtain a target digital layout, wherein the target object is a metal layer causing the target type short circuit.

In a third aspect, some embodiments of the present application provide a chip manufacturing method, including: obtaining a plurality of masks according to the target digital layout according to any embodiment of the first aspect; and manufacturing a chip according to the plurality of mask plates.

In a fourth aspect, some embodiments of the present application provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, may implement the method as described in any of the embodiments of the first and third aspects above.

In a fifth aspect, some embodiments of the present application provide an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor, when executing the program, may implement the method as in any of the first and third aspects.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

FIG. 1 is a cross-sectional view of a chip provided in the related art;

FIG. 2 is a top view of a chip including a cut metal layer according to the related art;

FIG. 3 is a flowchart of a method for correcting a short defect on a digital layout according to an embodiment of the present application;

FIG. 4 is a second flowchart of a method for correcting a short defect on a digital layout according to an embodiment of the present application;

FIG. 5 is a third flowchart of a method for correcting a short defect on a digital layout according to an embodiment of the present application;

FIG. 6 is a block diagram illustrating an apparatus for correcting short defects on a digital layout according to an embodiment of the present disclosure;

fig. 7 is a schematic composition diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Referring to fig. 1, fig. 1 is a cross-sectional view of any chip provided in the related art, which may exemplarily show a metal layer structure of metal interconnection, and which shows metal layers of various layers involved in a front-end process and a back-end process.

M1 (Metal Layer 1), M2, M3 and M4 in fig. 1 refer to four layers of transverse Metal connecting lines, and it is understood that only transverse lines on a chip have no longitudinal connection, so Via in fig. 1 is a longitudinal connection, and different Metal layers are connected together to realize the function of the whole chip. In practice, Via 1 and M1 are produced simultaneously during the production of the metal conductor (copper process). Fig. 1 further includes a passivation layer, a pad metal layer, a shallow trench isolation, an L1 metal, a P-well, etc., which are not further described since they are not related to the improvement of the present application.

Related art metal cutting Cut metal is a new technology introduced by a 7nm manufacturing process in order to minimize minimum pitch violations, minimum area violations and via taping violations for the same layer of metal (i.e., the same metal layer). For example, a metal cutting technique may be applied to a first metal layer to obtain a first cut metal layer (e.g., fig. 2) and applied to a second metal layer to obtain a second cut metal layer M2 (e.g., fig. 2), which is a process of etching a complete metal shape into two separate metal shapes to reduce layout rule violations. It should be noted that, in some embodiments, because the manufacturing process rules of the M3 and M4 layers of metal are different, the cut metal is mainly introduced by solving the problem of minimum spacing between the M1 or M2 end-of-line layers, and the cost is high, and if such a technique is cited in all layers, the manufacturing cost will be greatly increased, so the metal cutting process is only used in the M1 layer and the M2 layer at present, but the embodiment of the present application does not limit the specific level of the metal cutting process. Other contents included in fig. 2 are irrelevant to the improvement point of the present application and therefore are not described in detail, and fig. 1 and fig. 2 are not a chip, fig. 1 is only used for explaining each metal layer, and fig. 2 is only used for explaining the application of cut metal technology in the relevant metal layer. As in the related art, different depth values in fig. 2 represent different hierarchies.

However, the inventor of the present application found in the research that in the actual routing process, there are usually a lot of short circuit problems caused by too small distance between the cut metal layer and the bottom metal of the cell port (this is because the short circuit of the cut metal occurs mainly at the pin position of the bottom of the cell, and the pin layers of the cell are basically M1 and M2), and if the short circuit problems are repaired manually, it will take much time and effort and the optimization space in the later design stage will be small.

At least in order to solve the above technical problems, some embodiments of the present application provide a method for efficiently solving cut metal physical short violation in batch on the premise of satisfying chip design function and performance, for example, in some embodiments of the present application, by analyzing the actual routing condition and the design rule in the digital layout (for example, using an Innovus or calibre tool to directly see the digital layout information, such as routing density condition and layout design rule (design rule based on process manufacturing requirement) violation condition, and the short-circuit defect is the most serious one of the layout design rule violation), it is determined whether the cut metal and other metal layers satisfy the layout design spacing requirement, the cut metal causing physical short circuit violation due to overlapping with other metal layers in the layout design is removed in batch, therefore, the repair time of the design rule violation is shortened, and the reliability of the chip design is improved. For example, bulk removal refers to the deletion of metal layers and cut metal layers that overlap on a target network on a layout.

It should be noted that, in some embodiments of the present application, the determination whether the layout design space requirement is satisfied between the cut metal and other metal layers, which is described in the above paragraph of applying the cut metal technology only on the M1 layer and the M2 layer, is to determine whether the distance between the cut metal layer and the cell port bottom layer metals M1 and M2 except for the cut metal itself satisfies the requirement. Since the related art often uses M1 and M2 layers to draw short lines near the cell ports (the cell pins are in the bottom M1 and M2 layers, the resistance of the bottom metal is too large, and the performance is degraded due to the long lines), the target type short circuit caused by cut metal is very easy to occur in these metal layers.

A method for correcting a short defect on a digital layout provided by some embodiments of the present application is illustratively described below in conjunction with fig. 3.

As shown in fig. 3, a method for correcting a short defect on a digital layout according to some embodiments of the present application includes: s101, acquiring a plurality of short-circuit defects existing in the digital layout; s102, if at least part of the short-circuit defects are determined to belong to a target type short circuit, taking an area where each short-circuit defect is located in the at least part of the short-circuit defects as a target processing area, wherein the target type short circuit belongs to the short-circuit defects caused by metal cutting processing, and the number of the target processing areas is one or more; s103, deleting the target object of the target processing area on the digital layout to obtain a target digital layout, wherein the target object is a metal layer causing short circuit of the target type.

That is, some embodiments of the present application reduce short rule violation repair time and improve chip design reliability by identifying all short defects present on a digital layout that are caused between a cut metal layer and a metal layer adjacent to the cut metal layer and deleting the metal layers that cause the short defects.

The following examples illustrate the implementation of the above steps.

In some embodiments of the present application, the acquiring, at S101, a plurality of short defects existing in the digital layout exemplarily includes: and checking a layout design rule of the digital layout to obtain the plurality of short-circuit defects, wherein each short-circuit defect in the plurality of short-circuit defects is represented by network information and metal level information respectively. Some embodiments of the present application may obtain all short defects present on a digital layout by performing layout design rule checking on the digital layout.

For example, in some embodiments of the present application, the obtaining of the plurality of short-circuit defects through layout design rule checking on the digital layout in S101 exemplarily includes: acquiring a process rule and the digital layout; and checking the digital layout design rule through electronic design automation software according to the process rule. Some embodiments of the present application identify all short defects present on a digital layout by process rules and electronic design automation software, namely EDA software.

It should be noted that, in some embodiments of the present application, the network information is used to characterize a network on the digital layout, and the metal layer information is used to characterize a metal layer where a trace connecting two ports is located. Some embodiments of the application record each short-circuit defect through network information and metal level information so as to obtain a target type short-circuit defect through traversing each short-circuit defect in the following and ensure that excessive deletion is not performed when a target object causing the short-circuit defect is deleted, thereby causing an open-circuit defect.

In some embodiments of the present application, S102 exemplarily comprises:

the method comprises the steps of firstly, judging whether any short-circuit defect in the plurality of short-circuit defects belongs to the target type short circuit or not, if so, marking any short-circuit defect to obtain a marked defect, and if not, skipping, wherein the marked defect belongs to one of at least part of short-circuit defects.

For example, the marking any short-circuit defect if the short-circuit defect belongs to the group of short-circuit defects includes: and marking any short-circuit defect in the marking area by using a marking characteristic. Some embodiments of the application mark each target processing region by using a specific marking feature in one region, thereby facilitating subsequent uniform selection of the differences and deletion operations.

And secondly, recording the position of the mark defect to obtain the target processing area corresponding to the mark defect.

It should be noted that, as the same example as the first step and the second step, the corresponding step S103 of deleting the target object in the target processing region on the digital layout exemplarily includes the following steps a and B:

and A, acquiring the characterization information of all the marking defects.

It should be noted that, in some embodiments of the present application, the characterization information includes: the network name is used for characterizing a target network with a short-circuit fault at the position, and the overlapped metal layer is used for characterizing a target metal layer causing the short-circuit fault in the target network. For example, the target network belongs to at least one of a clock network, a power network, and a signal network. The network of some embodiments of the present application includes various network types on the digital layout, improving the versatility of the technical solution.

And B, selecting the target object according to the characterization information, and deleting the cutting metal layer and the target object which are positioned in the target processing area from the digital layout. For example, the obtaining the target object according to the characterization information exemplarily includes: acquiring the target network; acquiring the target metal layer in the target network; taking the target metal layer as the target object; the deleting the cut metal layer and the target object located in the target processing area from the digital layout includes: and deleting the cutting metal layer and the target metal layer.

Some embodiments of the present application accurately determine metal layers involved in a target type short circuit through a network name and overlapping metal levels, and subsequently delete these metal layers to avoid the defect of open circuit problem in a digital layout due to inaccurate deletion. According to some embodiments of the application, the short circuit defects caused by cutting the metal layer can be deleted in batches subsequently in a mode of traversing and marking short circuits of all target types one by one.

In some embodiments of the present application, the deleting, at S102, the cut metal layer and the target object located in the target processing region from the digital layout exemplarily includes: and selecting the target metal layer and the cutting metal layer included in all the mark areas on the digital layout and deleting the target metal layer and the cutting metal layer. According to some embodiments of the application, the target type short circuit in the digital layout can be corrected by selecting and deleting the relevant metal layer in the mark region, and the problem of short circuit violation of the digital layout is solved.

In some embodiments of the present application, after deleting the target object in the target processing region on the digital layout to obtain a target digital layout S103, the method further includes: and carrying out design rule checking and winding processing on the target digital layout to determine whether the target digital layout further comprises the target type short circuit defect. Some embodiments of the present application also require that the revised layout be confirmed again to improve the short circuit violation problem of the finally obtained digital layout.

The method for correcting short defects on digital layouts provided by some embodiments of the present application is exemplarily described below with reference to fig. 4, in which cut matal is applied only to the bottom metal layers, i.e., the M1 metal layer and the M2 metal layer.

Referring to fig. 4, some embodiments of the present application provide a method for batch resolving cut metal short circuit violations (i.e., target type short circuits), which includes:

s201, obtaining all short circuit related network information and metal level information in the layout and determining.

For example, the network information and the metal level information related to the short circuit fault can be obtained through a design rule check tool.

S202, traversing the acquired network information and the acquired metal layer information.

S203, judging whether short circuit exists between the cut metal layer and the bottom metal of the unit port, if not, no design rule is violated and no processing is carried out, and if so, short circuit of the target type exists, and then S204 is continuously executed.

S204, determining and calibrating the short circuit position coordinate, the network name and the metal level between the cut mental and the unit port bottom metal.

The unit ports are input/output ports of the circuit unit, and some special macro-modules use higher-level outlet ports.

For example, the short-circuit position coordinates are the origin at the lower left corner of the chip, and x and y are horizontal and vertical, respectively, which is the inherent information in the layout.

For example, the network names include: clock network 1, power network 2, signal network 3, and clock network 2 …, it should be noted that the network names are unique throughout the design, and subsequently to determine the violating network.

For example, the metal level refers to which layer of metal trace is used to connect two ports, such as M1-M14, and subsequently also to determine whether a short circuit occurs specifically at M1 or M2.

S205, the overlapped part metal and the cut metal (the overlapped part metal and the cut metal layer are target objects) of the marking network in the area are selected for deletion.

For example, a metal layer and a cut metal layer with a specified network overlap in the mark area are selected (since the cut metal includes an overlapping metal part and a complete cut metal shape must be selected), and then deleted together.

And S206, carrying out design rule check and common winding processing on the short-circuit network, namely carrying out design rule check and common winding processing on the short-circuit network again.

It should be noted that, after the short circuit violation corresponding to the target type short circuit is eliminated, re-design rule verification is required to be performed to ensure that the short circuit violation is solved, and the winding is still a physical design process to avoid the open circuit violation caused by the false elimination.

S207, batch solving cut metal short circuit violation is completed.

That is, some embodiments of the present application provide a method for solving cut metal short circuit violation in batch, in which a physical design tool (e.g., an EDA tool) is used to obtain all network information and metal level information related to all short circuits (i.e., all short defects) in a layout, the short circuit information between the cut metal and a cell port bottom metal is screened out and marked, an overlapped metal and a cut metal layer (i.e., an overlapped metal and a cut metal layer, i.e., a target object) on a short circuit network in a marked region are selected to be deleted, and a re-design rule check and routing process are performed on the short circuit network (i.e., a target digital layout) to ensure the integrity of the network and the reliability of a chip, so that a physical design tool is used to analyze the whole chip layout and routing condition for subsequent processing.

As shown in fig. 5, the process of acquiring cut metal and bottom layer metal short circuit position and short circuit information in some embodiments of the present application includes:

it is determined whether there is a short circuit between the cut metal and the cell port underlying metal in the acquired short circuit information (i.e., all short circuit defects) (as an example of a target short circuit type). For example, the short circuit behavior and level can be determined directly using EDA tools.

Information of short circuit overlap between cut metal and cell port underlying metal is separately retained and marked.

And acquiring the position coordinates, the network name and the overlapped metal layer of the short circuit violation mark area.

To sum up, some embodiments of the present application provide a method for solving short circuit violation of cut metal in batches, which performs inspection on a design layout (for example, the design layout is inspected to be a technology of an existing tool, after reading in process rules and physical layout information, layout design rule inspection can be performed by using Innovus and calibre), first determines whether short circuit occurs between the cut metal and a bottom metal of a unit port and marks the short circuit, if not, skips over, if short circuit occurs, obtains coordinates, net names and overlapping metal layers of a short circuit violation mark region (combining the above description, it can be known that obtaining coordinates is for locating a short circuit position, obtaining net names and overlapping metal layers is for determining that only a net in the same position violates the metal layer, otherwise, it is likely to delete other nets or other connected metal layers in the position, thereby causing an open circuit), and finally, the metal of the overlapped part of the marked network in the area is selected and deleted, so that the problem of a large number of design short circuits can be solved in batch. The short circuit problem between cut metal and unit port bottom metal in the design layout is obtained and processed in batches, and the iteration period is shortened. For example, the method of some embodiments of the present application illustratively comprises: acquiring network information related to all short circuits (for example, acquiring all short circuit defects by using a backend physical design tool) in the layout (the network information refers to a connection relationship between the two, and has specific network names and types, such as a clock network 1, a power network 2, a signal network 3 and a clock network 2 …, the names are unique in the whole design, and are used for determining a network violation later) and metal level information (for example, the metal level refers to which layer of metal wires used for connecting two ports, such as M1-M14, and is used for determining whether a short circuit occurs in M1 or M2 later); traversing the acquired network information and metal level information, and executing the following four steps every time the short-circuit network and the metal level are traversed:

the method includes the steps of judging whether short circuit (namely a target short circuit type) between cut metal and unit port bottom metal exists in acquired short circuit information, and independently retaining (for example, marking short circuit areas in a layout) information of short circuit overlapping between the cut metal and the unit port bottom metal and marking (for example, the information can be independently framed and highlighted); and acquiring the position coordinates, the network name and the overlapped metal layer of the short circuit violation mark area.

And secondly, selecting the metal and cut-metal deletion of the overlapped part of the marked network in the region, namely, firstly selecting the metal layer and cut-metal layer overlapped by the designated network in the marked region (because the cut-metal comprises the overlapped metal part and a complete cut-metal shape is required to be selected), and then deleting the metal and cut-metal together.

Thirdly, design rule checking and common winding processing are carried out on the short-circuit network, design rule verification is carried out again after violation is solved, short-circuit violation is guaranteed to be solved, winding is still in a physical design process, and open-circuit violation caused by mistaken deletion is avoided.

And fourthly, solving the cut metal short circuit violation in batch.

The following illustrates an apparatus for correcting short defects on a digital layout according to some embodiments of the present application.

Referring to fig. 6, fig. 6 illustrates an apparatus for correcting a short-circuit defect on a digital layout according to an embodiment of the present application, and it should be understood that the apparatus corresponds to the embodiment of the method in fig. 3, and can perform the steps related to the embodiment of the method, and the specific functions of the apparatus may be referred to the description above, and a detailed description is appropriately omitted here to avoid redundancy. The device comprises at least one software functional module which can be stored in a memory in the form of software or firmware or solidified in an operating system of the device, and the device for correcting the short-circuit defect on the digital layout comprises: a plurality of short defect acquisition modules 101, a target processing area acquisition module 102, and a deletion module 103.

And the short-circuit defect acquisition modules 101 are used for acquiring a plurality of short-circuit defects existing in the digital layout.

A target processing area obtaining module 102, configured to determine that at least some of the short-circuit defects belong to a target type short circuit, and then use an area where each short-circuit defect of the at least some short-circuit defects is located as a target processing area, where the target type short circuit belongs to a short circuit caused by metal cutting processing, and the number of the target processing areas is one or more.

A deleting module 103 configured to delete the target object of the target processing region on the digital layout to obtain a target digital layout, wherein the target object is a metal layer causing a short circuit of the target type.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working process of the apparatus described above may refer to the corresponding process in the foregoing method, and will not be described in too much detail herein.

Some embodiments of the present application provide a chip manufacturing method, including: obtaining a plurality of masks according to the target digital layout according to any one of the embodiments; and manufacturing a chip according to the plurality of mask plates.

Some embodiments of the present application provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, may implement a method as described above in any of the embodiments of the method of fig. 3.

As shown in fig. 7, some embodiments of the present application provide an electronic device 500, the electronic device 500 illustratively comprises a memory 510, a processor 520, and a computer program stored on the memory 510 and executable on the processor 520, wherein the processor 520 may implement the method according to any of the embodiments described above when reading the program from the memory 510 via a bus 530 and executing the program.

Processor 520 may process digital signals and may include various computing structures. Such as a complex instruction set computer architecture, a structurally reduced instruction set computer architecture, or an architecture that implements a combination of instruction sets. In some examples, processor 520 may be a microprocessor.

Memory 510 may be used to store instructions that are executed by processor 520 or data related to the execution of the instructions. The instructions and/or data may include code for performing some or all of the functions of one or more of the modules described in embodiments of the application. The processor 520 of the disclosed embodiments may be used to execute instructions in the memory 510 to implement the method shown in fig. 3. Memory 510 includes dynamic random access memory, static random access memory, flash memory, optical memory, or other memory known to those skilled in the art.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Claims

1. A method for correcting short defects on a digital layout, the method comprising:

acquiring a plurality of short-circuit defects existing in the digital layout;

if at least part of the short-circuit defects are determined to belong to a target type short circuit, taking an area where each short-circuit defect is located in the at least part of the short-circuit defects as a target processing area, wherein the target type short circuit belongs to the short-circuit defects caused by metal cutting processing, and the number of the target processing areas is one or more;

and deleting the target object of the target processing area on the digital layout to obtain a target digital layout, wherein the target object is a metal layer causing short circuit of the target type.

2. The method of claim 1,

the acquiring of the plurality of short-circuit defects existing in the digital layout includes:

and checking a layout design rule of the digital layout to obtain the plurality of short-circuit defects, wherein each short-circuit defect in the plurality of short-circuit defects is represented by network information and metal level information respectively.

3. The method of claim 2, wherein said obtaining said plurality of short defects by performing a layout design rule check on said digital layout comprises:

acquiring a process rule and the digital layout;

checking the layout design rule of the digital layout through electronic design automation software according to the process rule.

4. The method of claim 2, wherein the network information is used to uniquely characterize a network on the digital layout, and the metal level information is used to characterize a metal layer on which a trace connecting two ports is located.

5. The method according to any one of claims 1 to 4, wherein confirming that at least some of the plurality of short defects belong to a target type short circuit, then regarding an area in which each short defect of the at least some short defects is located as a target processing area comprises:

judging whether any short-circuit defect in the plurality of short-circuit defects belongs to the target type short circuit or not, if so, marking any short-circuit defect to obtain a marked defect, and if not, skipping, wherein the marked defect belongs to one of at least part of short-circuit defects;

recording the position of the mark defect to obtain the target processing area corresponding to the mark defect;

the deleting the target object of the target processing area on the digital layout comprises:

acquiring the characterization information of all the mark defects;

selecting the target object according to the characterization information;

and deleting the cutting metal layer and the target object which are positioned in the target processing area from the digital layout.

6. The method of claim 5, wherein the characterization information comprises: a network name and an overlapping metal hierarchy, wherein the network name is used for characterizing a target network with a short-circuit fault at the position, and the overlapping metal hierarchy is used for characterizing a target metal layer causing the short-circuit fault in the target network;

wherein,

the obtaining the target object according to the characterization information includes:

acquiring the target network;

acquiring the target metal layer in the target network;

taking the target metal layer as the target object;

the deleting the cut metal layer and the target object located in the target processing area from the digital layout includes:

and deleting the cutting metal layer and the target metal layer.

7. The method of claim 6, wherein the target network belongs to at least one of a clock network, a power network, and a signal network.

8. The method of claim 5, wherein said marking any short defect if any, comprises: and marking any short-circuit defect in the marking area by using a marking characteristic.

9. The method of claim 8, wherein said removing the cut metal layer and the target object located at the target processing region from the digital layout comprises:

and selecting the target metal layer and the cutting metal layer included in all the mark areas on the digital layout and deleting the target metal layer and the cutting metal layer.

10. The method of claim 1, wherein after deleting the target object of the target processing region on the digital layout to obtain a target digital layout, the method further comprises:

and carrying out design rule checking and winding processing on the target digital layout to confirm whether the target digital layout further comprises the target type short circuit.

11. An apparatus for correcting short defects on a digital layout, the apparatus comprising:

the short-circuit defect acquisition modules are used for acquiring a plurality of short-circuit defects existing in the digital layout;

a target processing area obtaining module configured to determine that at least some of the plurality of short-circuit defects belong to a target type short circuit, and then use an area where each short-circuit defect of the at least some short-circuit defects is located as a target processing area, where the target type short circuit belongs to a short circuit caused by metal cutting processing, and the number of the target processing areas is one or more;

and the deleting module is configured to delete the target object of the target processing area on the digital layout to obtain a target digital layout, wherein the target object is a metal layer causing the target type short circuit.

12. A chip manufacturing method, characterized by comprising:

obtaining a plurality of masks according to the target digital layout according to any of claims 1-10;

and manufacturing a chip according to the plurality of mask plates.

13. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, is adapted to carry out the method of any one of claims 1 to 10 and 12.

14. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor when executing the program is operable to implement the method of any one of claims 1-10 and claim 12.