CN114817128A - Spaceborne computer system and its data receiving and sending method - Google Patents

Abstract

An on-board computer system, comprising: the satellite-borne microprocessor is used for data processing and whole satellite control; a data memory for storing payload data; and the coprocessor is electrically connected with the satellite-borne microprocessor and the data memory, is provided with a plurality of data receiving and transmitting channels and automatically stores and forwards the load data. The communication coprocessor is integrated in the general processor module, and the interface data management and control function of the on-board general processor is completed by the coprocessor, so that the working efficiency of the on-board general processor is improved, and meanwhile, the computing resources of an on-board platform are saved.

Description

Spaceborne computer system and its data receiving and sending method

technical field

The invention belongs to the technical field of satellite electronic equipment, and in particular relates to an on-board computer system and a data receiving and sending method thereof.

Background technique

With the rapid development of my country's aerospace industry, satellite business is gradually integrated into daily life. The demand for satellite networking services with global coverage is increasing. At the same time, various vertical industries have put forward higher requirements for on-board information processing time to meet the needs of market users. The traditional mode of single-satellite operation and ground control operation can no longer meet the needs of users. Therefore, the importance of researches such as enhancing space-based computing resources, reducing on-board processing time, and carrying out multi-satellite collaborative mission planning modes is self-evident.

In this context, the demand for data interaction between on-board stand-alone computers continues to increase. The satellite platform needs to be able to receive local and other satellite data, run multi-source data fusion and mission planning algorithms, and finally realize on-board intelligent autonomous and collaborative task scheduling planning and communication. , navigation, remote control telemetry, weather forecast, environmental monitoring and other fields of information networking to accelerate economic and social development.

However, on-board general-purpose processors not only need to complete data interaction management and control, but also need to process the received data, resulting in conflicts between data management and data processing resources, and cannot meet the requirements of high reliability and high efficiency.

SUMMARY OF THE INVENTION

In order to solve the above problems, the purpose of the present invention is to provide an on-board computer communication co-processor, which is integrated in a general-purpose processor module, and the interface data control function of the on-board general-purpose processor is handed over to the co-processor. It can improve the work efficiency of the general-purpose processor on the satellite and save the computing resources of the on-board platform.

For achieving the above object, the technical scheme of the present invention is:

An on-board computer system, comprising: an on-board microprocessor for data processing and whole satellite control; a data memory for storing payload data; a co-processor for working with the on-board microprocessor and the data The memory is electrically connected, and the coprocessor has a plurality of data transceiving channels and automatically stores and forwards the payload data.

In a possible embodiment of the present invention, the onboard computer system further includes a communication buffer, and the coprocessor is connected to the data storage through the communication buffer.

In a possible embodiment of the present invention, the coprocessor includes a plurality of data management channels, a multi-port interaction interface, and a controller, the data management channel is electrically connected to the data transceiver channel, and the multi-port interaction interface is connected to all The data management channel and the communication buffer are electrically connected, and the controller is configured to control the data management channel and the multi-port interaction interface to automatically store and/or forward the payload data according to a preset program.

In a possible embodiment of the present invention, the data management channel includes a data buffer module and a descriptor matching module, the data buffer module is electrically connected to the corresponding data transceiver channel, and the descriptor matching module is connected to the The data buffer module is electrically connected to the multi-port interactive interface.

In a possible embodiment of the present invention, the coprocessor further includes a configuration register, and the configuration register is electrically connected to the data management channel and the onboard microprocessor.

In a possible embodiment of the present invention, the communication buffer includes a plurality of descriptor arrays corresponding to the data management channels one-to-one, and the descriptor array is matched with the corresponding descriptor matching module and the communication buffer The corresponding channels are electrically connected.

In a possible embodiment of the present invention, the coprocessor adopts an FPGA chip whose model is Actel AX2000.

Based on the same concept, the present invention also provides a method for receiving payload data of an onboard computer system, comprising the following steps: when receiving external payload data, identifying a valid data frame header according to a data communication protocol, and after identifying the valid frame header, according to the data The packet format parses the data key information in the packet header; performs data type matching on the data key information in the parsed packet header; reads the remaining parameter information in the data key information, including the storage mechanism and storage address; based on the storage mechanism and The storage address forwards and/or stores the current payload data to a corresponding address.

Based on the same concept, the present invention also provides a method for sending payload data of an on-board computer system, comprising the steps of: configuring a descriptor array of a sending port; reading corresponding data from a buffer cache based on the length information of the configuration information of the descriptor array and sending it ;When the current frame to be sent is not the last frame of data, after sending the data of this frame according to the parameters in the descriptor array, poll the next descriptor array and complete the corresponding sending action; the current frame to be sent is the last frame of data , this transmission ends.

Based on the same concept, the present invention also provides a readable storage medium, where a processing program is stored on the readable storage medium, and when the processing program is executed by a processor, the above-mentioned method for receiving payload data of an on-board computer system or an on-board computer system is implemented. Computer system load data transmission method.

Compared with the prior art, the present invention has the following advantages and positive effects due to the adoption of the above technical solutions:

1. A dedicated communication co-processor is integrated in the onboard computer system, and the interface data management and control functions of the processor are completed by the co-processor, which improves the work efficiency of the processor, saves the computing resources of the on-board platform, and improves reliability. better and more efficient.

2. Due to the setting of the communication cache, the writing efficiency can be accelerated when the data is written into the data storage; the setting of the descriptor matching module can store the load data by classification, so that the files are stored in an orderly manner, which is convenient for subsequent searches.

Description of drawings

The specific embodiments of the present invention will be described in further detail below in conjunction with the accompanying drawings, wherein:

1 is a schematic diagram of an onboard computer system device of the present invention;

Fig. 2 is the flow chart of the method for receiving load data of the spaceborne computer system of the present invention;

FIG. 3 is a schematic diagram of the load data receiving principle of the on-board computer system of the present invention;

Fig. 4 is the flow chart of the method for receiving payload data of the on-board computer system of the present invention;

FIG. 5 is a schematic diagram of the principle of receiving data of the on-board computer system of the present invention.

Detailed ways

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become apparent from the following description and claims. It should be noted that, the accompanying drawings are all in a very simplified form and use imprecise ratios, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relationship between various components under a certain posture (as shown in the accompanying drawings). The relative positional relationship, the movement situation, etc., if the specific posture changes, the directional indication also changes accordingly.

first embodiment

As shown in FIG. 1, an embodiment of the present invention provides an on-board computer system, including: an on-board microprocessor for data processing and satellite control; a data memory for storing payload data; The onboard microprocessor is electrically connected to the data storage, and the coprocessor has a plurality of data transceiving channels and automatically stores and forwards the payload data.

A dedicated communication co-processor is integrated in the onboard computer system, and the interface data management and control functions of the processor are completed by the co-processor, which improves the working efficiency of the processor, saves the computing resources of the on-board platform, and has better reliability. higher efficiency.

In a possible embodiment of the present invention, the onboard computer system further includes a communication buffer, and the coprocessor is connected to the data storage through the communication buffer.

Since the communication buffer is set, the writing efficiency can be accelerated when writing data into the data memory; when reading the data in the data memory, the data in the communication buffer can be directly transferred to the memory. The speed of the communication buffer is much higher than the read and write speed of the magnetic head, so it can achieve the purpose of significantly improving the performance. Sometimes, some data needs to be accessed frequently. For example, the internal cache of the hard disk (a kind of scratchpad) will store some data that is read more frequently in the cache, and can be directly read from the cache when it is read again. direct transmission.

In a possible embodiment of the present invention, the coprocessor includes a plurality of data management channels, a multi-port interaction interface, and a controller, the data management channel is electrically connected to the data transceiver channel, and the multi-port interaction interface is connected to all the data transmission and reception channels. The data management channel and the communication buffer are electrically connected, and the controller is configured to control the data management channel and the multi-port interaction interface to automatically store and/or forward the payload data according to a preset program.

By setting the data management channel, the payload data can be classified and stored according to the data type, and the file rules can be stored, which is easy to read.

In a possible embodiment of the present invention, the data management channel includes a data buffer module and a descriptor matching module, the data buffer module is electrically connected to the corresponding data transceiver channel, and the descriptor matching module is connected to the The data buffer module is electrically connected to the multi-port interactive interface.

Through the data buffer module, the payload data is cached in the corresponding module, and the key data information in the packet header is parsed according to the data packet format, and after the descriptor matching module matches the payload data, the payload data is stored in the multi-port interactive interface. in the corresponding communication buffer.

In a possible embodiment of the present invention, the coprocessor further includes a configuration register, and the configuration register is electrically connected to the data management channel and the onboard microprocessor.

The configuration register is used to perform initial information configuration on the data buffer module and the descriptor matching module according to a preset program.

In a possible embodiment of the present invention, the communication buffer includes a plurality of descriptor arrays in one-to-one correspondence with the data management channels, and the descriptor array is matched with the corresponding descriptor matching module and the communication buffer The corresponding channels are electrically connected.

The descriptor array includes a plurality of descriptor modules for matching the data type of the payload data.

In a possible embodiment of the present invention, the coprocessor adopts an FPGA chip whose model is Actel AX2000.

Second Embodiment

As shown in FIG. 2 and FIG. 3 , the present invention also provides a method for receiving load data of an on-board computer system, comprising the following steps:

When receiving external payload data, identify the valid data frame header according to the data communication protocol, and after identifying the valid frame header, parse the data key information in the packet header according to the data packet format;

Match the data type of the data key information in the parsed packet header;

Read the remaining parameter information in the key information of the data, including the storage mechanism and storage address;

The current payload data is forwarded and/or stored to a corresponding address based on the storage mechanism and the storage address.

Specifically, each data management channel provides N "receive descriptors". Each receiving descriptor can specify information such as "APID matching condition", "packet start address (write pointer)", "buffer start address", "total buffer length", etc. The total length is 128 bits. After the receiving descriptor configuration is completed, the data management channel automatically matches the received packet and the receiving descriptor in parallel, and saves the data packet into the corresponding buffer. The onboard microprocessor only needs to periodically check the write pointer of the descriptor to know which packets have been received and deal with it accordingly. Specific steps are as follows:

(1) When the onboard computer system receives external data, the coprocessor identifies the valid data frame header according to the data communication protocol. After identifying the valid frame header, the coprocessor parses the data length and APID in the packet header according to the data packet format. information;

(2) Match the data type of the parsed header information with those located in the cache or all received descriptors. The descriptor configuration area is shown in the following table:

(3) APID matching conditions are as follows:

When {cond,neg}={0,0}, the matching mask plus matching target pattern: (APID&mask)==match, that is, after the APID is filtered by the mask, if it is consistent with the match, it is determined that the descriptor matches;

When {cond,neg}={1,0}, the minimum value plus the maximum value (in the interval) matching mode: (APID>=mask&&APID<=match) that is, when APID is within the mask to match interval set by the descriptor, it is determined match for the descriptor;

When {cond,neg}={0,1}, the matching mask plus matching target (filtering) mode: (APID&mask)! =match means that after the APID is filtered by the mask, if it is inconsistent with the match, it is determined that the descriptor matches;

When {cond,neg}={1,1}, the minimum value plus the maximum value (outside the interval) matching mode: (APID<mask||APID>mask) that is, when APID is outside the mask to match interval set by the descriptor, then It is determined that the descriptor matches;

(4) After matching the current data packet with a descriptor of the port through APID, further read the remaining parameter information in the descriptor, including storage mechanism, storage address, etc., as follows:

①Data storage address:

When the descriptor matching result is {mon,byp}={0,0} or when {mon,byp}={1,0}, the data packet needs to be stored in the RAM memory area. The base in the descriptor is the starting base address where the data of the communication port matches the current descriptor stored in the memory, and the idx is the offset address where the first byte of the data packet is stored, so the starting address of the current data packet is base+ idx. After the coprocessor detects the matching of the data packets, it automatically increases the idx value corresponding to this descriptor to the current data packet length, and the next matched data packets will be stored in the memory in turn.

②Data storage area:

The size in the descriptor indicates the size of the address space available for the data packet matched by the current descriptor to prevent data from being written to the wrong address. The starting address is base and the ending address is base+size. When the data packets whose descriptors match successfully are stored in sequence, and after they are stored to the end address, the write pointer loop is stored, and the next data loop is looped back to the base address to overwrite and write in sequence, and the idx value is automatically looped back.

(5) According to the address specified in the descriptor configuration area, the destination of storage and forwarding, etc., the storage and distribution of the received data is automatically realized.

Third Embodiment

As shown in FIG. 4 and FIG. 5 , the present invention also provides a method for sending load data of an on-board computer system, comprising the following steps:

Configure the descriptor array of the transmit port;

Based on the length information of the descriptor array configuration information, the corresponding data is read from the cache and sent;

When the current frame to be sent is not the last frame of data, after sending the data of this frame according to the parameters in the descriptor array, poll the next descriptor array and complete the corresponding sending action;

When the current frame to be sent is the last frame of data, the current sending ends.

Specifically, N "transmission descriptors" are provided for each communication transmission interface. Each sending descriptor can specify information such as "sending packet length", "packet start address (read pointer)", "buffer start address", "total buffer length", etc. The total length is 128 bits. By sending descriptors, the onboard microprocessor assigns up to 32 sending actions to the sending interface at a time, and sends 32 data packets from different buffer locations. After the sending is started, the sending interface automatically reads the sending descriptor in turn to complete the sending of the data packet without the intervention of the highly reliable processor.

The specific implementation steps are as follows: When the onboard computer system plans to send data, the onboard microprocessor first configures the sending descriptor array for the port, and the coprocessor implements the subsequent sending work. The configuration information of the sending descriptor that needs to be configured is shown in the following table. Show:

①Sending packet length:

Set len as the length of the sent data packet, and the coprocessor sending interface reads the corresponding data from the buffer and sends it according to the length information.

②Continuous sending mode:

The processor sets the descriptor last=0 or last=1 in turn. Last=0 means that the frame to be sent is not the last frame. After the coprocessor sends the data of this frame according to the parameters in the descriptor, it polls the next descriptor and completes it. Corresponding sending action, until polling to the last = 1 of the descriptor, it is regarded as the last frame of data, and this sending ends.

③Send start address

In the descriptor, base is the starting base address of the current descriptor corresponding to the sending data stored in the memory, and idx is the offset address where the first byte of the sending data packet is stored, so the starting address of the current data packet is base+idx. After the coprocessor specifies the sending port and the descriptor serial number, it sends the data in the communication buffer in turn according to the sending start address base+idx and length information len. When update=0, the idx value does not change after the data is sent, and the next data packet will be overwritten and stored in the current memory; when update=1, the idx value corresponding to this descriptor is automatically added to the current data packet length, and the next matching data Packages will be placed in memory sequentially.

④Data storage area

The size in the descriptor indicates the size of the address space available for the data packet matched by the current descriptor to prevent data from being written to the wrong address. The starting address is base and the ending address is base+size. The onboard microprocessor puts the data content to be sent in sequence, stores it to the end address, stores the write pointer loopback, loops back the next data to the base address and overwrites it in turn, and the idx value automatically loops back.

⑤Data error proofing mode

When single=1, the coprocessor does not discriminate the transmission content when sending, and when single=0, the coprocessor discriminates the data content of the starting address before sending, compares the preset data frame header, and starts searching from the preset starting address , start sending after finding a valid frame header, otherwise it will not send.

Fourth Embodiment

Based on the same concept, the present invention also provides a readable storage medium, where a processing program is stored on the readable storage medium, and when the processing program is executed by a processor, the above-mentioned method for receiving payload data of an on-board computer system or an on-board computer system is implemented. Computer system load data transmission method.

The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above-mentioned embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and the technical equivalents thereof, they still fall within the protection scope of the present invention.

Claims (10)

1. A space-borne computer system, comprising:

the satellite-borne microprocessor is used for data processing and whole satellite control;

a data memory for storing payload data;

and the coprocessor is electrically connected with the satellite-borne microprocessor and the data memory, is provided with a plurality of data receiving and transmitting channels and automatically stores and forwards the load data.

2. The on-board computer system of claim 1, further comprising a communication cache, the co-processor coupled to the data storage through the communication cache.

3. The on-board computer system of claim 2, wherein the coprocessor includes a plurality of data management channels, a multi-port interactive interface, and a controller, the data management channels are electrically connected to the data transceiving channels, the multi-port interactive interface is electrically connected to the data management channels and the communication cache, and the controller is configured to control the data management channels and the multi-port interactive interface to automatically store and/or forward payload data according to a preset program.

4. The on-board computer system of claim 3, wherein the data management channels comprise a data buffering module electrically connected to the corresponding data transceiving channels and a descriptor matching module electrically connected to the data buffering module and the multi-port interaction interface.

5. The on-board computer system of claim 3, wherein the co-processor further comprises a configuration register electrically connected to the data management channel and the on-board microprocessor.

6. The on-board computer system of claim 4, wherein the communication cache includes a plurality of descriptor arrays in one-to-one correspondence with the data management channels, the descriptor arrays being electrically connected to the corresponding descriptor matching modules and the corresponding channels of the communication cache.

7. The on-board computer system of any of claims 1-6, wherein the co-processor employs an FPGA chip of type ActelAX 2000.

8. A method for receiving load data of a satellite-borne computer system is characterized by comprising the following steps:

when receiving external load data, identifying an effective data frame header according to a data communication protocol, and after identifying the effective frame header, analyzing data key information in the packet header according to a data packet format;

performing data type matching on the analyzed data key information in the packet header;

reading the rest parameter information in the data key information, wherein the rest parameter information comprises a storage mechanism and a storage address;

and forwarding and/or storing the current load data to the corresponding address based on the storage mechanism and the storage address.

9. A method for sending payload data of a satellite-borne computer system is characterized by comprising the following steps:

configuring a descriptor array of a sending port;

reading corresponding data from the cache based on the length information of the descriptor array configuration information and sending the data;

when the current frame to be sent is not the last frame data, polling the next descriptor array and finishing the corresponding sending action after sending the current frame data according to the parameters in the descriptor array;

and when the current frame to be sent is the last frame data, the sending is finished.

10. A readable storage medium, characterized in that the readable storage medium has stored thereon a processing program, which when executed by a processor implements the method for receiving payload data of a satellite borne computer system according to claim 8 or the method for transmitting payload data of a satellite borne computer system according to claim 9.

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