CN114816566A - Instruction moving method, system, equipment and medium - Google Patents

Abstract

The invention discloses an instruction moving method, comprising the following steps: in response to receiving an IO request issued by a host, updating first pointer information in a corresponding task according to an address parameter of an instruction carried in the request; detecting each task Whether the first pointer information of The second flags of other tasks are in the set state, and the corresponding continuous instructions are moved according to the first pointer information; in response to the completion of the transfer of the continuous instructions, the set first and second flags are restored. The invention also discloses a system, a computer device and a readable storage medium. The solution proposed by the present invention can realize the transfer of continuous instructions, and has higher bus efficiency compared with the traditional single-instruction transfer, and in a program with good spatial locality, the performance is significantly improved.

Description

Instruction moving method, system, device and medium

technical field

The present invention relates to the field of data processing, in particular to an instruction moving method, system, device and storage medium.

Background technique

With the popularization of cloud computing and big data, computing and storage have increasingly become the key path restricting the development of computing technology. For a computing system, since both data calculation and movement are handled by the CPU, the CPU becomes an intermediate node. As the amount of system application data increases, the CPU load is getting higher and higher. In order to solve this problem, the data calculation is moved from the CPU to a dedicated processing unit, which greatly reduces the CPU load and greatly improves the efficiency. AEM (Acceleration Engine Management) is a device that transfers operations such as data calculation, and sends it back to the processing unit of the host after the calculation processing is completed.

As shown in Figure 1, traditional processing is scheduled by firmware. The firmware needs to obtain the instructions issued by the host, parse the instructions, and then transmit them to the corresponding computing processing unit for processing. After the hardware processing is completed, the firmware is notified to return the reply data to the host.

This processing method consumes too much CPU processing time and occupies CPU load. In order to relieve the load of the CPU, using the hardware accelerator card can transfer some data processing tasks of the CPU to the accelerator card for processing, which greatly relieves the pressure on the CPU. The processing method using AEM (Acceleration Engine Management) is shown in Figure 2. AEM (acceleration engine management) needs to move the instructions issued by the host to the local for processing. AEM removes the commands created by the host in turn, and then processes them. This processing method can only move one instruction at a time, the number of bus accesses is large, and the efficiency is low.

The single-instruction transfer method is relatively simple and easy to implement, but the efficiency is limited and the bus utilization rate is low. The host maintains a buffer and a set of doorbell registers. The Doorbell register is used to identify the pointer position of the buffer and notify the host of the execution status of the instruction. The register group is mainly composed of 3 registers: 1. Tail pointer: used to indicate the issuance of the instruction; 2. Head pointer: used to indicate the completion of the instruction. 3. Processing pointer: used to indicate the processing of hardware instructions. The specific execution process is as follows:

1. The host side sends the command, put the command in the storage space on the host side, and configure the doorbell register to notify AEM that there is a command to send. If the doorbell register is configured as 10, it means that there are 10 instructions to be executed on the host side.

2. AEM requests PCIE DMA (Direct Memory Access, direct memory access). Due to the single-instruction moving method, 10 operations are required to move 10 instructions, and 10 bus operations are initiated. The hardware maintains a processing pointer, which is updated every time a bus operation is initiated.

3. Wait for the command from the host side to be moved to the local storage space. The corresponding head pointer is updated after the bus responds and moves the command issued by the corresponding host side to the local. Finally, the consistent head and tail pointers indicate that all the instructions issued by the host have been moved by AEM.

Therefore, when 10 instructions issued by the host require 10 DMA operations, the number of bus accesses is 10, and the bus utilization rate is low.

SUMMARY OF THE INVENTION

In view of this, in order to overcome at least one aspect of the above problems, an embodiment of the present invention proposes a method for moving instructions, including the following steps:

In response to receiving the IO request issued by the host, update the first pointer information in the corresponding task according to the address parameter of the instruction carried in the request;

Detecting whether the first pointer information in each task reaches a preset value;

In response to detecting that the first pointer information reaches a preset value, set the first flag and the second flag of the corresponding task;

In response to detecting that the first flag is set and the second flag of no other task is currently in the set state, move the corresponding continuous instruction according to the first pointer information;

In response to the completion of the successive instruction transfer, the set first and second flags are restored.

In some embodiments, in response to receiving an IO request issued by the host, updating the first pointer information in the corresponding task according to the address parameter of the instruction carried in the request, further comprising:

Determine whether the first pointer information of the corresponding task is empty;

In response to being empty, the IO request delivery time is recorded and timed.

In some embodiments, the method further includes:

In response to the first pointer information in each task not reaching the preset value, determine whether there is a time-out task;

In response to the existence of a timed out task, the first flag and the second flag of the timed out task are set;

In response to detecting that the first flag is set and the second flag of no other task is currently in the set state, move the corresponding continuous instruction according to the current first pointer information of the timeout task;

The first and second flags that have been set by the time-out task are restored in response to the completion of successive instruction transfers.

In some embodiments, moving corresponding continuous instructions according to the first pointer information, further comprising:

Update the second pointer information according to the moved instruction;

In response to the second pointer information being the same as the first pointer information, it is determined that the corresponding continuous instruction transfer is completed.

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention also provides an instruction moving system, including:

The first update module is configured to update the first pointer information in the corresponding task according to the address parameter of the instruction carried in the request in response to receiving the IO request issued by the host;

a detection module, configured to detect whether the first pointer information in each task reaches a preset value;

a setting module, configured to set the first mark and the second mark of the corresponding task in response to detecting that the first pointer information reaches a preset value;

A moving module, configured to move the corresponding continuous instruction according to the first pointer information in response to detecting that the first mark is set and the second mark of no other task is currently in the set state;

The restoration module is configured to restore the set first flag and the second flag in response to the completion of the continuous instruction transfer.

In some embodiments, the first update module is further configured to:

Determine whether the first pointer information of the corresponding task is empty;

In response to being empty, the IO request delivery time is recorded and timed.

In some embodiments, it also includes a judgment module, configured as:

In response to the first pointer information in each task not reaching the preset value, determine whether there is a time-out task;

In response to the existence of a timed out task, the first flag and the second flag of the timed out task are set;

In response to detecting that the first flag is set and the second flag of no other task is currently in the set state, move the corresponding continuous instruction according to the current first pointer information of the timeout task;

The first and second flags that have been set by the time-out task are restored in response to the completion of successive instruction transfers.

In some embodiments, the moving module is further configured to:

Update the second pointer information according to the moved instruction;

In response to the second pointer information being the same as the first pointer information, it is determined that the corresponding continuous instruction transfer is completed.

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer device, including:

at least one processor; and

A memory, wherein the memory stores a computer program that can be executed on the processor, and is characterized in that, when the processor executes the program, the processor executes the steps of any one of the above-mentioned instruction moving methods.

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor Perform the steps of any of the instruction moving methods described above.

The present invention has one of the following beneficial technical effects: the solution proposed by the present invention can realize the transfer of continuous instructions, has higher bus efficiency compared with the traditional single-command transfer, and has obvious performance improvement in programs with good spatial locality.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other embodiments can also be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic diagram of a traditional data acceleration processing process;

2 is a schematic diagram of a processing method using an acceleration engine;

3 is a schematic flowchart of an instruction moving method provided by an embodiment of the present invention;

4 is an AEM hardware structure diagram provided by an embodiment of the present invention;

5 is a schematic diagram of a bus decoding module according to an embodiment of the present invention;

FIG. 6 provides a schematic diagram of a task creation module according to an embodiment of the present invention;

7 is a schematic diagram of a timeout processing module according to an embodiment of the present invention;

8 is a schematic diagram of an instruction fetch module according to an embodiment of the present invention;

9 is a schematic diagram of an instruction cache module provided by an embodiment of the present invention;

10 is a schematic structural diagram of an instruction moving system provided by an embodiment of the present invention;

11 is a schematic structural diagram of a computer device provided by an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of a computer-readable storage medium provided by an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention will be further described in detail below with reference to the specific embodiments and the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities with the same name but not the same or non-identical parameters. It can be seen that "first" and "second" It is only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention, and subsequent embodiments will not describe them one by one.

According to an aspect of the present invention, an embodiment of the present invention proposes an instruction moving method, as shown in FIG. 3 , which may include the steps:

S1, in response to receiving the IO request issued by the host, update the first pointer information in the corresponding task according to the address parameter of the instruction carried in the request;

S2, detecting whether the first pointer information in each task reaches a preset value;

S3, in response to detecting that the first pointer information reaches a preset value, set the first mark and the second mark of the corresponding task;

S4, in response to detecting that the first mark is set and the second mark of no other task is currently in the set state, move the corresponding continuous instruction according to the first pointer information;

S5, in response to the completion of the transfer of the continuous instruction, restore the set first flag and the second flag.

The solution proposed by the present invention can realize the transfer of continuous instructions, and has higher bus efficiency compared with the traditional single-instruction transfer, and in a program with good spatial locality, the performance is significantly improved.

In some embodiments, as shown in FIG. 4 , AEM (Acceleration Engine Manager, acceleration engine management) may include a bus decoder (bus decoder), a task generation module (task generation), an instruction fetcher (instruction fetcher), an instruction Cache module (instruction buffer), and timeout processing module (timeout ctrl). Compared with the single-instruction move mode, the move size of multiple instructions requires certain conditions to be executed. Due to the randomness of the tasks issued by the host, a timeout processing mechanism needs to be added for the transfer of multiple instructions, so as to prevent the tasks issued by the host from meeting the conditions and having no chance to be executed.

In some embodiments, as shown in FIG. 5 , the function of the bus decoding module is to parse the configured tail pointer and some configuration values required for hardware processing from the bus protocol according to the task issued by the host. At the same time, the value of the processing pointer and the head pointer of AEM are updated to the register. Notifies the host of the progress of the command's processing. The structure diagram of this module is shown in Figure 5: the configuration information required by AEM is obtained from the bus interface, different configuration information corresponds to different addresses, and the decoding logic is used to obtain the configuration information. Configuration information such as: type 3 pointer information, queue configuration information, and other configuration information. The mode select signal configures the read and write operations of the bus according to the source and timing of the information.

In some embodiments, in step S1, in response to receiving a request issued by the host to the IO, update the first pointer information in the corresponding task according to the address parameter of the instruction carried in the request. Specifically, as shown in FIG. 6 , The task creation module is used for assembling task moving information according to the configuration information issued by the host to be written into the instruction fetching module, and waiting for the instruction fetching module to process the instruction moving operation. This module can support multi-task processing. Each line of information represents the command issued by the host that needs to be moved. The command must be continuous on the host side. Discontinuous commands need to be split into multiple continuous commands for processing. This operation done by the host side. Among them, the task request flag indicates that the task to be moved is waiting to be executed, and there are two ways to set it: 1. The tail pointer is updated to a preset value; 2. There is a task timeout. The tail pointer and the processing pointer identify the processing progress of the AEM. The processing flag indicates that the moving operation of the task has not been completed, and a new processing request can only be initiated after the completion of the task.

It should be noted that the IO request issued by the host can be sent to the corresponding task in the task creation module through different channels in the bus decoding module, and the tail pointer information (first pointer information) in the corresponding task is updated. Each IO represents an independent instruction. By updating the tail pointer parameter, continuous instructions can be accumulated, so that after reaching the threshold, the address of the continuous instruction is determined according to the parameter corresponding to the tail pointer for moving.

The advantage of one-time transfer of multiple instructions is that for spatially continuous instructions, only one bus operation needs to be initiated to complete, and the efficiency of programs with good spatial locality is significantly improved. At the same time, since the queue of cached instructions is composed of RAM, a part of the hardware area can be well saved compared to the implementation of registers.

In some embodiments, in response to receiving an IO request issued by the host, updating the first pointer information in the corresponding task according to the address parameter of the instruction carried in the request, further comprising:

Determine whether the first pointer information of the corresponding task is empty;

In response to being empty, the IO request delivery time is recorded and timed.

Specifically, when the first pointer information in the task is empty, in order to prevent the task issued by the host from meeting the conditions for a long time and having no chance to execute, a timestamp is stamped according to the first received request, the timing starts, and the timeout judgment process is entered.

In some embodiments, the method further includes:

In response to the first pointer information in each task not reaching the preset value, determine whether there is a time-out task;

In response to the existence of a timed out task, the first flag and the second flag of the timed out task are set;

In response to detecting that the first flag is set and the second flag of no other task is currently in the set state, move the corresponding continuous instruction according to the current first pointer information of the timeout task;

The first and second flags that have been set by the time-out task are restored in response to the completion of successive instruction transfers.

Specifically, as shown in FIG. 7 , the timeout processing module is used to process the timeout request for dispatching instructions, because the moving operation of multiple instructions is dispatched by the host, and the instructions dispatched by the host are random. According to the specific scene, when encountering a scene with good spatial locality, the transfer of the instruction always meets the transfer conditions, and the transfer can be carried out normally. When encountering a scenario with poor spatial locality, the tasks dispatched by the host may be discontinuous, resulting in each process having only a sporadic move operation of one or two instructions. In this case, if the host has been unable to issue new commands that satisfy the moving conditions, sporadic tasks will not be processed. In this scenario, a timeout processing mechanism is required to ensure that the instructions that meet the moving conditions can be moved.

The timeout processing module consists of timer, comparator and timestamp buffer. The counter starts to work after power-on. When the module receives the task request sent by the host, it will cache the time stamp of the sending time. The comparator judges whether the delay of each task has timed out, and if it times out, the timed out task request will be dispatched to the task creation module for processing. Tasks that are processed normally will exit the timeout processing process.

According to the request flag (the first flag), it is judged whether there is a task to be processed. If the current process has an unfinished task, the position and size to be moved are calculated according to the configuration information. Determine whether the transfer meets the minimum threshold value of the transfer. If it is satisfied, and the second flag (processing flag) of no other task is currently in the set state, that is, there is no other task being processed, then the transfer information is written into the instruction fetch. module, waiting to be moved, and set the processing flag. If it is not satisfied, do nothing until a new moving task is issued or the task times out. For a task that has timed out, the request flag is set, and there is no need to judge whether the transfer threshold value is met, and all instructions are directly moved at one time. After the normal execution of the task is completed, the task that has been processed normally is exited from the timeout processing flow.

In some embodiments, S4, in response to detecting that the first flag is set and the second flag of no other task is currently in the set state, move the corresponding continuous instruction according to the first pointer information, specifically, as shown in FIG. 8 As shown, the instruction fetch module receives the task created by the task creation module, stores the transfer information, such as the base address of the transfer and the transfer length, etc., and requests the bus, sends the information to the bus, and performs the command transfer operation. The module consists of a RAM and a state machine. The RAM is used to store the transfer information, and the state machine is used to control the generation of bus data packets in a specified format. The data packets mainly include source address, destination address, transfer length, and other control information. After the bus request is issued, the state machine control logic updates the processing pointer, the processing flag, and deletes the time stamp information in the timeout processing module (the operation is completed normally without timeout). The external control module performs the DMA transfer operation according to the data packet analysis information.

In some embodiments, moving corresponding continuous instructions according to the first pointer information, further comprising:

Update the second pointer information according to the moved instruction;

In response to the second pointer information being the same as the first pointer information, it is determined that the corresponding continuous instruction transfer is completed.

Specifically, as shown in FIG. 9 , the instruction cache module mainly completes the cache of instructions and the update operation of the head pointer (second pointer). It is composed of RAM and control state machine. The control state machine updates the head pointer according to the number of received instructions, which is used to identify the instruction processing state of the AEM. At the same time, the module also packs some control information from the received command and sends it to the subsequent processing engine for processing.

Aiming at the problem of low moving efficiency of a single instruction, the present invention proposes a moving method of continuous multiple instructions. Using the locality of the program, a continuous instruction can be moved to the local, split and processed locally, and turned into a single instruction for operation. The purpose of this is to reduce the configuration frequency of the bus, and change the transmission that needs to be configured multiple times to be completed only once, so as to reduce the access frequency of the bus and improve the utilization rate of the bus.

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides an instruction moving system 400, as shown in FIG. 10, including:

The first update module 401 is configured to update the first pointer information in the corresponding task according to the address parameter of the instruction carried in the request in response to receiving the IO request issued by the host;

The detection module 402 is configured to detect whether the first pointer information in each task reaches a preset value;

The setting module 403 is configured to set the first flag and the second flag of the corresponding task in response to detecting that the first pointer information reaches a preset value;

The moving module 404 is configured to move the corresponding continuous instruction according to the first pointer information in response to detecting that the first mark is set and the second mark of no other task is currently in the set state;

The restoration module 405 is configured to restore the set first flag and the second flag in response to the completion of the continuous instruction transfer.

In some embodiments, the first update module 401 is further configured to:

Determine whether the first pointer information of the corresponding task is empty;

In response to being empty, the IO request delivery time is recorded and timed.

In some embodiments, it also includes a judgment module, configured as:

In response to the first pointer information in each task not reaching the preset value, determine whether there is a time-out task;

In response to the existence of a timed out task, the first flag and the second flag of the timed out task are set;

In response to detecting that the first flag is set and the second flag of no other task is currently in the set state, move the corresponding continuous instruction according to the current first pointer information of the timeout task;

The first and second flags that have been set by the time-out task are restored in response to the completion of successive instruction transfers.

In some embodiments, the moving module 404 is further configured to:

Update the second pointer information according to the moved instruction;

In response to the second pointer information being the same as the first pointer information, it is determined that the corresponding continuous instruction transfer is completed.

Based on the same inventive concept, according to another aspect of the present invention, as shown in FIG. 11 , an embodiment of the present invention further provides a computer device 501, including:

at least one processor 520; and

The memory 510, the memory 510 stores a computer program 511 that can be executed on the processor, and the processor 520 executes the steps of any one of the above instruction moving methods when executing the program.

Based on the same inventive concept, according to another aspect of the present invention, as shown in FIG. 12 , an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer When the program instructions 610 are executed by the processor, the steps of any of the above instruction moving methods are performed.

Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the process in the method of the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it may include the flow of the embodiments of the above-mentioned methods.

In addition, it should be understood that computer-readable storage media (eg, memory) herein can be volatile memory or non-volatile memory, or can include both volatile and non-volatile memory.

Those skilled in the art will also appreciate that the various exemplary logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends on the specific application and design constraints imposed on the overall system. Those skilled in the art may implement the functions in various ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The above are exemplary embodiments of the present disclosure, but it should be noted that various changes and modifications may be made without departing from the scope of the disclosure of the embodiments of the present invention as defined in the claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements disclosed in the embodiments of the present invention may be described or claimed in the singular, unless expressly limited to the singular, the plural may also be construed.

It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It will also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The above-mentioned embodiments of the present invention disclose the serial numbers of the embodiments only for description, and do not represent the advantages and disadvantages of the embodiments.

Those of ordinary skill in the art can understand that all or part of the steps of implementing the above embodiments can be completed by hardware, or can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. The storage medium can be a read-only memory, a magnetic disk or an optical disk, and the like.

Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is only exemplary, and is not intended to imply that the scope (including the claims) disclosed by the embodiments of the present invention is limited to these examples; under the idea of the embodiments of the present invention , the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention should be included within the protection scope of the embodiments of the present invention.

Claims (10)

1. a kind of instruction transfer method, is characterized in that, comprises the following steps: In response to receiving the IO request issued by the host, update the first pointer information in the corresponding task according to the address parameter of the instruction carried in the request; Detecting whether the first pointer information in each task reaches a preset value; In response to detecting that the first pointer information reaches a preset value, set the first flag and the second flag of the corresponding task; In response to detecting that the first flag is set and the second flag of no other task is currently in the set state, move the corresponding continuous instruction according to the first pointer information; In response to the completion of the successive instruction transfer, the set first and second flags are restored. 2. method as claimed in claim 1, is characterized in that, in response to receiving the host computer to send down to IO request, according to the address parameter of the instruction carried in the described request to update the first pointer information in the corresponding task, further comprises: Determine whether the first pointer information of the corresponding task is empty; In response to being empty, the IO request delivery time is recorded and timed. 3. The method of claim 2, wherein the method further comprises: In response to the first pointer information in each task not reaching the preset value, determine whether there is a time-out task; In response to the existence of a timed out task, the first flag and the second flag of the timed out task are set; In response to detecting that the first flag is set and the second flag of no other task is currently in the set state, move the corresponding continuous instruction according to the current first pointer information of the timeout task; The first and second flags that have been set by the time-out task are restored in response to the completion of successive instruction transfers. 4. The method of claim 1, wherein moving corresponding continuous instructions according to the first pointer information, further comprising: Update the second pointer information according to the moved instruction; In response to the second pointer information being the same as the first pointer information, it is determined that the corresponding continuous instruction transfer is completed. 5. An instruction transfer system, characterized in that, comprising: The first update module is configured to update the first pointer information in the corresponding task according to the address parameter of the instruction carried in the request in response to receiving the IO request issued by the host; a detection module, configured to detect whether the first pointer information in each task reaches a preset value; a setting module, configured to set the first mark and the second mark of the corresponding task in response to detecting that the first pointer information reaches a preset value; a moving module, configured to move the corresponding continuous instruction according to the first pointer information in response to detecting that the first mark is set and the second mark of no other task is currently in the set state; The restoration module is configured to restore the set first flag and the second flag in response to the completion of the continuous instruction transfer. 6. The system of claim 5, wherein the first update module is also configured as: Determine whether the first pointer information of the corresponding task is empty; In response to being empty, the IO request delivery time is recorded and timed. 7. The system of claim 6, further comprising a judgment module configured as: In response to the first pointer information in each task not reaching the preset value, determine whether there is a time-out task; In response to the existence of a timed out task, the first flag and the second flag of the timed out task are set; In response to detecting that the first flag is set and the second flag of no other task is currently in the set state, move the corresponding continuous instruction according to the current first pointer information of the timeout task; The first and second flags that have been set by the time-out task are restored in response to the completion of successive instruction transfers. 8. The system of claim 5, wherein the transfer module is further configured to: Update the second pointer information according to the moved instruction; In response to the second pointer information being the same as the first pointer information, it is determined that the corresponding continuous instruction transfer is completed. 9. A computer device comprising: at least one processor; and A memory, wherein the memory stores a computer program that can be executed on the processor, wherein the processor executes the steps of the method according to any one of claims 1-4 when the processor executes the program. 10. A computer-readable storage medium storing a computer program, characterized in that, when the computer program is executed by a processor, the method of any one of claims 1-4 is executed. step.

Images