CN114815958B - High-capacity cascading electro-optical full adder/subtractor chip - Google Patents
High-capacity cascading electro-optical full adder/subtractor chip Download PDFInfo
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Abstract
The invention discloses a high-capacity cascading electro-optical full adder chip, belonging to the field of integrated optical calculation. The system comprises an addend A loading area, a first linear operation area, an addend B loading area, a second linear operation area and an auxiliary light path. The adder A loading area and the first linear operation area are used for realizing logical operation of exclusive OR and AND of the carry optical signal and the adder A electric signal. The loading area of the addend B and the second linear operation area are used for realizing the logical operation of the exclusive-or optical signal obtained by the carry signal and the addend A and the exclusive-or sum of the electric signal of the addend B. The above structure is combined with an auxiliary optical path to realize a full adder. The invention has the capability of cascade expansion to higher bit number adders. Moreover, the full-bridge dimmer can be realized by utilizing the original optical structure. In addition, the invention can introduce a wavelength division multiplexing technology to realize multi-wavelength parallel computation, so that the total operation rate of the chip reaches the Tbit/s magnitude, and can also utilize the parallelism of the wavelength to realize a carry selection adder with higher bit number on the structure of the low bit full adder.
Description
Technical Field
The invention belongs to the field of integrated optical computing, and particularly relates to a high-capacity cascading electro-optical full adder/subtractor chip.
Background
With the large-scale application of artificial intelligence and the rapid development of 5G technology, the data processing demands of various industries are increasing. However, as a basic unit of digital logic computation, the size and performance of the electronic computing transistor are difficult to be obviously improved, and the increasing data processing capacity is difficult to meet. Light has the characteristics of ultra-large bandwidth, ultra-high frequency and low power consumption, and photons have multiple dimensions, so that data can be processed in parallel, which makes optical digital computation one of the very competitive alternatives for data processing.
The existing optical adders are divided into an all-optical adder and an electro-optical adder, the all-optical adder can generate huge energy loss due to nonlinear effect and is generally limited to a half adder or a single-bit all adder, and the adder with higher bit number is difficult to realize. While the electro-optical adder has small power consumption of logic operation, because exclusive-or logic is difficult to realize through a simple optical path, a plurality of modulators are usually required to load the same signal together by the adder, and the expansion of the adder to high bit is limited by the number of the modulators and the complex optical path. And the existing all-optical and electro-optical adders are difficult to introduce wavelength division multiplexing and other technologies to realize parallel operation, so that the operation speed is difficult to be greatly improved. Therefore, the development of the high-capacity cascading electro-optical full adder/subtractor chip which introduces the wavelength division multiplexing technology to realize parallel high-speed calculation and has the capability of expanding to n bits has very important significance.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a high-capacity cascading electro-optical full-add/subtract chip and aims to realize full-add/full-subtract electro-optical logic operation which can be expanded to high bit numbers.
In order to achieve the above object, the present invention provides a high-capacity cascading electro-optical full adder chip, which includes adders cascaded, each stage of adders including an addend A loading area, a first linear operation area, an addend B loading area, a second linear operation area and related auxiliary light paths; the input of the addition A loading area is an electric signal containing continuous light of a plurality of wavelengths, a carry light signal C n-1 of a previous-stage adder and an addition A, and the electric signal is output as 3 channels; the input of the first linear operation area is 3 output channels of the addition A loading area, and the output is a logic optical signal result of exclusive OR and AND of a carry signal C n-1 and the addition A; the input of the loading area of the addend B is a logic optical signal which comprises continuous light with a plurality of wavelengths and is subjected to exclusive OR operation by the carry signal C n-1 output by the first linear operation area and the addend A, and an electric signal of the addend B, and the output of the logic optical signal is 3 channels; the input of the second linear region is three output channels of the loading region of the addition number B, and the output is the sum operation result S of the full adderThe logic optical signal result obtained by summing the carry signal C n-1 and the addition A output by the first linear operation region is output by the fourteenth channel in the auxiliary optical path and the second linear regionThe logic optical signal of (2) is input to the fifth MMI 3dB combiner through the thirteenth channel in the auxiliary optical path, and then the carry signal C n is output.
The addend A loading area and the first linear operation area together form a Logic Unit (LU) for performing exclusive OR and AND Logic operation on the carry signal C n-1 and the addend A, and outputting the result in the form of optical signals from a seventh channel and an eighth channel of the first linear operation area respectively; the adder B loading area and the second linear operation area together form an LU for outputting to the previous LUExclusive or and logical operation is performed on the optical signal and the addend B. Finally, combining with the auxiliary light path to realize the summation resultAnd carry signal And output in the form of an optical signal.
Further, the addend a loading area includes a second MMI 3dB optical splitter, N electro-optical modulators, a fourth channel, a fifth channel, and a sixth channel, where the carry signal C n-1 is input to the second MMI 3dB optical splitter via the second channel in the auxiliary optical path, split into the fifth channel and the sixth channel, and the continuous light is input to the fourth channel via the first channel in the auxiliary optical path and then split out by the first MMI 3dB optical splitter in the auxiliary optical path. The input of the electro-optical modulator is an electric signal A, which is used for modulating a fourth channel and a fifth channel simultaneously, and the electric signal A is loaded on an optical domain, and meanwhile, carry optical signal C n-1 and the electric signal A are subjected to logical AND operation, so that after the carry optical signal C n-1 and the electric signal A pass through an addition A loading area, the carry optical signal C n-1 and the electric signal A are mapped into a three-dimensional space from the two-dimensional space, and the subsequent logical operation of exclusive OR and AND can be realized only through linear operation.
Further, the first linear operation area includes a first MZI, a second MZI, a third MZI, a first MMI 3dB combiner, a second MMI 3dB combiner, a seventh channel, an eighth channel and a first cross waveguide, where the first MZI is connected with the fourth channel and outputs signals from the upper trailing arm, the second MZI is connected with the fifth channel, the signals output from the upper trailing arm and the output from the first MZI are combined by the first MMI 3dB combiner, the signals output from the lower trailing arm are input into the fourteenth channel after passing through the eighth channel and the first cross waveguide, the third MZI is connected with the sixth channel and outputs signals from the upper trailing arm, the output signals are combined by the first cross waveguide and input into the second MMI 3dB combiner and the signals output from the first MMI 3dB combiner, and the result of the obtained exclusive or logical operation is input into the seventh channel, and the first linear operation area is used for performing the exclusive or and the result obtained from the seventh channel and the result of the obtained exclusive or logical operation.
Further, the addend B loading area comprises a third MMI 3dB optical splitter, an electro-optical modulator, a ninth channel, a tenth channel and an eleventh channel, and inputs optical signalsThe continuous light enters a tenth channel and an eleventh channel after being split by a seventh channel to a third MMI 3dB optical splitter, and the continuous light enters the third channel and then enters a ninth channel by a first channel in an auxiliary optical path and an upper branch which is split by the MMI 3dB optical splitter in the auxiliary optical path. The input of the electro-optic modulator is an electrical signal B for modulating the ninth channel and the tenth channel simultaneously, and the electrical signal B is loaded on the optical domain and the optical signal is inputAnd the electric signal B, thereby inputting the optical signalAnd after the electric signal B passes through an addend B loading area, the electric signal B is mapped from the two-dimensional space to the three-dimensional space in a nonlinear manner.
Further, the second linear operation region includes a fourth MZI, a fifth MZI, a sixth MZI, a third MMI 3dB combiner, a fourth MMI 3dB combiner, a twelfth channel, a thirteenth channel, and a second cross waveguide, where the fourth MZI is connected to the ninth channel and outputs a signal from the upper back arm thereof, the fifth MZI is connected to the tenth channel, the output of the upper back arm thereof and the output of the fourth MZI are combined by the third MMI 3dB combiner, the signal of the lower back arm thereof is input to the fifth MMI 3dB combiner through the thirteenth channel and the second cross waveguide, the sixth MZI is connected to the eleventh channel and outputs a signal from the upper back arm thereof, the output signal is input to the fourth MMI 3dB combiner and the signal of the third MMI 3dB combiner through the second cross waveguide and the result of the obtained exclusive or logical operation is input to the twelfth channel, and the obtained exclusive or logical operation region is input to the twelfth channel and the obtained exclusive or logical operation region.
Further, the electro-optic modulator is a carrier injection type micro-ring modulator, the modulation rate is 40GHz, and the 3dB bandwidth of the resonance peak is 0.2nm. The N electro-optical modulators are coupled in sequence, and the resonant wavelengths lambda 1、λ2···λN of the N electro-optical modulators respectively correspond to the wavelength lambda 1、λ2···λN of the carry optical signal C n-1.
Further, by adjusting the voltage applied to the MZI thermal electrode, the MZI can be made to complete the linear arithmetic operation of the target.
Further, the bandwidths of the first linear operation region and the second linear operation region are at least 10nm. According to the characteristic that the MZI is a broadband device and the electro-optical modulator is a narrow-band device, a plurality of electro-optical modulators can be introduced, and wavelength division multiplexing is realized, so that multi-wavelength parallel operation is realized. In theory, the 3dB bandwidth of the MZI divided by the width of the micro-ring resonance peak can be introduced, in practice, the 3dB bandwidths of the first linear operation region and the second linear operation region are at least 10nm, and the 3dB bandwidth of the micro-ring resonance peak is 0.2nm, so that at least 50 wavelengths can be introduced, that is, 50 electro-optical modulators can be introduced in the nonlinear mapping region, and parallel operation is performed on 50 wavelengths.
Further, after the wavelength division multiplexing, the total operation rate of the chip is the modulation rate of a single electro-optical modulator multiplied by the introduced wavelength number, and the total operation rate can reach 2Tbit/s.
Furthermore, because the input and output carry signals of the high-capacity cascading electro-optical full adder are optical signals, the cascading electro-optical full adder can be expanded to higher bit positions in a cascading mode.
Further, by changing the signal loading rule of the addend B, the electric signal B is loaded on the light to becomeAnd the final summation result is output and then connected with an inverter of an electric domain or introduced with a coherent direct current bias light, thereby realizing the function of a subtracter without influencing the cascade property of the subtracter.
Furthermore, the parallelism of the wavelength can be utilized, and the carry selection adder with higher bit number can be realized based on the structure of a single bit or multi-bit full adder.
Further, all devices adopted by the high-capacity cascading electro-optic full adder/subtractor chip are developed by a silicon-based process platform which is mature at present, and the high-capacity cascading electro-optic full adder/subtractor chip has the potential of large-scale application.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. The high-capacity cascading electro-optical full adder/subtractor chip provided by the invention can be used for mapping signals from two-dimensional nonlinearity to three-dimensional nonlinearity in a modulation mode of an electro-optical modulator, and is combined with a simple MZI network to realize the logic of exclusive OR and AND of a nonlinearity domain;
2. the high-capacity cascading electro-optical full adder/subtractor chip provided by the invention has cascading property because the carry signals of the full adder are input and output in the form of light, and has a space expanded to an n-bit full adder;
3. the high-capacity cascading electro-optical full adder/subtractor chip provided by the invention can be switched from a full adder to a full subtractor under the condition of keeping the original optical structure unchanged by some simple changes;
4. The high-capacity cascading electro-optical full adder/subtractor chip provided by the invention can realize multi-wavelength parallel operation by introducing a wavelength division multiplexing technology, and can also realize a carry selection adder with higher bit number based on the structure of a single bit or multi-bit full adder by utilizing the parallelism of wavelengths.
5. All devices adopted by the high-capacity cascading electro-optical full adder/subtractor chip provided by the invention are developed by a silicon-based process platform which is mature at present, are compatible with a common commercial process, can realize arbitrary logic, have strong universality, have the capability of cascading and expanding, and have the potential of large-scale application.
Drawings
FIG. 1 is a schematic diagram of a high-capacity cascading electro-optic full adder chip provided by the invention;
FIG. 2 is a schematic diagram of a high-capacity cascade-able electro-optic full-adder chip implementation carry select adder provided by the present invention, (a) a schematic diagram of a carry select adder architecture; (b) a schematic of the operation of the carry select adder; (c) The transmission spectrum of the electro-optic modulator under different logic voltage signals;
FIG. 3 is a functional schematic of a high-capacity cascading electro-optic full-adder chip provided by the present invention, (a) is a functional schematic of a full-adder; (b) is a functional schematic of a full-dimmer;
FIG. 4 is a waveform diagram of the input and output results of a large-capacity cascadable electro-optic full-adder chip implementation of (a) a full adder and (b) a full subtractor provided by an example of the present invention;
FIG. 5 is a schematic diagram of a cascading model of a high-capacity cascading electro-optic full-adder chip provided by the invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not interfere with each other.
As shown in fig. 1, the cascadable high-capacity electro-optical full adder chip of the embodiment of the present invention, taking one-stage adder as an example, includes an addend a loading area 1, a first linear operation area 2, an addend B loading area 3, a second linear operation area 4, and an associated auxiliary optical path.
The reference continuous light with the wavelength lambda 1、λ2……λN is input from the first channel 201, split by the first MMI3dB splitter 51, one path is input to the adder A loading area 1, and the other path is input to the adder B loading area 3 through the third channel 203. Carry signal light including wavelength lambda 1、λ2……λN From the second channel 202 to the addend a loading section 1.
The addend a loading section 1 comprises the second MMI 3dB splitter 52, the fourth channel 204, the fifth channel 205, the sixth channel 206 and the electro-optical modulator 11 … … N. After the carry signal C n-1 is split by the MMI 3dB splitter, one path of the carry signal C n-1 is directly input to the first linear operation region 2 through the sixth channel 206, and the other path of the carry signal C n-1 and the input reference continuous light are respectively input to the lower end and the upper end of the electro-optical modulator through the fifth channel 205 and the fourth channel 204, and are modulated together. Without loss of generality, here it is specified that light intensity transmittance is greater than-10 dB at logic 1 and less than-20 dB at logic 0. As shown in fig. 2 (c), the resonant peak of the electro-optic modulator 11 is located at λ 1, i.e. light having a wavelength of λ 1 cannot pass through the electro-optic modulator. By varying the voltage applied to the electrodes of the electro-optic modulator 11, the resonance peak is shifted by λ 1 to λ' 1, so that λ 1 can pass through the electro-optic modulator. Here, it is specified that the voltage signal a 1 applied to the electro-optical modulator 11 has a resonance peak at λ 1 as a logic 0, and that the voltage signal a 1 applied to the electro-optical modulator 11 has a resonance peak at λ' 1 as a logic 1 (the same applies to the rest of the electro-optical modulators). For the fourth channel 204, when the electrical signal a 1 is 0, λ 1 is the resonant wavelength, and as can be seen from (c) in fig. 2, the transmitted light intensity of λ 1 is less than-20 dB, and the modulated optical signal a 1 is logic 0; when a 1 is 1, the light with wavelength lambda 1 can be transmitted, and as can be seen from fig. 2 (c), the transmitted light intensity of lambda 1 is greater than-10 dB, and the modulated optical signal a 1 is logic 1, so as to satisfy the definition of logic 0 and 1 of the optical signal. And for the fifth channel 205 only whenIn the case where A 1 is simultaneously logic 1, the output light intensity is greater than-10 dB, i.e., the final output signal of the fifth channel 205 isFor carry signalAnd addend A 1, which share four different combinations as shown in Table 1:
TABLE 1
After passing through the electro-optic modulator, the logical optical signals corresponding to each waveguide are shown in table 2 below:
TABLE 2
A 1 andAfter the signal passes through the electro-optical modulator, the signal input into the first linear operation area 2 is mapped from the original two-dimensional space to three-dimensional space in a nonlinear manner due to the AND logic operation performed at the fifth channel 205, so that the first linear operation area 2 can realize nonlinear exclusive OR logic only by performing linear operation processing.
The first linear region 2 comprises a first MZI21, a second MZI22, a third MZI23, a first MMI 3dB combiner 53, a second MMI 3dB combiner 54, and seventh and eighth channels 207, 208. The signal output by the seventh channel 207 is the sum of the outputs from the upper ends of the first MZI21, the second MZI22, and the third MZI23, and the signal output by the eighth channel 208 is the output from the lower end of the MZI 22. The complex amplitude specific mathematical expression is respectively as follows:
As can be seen from the above expression, the seventh channel 207 is output as exclusive or logic, and the eighth channel 208 is output as and logic. Here, the optical transmittance coefficient of each output port of the MZI is changed by adjusting the phase shifter of the inner arm of the MZI, and the positive or negative of the phase shifter change coefficient of the corresponding output outer arm of the MZI is adjusted. The linear addition function is realized by combining light by the first MMI 3dB light combiner 53 and the second MMI 3dB light combiner 54. Because the output signals of the upper and lower ends of the second MZI22 must satisfy the energy distribution relationship, i.e. the sum of squares of the complex amplitude modes of the output signals of the upper and lower ends is 1, the light transmittance coefficients of the upper and lower ends of the MZI22 are respectively set to AndIt should be noted that, here, only the combination of the loading area 1 and the first linear operation area 2 by the addend a is described to realize the logical operation of the exclusive or and the sum, because the subsequent cascade of multiple stages is also required, the balancing relation of the level of the subsequent logic output is related, and for the actual chip, there are factors such as process errors, etc., the transmittance of each MZI will be different from that in the above formula, but by adjusting the phase shifter of the MZI, the output still can reach the target logic level.
As is apparent from the above description, the loading area 1 of the addend a and the first linear operation area 2 together implement the logical operation of the exclusive or and of the carry signal C n-1 and the addend a, which constitute the logical unit LU shown in (a) of fig. 3, and the full adder can be implemented by combining the two LU into the auxiliary optical path. Wherein the second LU corresponds to the addend B loading section 3 and the second linear operation section 4 in fig. 1.
The following lists the summation result S and carry signal C n in the full adder with the input carry signal C n-1, logical truth table 3 and table 4 of the addend A, B, respectively, and the timing waveform relationship is shown in fig. 4 (a). C n-1 A andThe two signals are not 1 at the same time, so that the problem that the two signals have higher level after beam combination is avoided, the output carry signal C n still has only two levels, and the carry signal C n can be input into an adder of the next stage for operation. So that one or logical operation can be achieved using the fifth MMI3dB combiner 58 in fig. 1.
TABLE 3 summation result S logic truth table
Table 4 carry signal C n logic truth table
As can be seen from FIG. 3 (b), the difference between the full adder and the full subtractor is above the carry/borrow signal C n output, and the former LU output logic is unchanged, except that the latter LU is implementedHere, by changing the logical loading setting of the electro-optic modulator in the loading area 3 of the addend B, it is provided that the voltage signal B 1 applied to the electro-optic modulator 31 causes the resonance peak to be at λ 1 to be a logical 1 for the electro-optic modulator 31 and that the voltage signal B 1 applied to the electro-optic modulator 11 causes the resonance peak to be at λ' 1 to be a logical 0 (as in the electro-optic modulator 32-3N, as in the previous setting), which corresponds to the loading beingA signal. And the difference result D output at this time is And should originally outputJust in the inverse relation, the correct difference result D output can be realized by supplementing an inverter of an electric domain at the output end of the original summation result S or introducing a coherent direct current bias light.
The difference D and borrow signals C n and C n-1 of the total subtracter and the input borrow signal C n-1, the reduction a, the logic truth tables 5 and 6 of the reduced number B are shown below, and the time-series waveform relationship is shown in fig. 4 (B).
TABLE 5 Difference result D logic truth table
Table 6 borrow signal C n logic truth table
The above is given a method of implementing a single bit full adder and full subtractor by the structure of fig. 1, respectively, and the carry/borrow signal output therefrom can be directly input to the next stage for operation. Based on the above structure, the single bit Quan Jia/full-adder can be extended to the n bit full-adder shown in fig. 5. In addition, since the MZI is a broadband device and the micro-ring is a narrow-band device, N micro-rings can be subjected to signal modulation simultaneously, namely N groups of addends can be subjected to addition operation simultaneously, the modulation rate of a single electro-optical modulator can reach 40GHz, and the total operation rate of an N-bit full adder after wavelength division multiplexing can reach 40 XN GHz. Thereby realizing a large-capacity cascading full adder.
Also, the parallelism of the wavelength is utilized to realize a carry selection adder with higher bit number based on the structure of a single bit or multi-bit full adder. As shown in fig. 2 (a), the basic structural unit of the carry select adder is identical to the adder described above, except that the input wavelength and the loading signal are changed. It is provided here that the addends involved in the summation add up to N bits, the number of wavelengths input is 2N, 2N < N (the total number of wavelengths that can be multiplexed by the system) is satisfied, and the wavelengths lambda m and lambda m+n (0<m < N) differ by the FSR (FREE SPECTRAL RANGE ) of the electro-optic modulator. Thus, taking wavelength λ 1 as an example, as shown in fig. 2 (c), when the resonance peak of the electro-optical modulator shifts from λ 1 to position λ '1, wavelength λ n+1 of one FSR will also shift to λ' n+1, and when an electrical signal is loaded according to the initially prescribed logic signal loading mode, one micro-ring can modulate two wavelengths (λ m and λ m+n) simultaneously. As shown in fig. 2 (a), wavelengths from λ 1 to λ 2n are input at the input of continuous light for subsequent loading and modulation of the electrical signal; only wavelengths from λ 1 to λ n are input at the input carry signal, in this way, a case where the carry signal is 1 can be represented, and a case where the carry signal is 0 can be represented for wavelengths from λ n+1 to λ 2n that are not input at the carry signal. Taking the output wavelengths lambda 1 and lambda n+1 as examples, the first bits A 1 and B 1 in the represented addends A and B are obtained by adding when the carry signals are 1 and 0 respectively. The same applies to other bits to obtain two results when the carry signal is 1 and 0, respectively. After the output signal passes through WDM (WAVELENGTH DIVISION MULTIPLEXING, wavelength division multiplexing system), each group of corresponding wavelengths (λ m and λ m+n) are detected respectively, and then the output result of each stage and the carry signal are selected step by step according to the actual carry signal C 0, so as to obtain the addition operation output result of two n bit binary numbers. Meanwhile, a cascading mode can be combined with the method, and a carry selection adder which is expanded to n multiplied by k bits is realized by inputting 2n wavelengths on an adder which is cascaded to k bits.
The invention provides a high-capacity cascading electro-optical full adder/subtractor chip, which can realize the nonlinear logic operation of exclusive or sum and sum by mapping signals from two-dimensional nonlinearity to three-dimensional nonlinearity and combining a simple MZI network, and is constructed on the basis. The carry signals of the full adder are input and output in an optical form, so that cascade connection is realized, and the space for expanding the full adder to the n bit is provided. And by some simple changes can be switched from full adder to full subtractor. In addition, a narrow-band micro-ring electro-optic modulator is combined with a wide-band MZI array, so that a wavelength division multiplexing technology is introduced, on one hand, multi-wavelength parallel operation can be realized, and the total operation rate can reach Tbit/s magnitude; on the other hand, the parallelism of the wavelength can be utilized, and the carry selection adder with higher bit number can be realized based on the structure of the single bit or multi-bit full adder.
It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (6)
1. The high-capacity cascading electro-optical full adder chip is characterized by comprising cascading adders, wherein each level of adder comprises an addend A loading area (1), a first linear operation area (2), an addend B loading area (3), a second linear operation area (4) and other related auxiliary light paths for providing light path connection; the input of the addition A loading area (1) is a carry light signal containing continuous light of a plurality of wavelengths and a previous adderAnd an electric signal of the addition number A, and outputting the electric signal as 3 channels; the input of the first linear operation area (2) is 3 output channels of the addition A loading area (1), and the output is a carry signalThe sum of the sum and the addition number A is exclusive or and logical optical signal result; the input of the adder B loading area (3) is a carry signal/>, which comprises continuous light with a plurality of wavelengths and is output by the first linear operation area (2)The logic optical signal which performs exclusive OR operation with the addend A and the electric signal of the addend B are output as 3 channels; the input of the second linear region (4) is three output channels of the adder B loading region (3), and the output is the sum operation result S of the full adder and (/ >)An optical signal of A) and B; carry signal output by the first linear operation region (2)And the logical optical signal result summed with the addend A is outputted (/ >) through a fourteenth channel (214) and a second linear region (4) in the auxiliary optical pathAfter the logic optical signals of A) and B are input into a fifth MMI 3dB optical combiner (58) to be combined through a thirteenth channel (213) in the auxiliary optical path, carry optical signals are output; Wherein n represents an nth bit;
The adder A loading area (1) and the first linear operation area (2) form a first stage logic unit together and are used for carrying signals Exclusive or and logical operation is performed on the sum of the sum numbers a, and the result is output from a seventh channel (207) and an eighth channel (208) of the first linear operation region (2) in the form of optical signals, respectively; the addition B loading area (3) and the second linear operation area (4) form a second stage logic unit together and are used for outputting/>, of the previous stage logic unitThe optical signal of (A) and the addend B are subjected to exclusive OR and AND logic operation, and finally the summation result S=/>, which is obtained by combining an auxiliary optical path, is realizedA # -B and carry signal=A+(A) and B) are output in the form of optical signals;
The addend a loading section (1) comprises a second MMI 3dB splitter (52), N electro-optical modulators (11, 12, ·1n), a fourth channel (204), a fifth channel (205), and a sixth channel (206), the carry optical signal of the preceding adder The continuous light enters a fifth channel (205) and a sixth channel (206) after being split by a second channel (202) in an auxiliary light path and being input into a fourth channel (204) after being split by a first MMI 3dB beam splitter (51) in the auxiliary light path after being input into a first channel (201) in the auxiliary light path; the electro-optical modulator (11, 12, the input of 1N) is an electrical signal a, for modulating the fourth channel (204) and the fifth channel (205) simultaneously, carry optical signal/>, while loading electrical signal a onto optical domainPerforming logic AND operation with the electric signal A, wherein N is the N-th wavelength representing multiplexing and corresponds to the N-th group of data loaded in parallel, thereby carrying the optical signalAfter the electric signal A passes through the addition number A loading area (1), the electric signal A is mapped from the two-dimensional space to the three-dimensional space in a nonlinear way, so that the subsequent logical operation of exclusive OR and AND can be realized only through linear operation;
The first linear operation area (2) comprises a first MZI (21), a second MZI (22), a third MZI (23), a first MMI 3dB optical combiner (53), a second MMI 3dB optical combiner (54), a seventh channel (207), an eighth channel (208) and a first cross waveguide (24), wherein the first MZI (21) is connected with the fourth channel (204) and outputs signals from the upper end rear arm thereof, the second MZI (22) is connected with a fifth channel (205), the signals output by the upper end rear arm thereof are combined with the output of the first MZI (21) through a first MMI 3dB optical combiner (53), the signals output by the lower end rear arm thereof are input into a fourteenth channel (214) through an eighth channel (208) and a first cross waveguide (24), the third MZI (23) is connected with the sixth channel (206), the signals are output from the upper end rear arm thereof through the first cross waveguide (24), the output signals are input into the MMI 3dB optical combiner (53) through the first cross waveguide (24), and the output signals are input into the seventh channel (208) and the output from the MMI 3dB optical combiner (53) are subjected to the first linear operation area and the output from the first linear operation area (207) and the first linear operation area (23) is subjected to exclusive or the logical operation area;
The addend B loading section (3) comprises a third MMI 3dB splitter (55), N electro-optical modulators (31, 32, 3N), a ninth channel (209) a tenth channel (210), an eleventh channel (211), input optical signal Is input to a third MMI 3dB optical splitter (55) through a seventh channel (207) in the first linear operation area (2), enters a tenth channel (210) and an eleventh channel (211) after being split, and continuous light is input to the third channel (203) through an upper branch which is split by a first MMI 3dB optical splitter (51) in an auxiliary optical path and then is input to a ninth channel (209) in the addend B loading area through a first channel (201) in the auxiliary optical path; the electro-optical modulator (31, 32, the input of 3N) is an electrical signal B, for modulating the ninth channel (209) and the tenth channel (210) simultaneously, input optical signal/>, while the electrical signal B is loaded onto the optical domainAnd the electric signal B to input optical signalAfter passing through an addend B loading area (3), the A and the electric signal B are mapped from a two-dimensional space to a three-dimensional space in a nonlinear manner;
The second linear operation region (4) comprises a fourth MZI (41), a fifth MZI (42), a sixth MZI (43), a third MMI 3dB optical combiner (56), a fourth MMI 3dB optical combiner (57), a twelfth channel (212), a thirteenth channel (213) and a second cross waveguide (44), the fourth MZI (41) is connected with a ninth channel (209) and outputs signals from the upper end rear arm thereof, the fifth MZI (42) is connected with a tenth channel (210), the signals output by the upper end rear arm thereof and the outputs of the fourth MZI (41) are combined by a third MMI 3dB optical combiner (56), the signals output by the lower end rear arm thereof are input into the fifth MMI 3dB optical combiner (58) after passing through the thirteenth channel (213) and the second cross waveguide (44), the sixth MZI (43) is connected with the eleventh channel (211) and outputs signals from the upper end rear arm thereof, the signals are input into the MMI 3dB optical combiner (212) after passing through the second cross waveguide (44) and the output signals are input into the third MMI 3dB optical combiner (56), the output from the fourth MMI 3dB optical combiner (212) and the output from the fourth MMI 3dB optical combiner (56) are subjected to the logical operation region and the output from the third MMI 3 optical combiner (212).
2. The high capacity cascading electro-optic full adder chip according to claim 1, characterized in that the electro-optic modulator is a carrier injection micro-ring modulator with a modulation rate of 40GHz and a resonance peak 3dB bandwidth of 0.2nm.
3. The high-capacity cascading electro-optical full adder chip according to claim 1, wherein said electro-optical modulators are sequentially coupled with their resonant wavelengths λ 1、λ2···λN corresponding to carry optical signals, respectivelyIs a wavelength lambda 1、λ2···λN.
4. The high capacity cascadable electro-optic full-adder chip of claim 1, wherein the MZI is caused to perform a targeted linear arithmetic operation by adjusting a voltage applied to the MZI thermodes.
5. The high-capacity cascadable electro-optical full-adder chip according to claim 1, characterized in that the bandwidth of the first linear operation region (2) and the second linear operation region (4) is at least 10nm.
6. The high-capacity cascade-connection electro-optic full adder-adder chip is characterized by comprising the high-capacity cascade-connection electro-optic full adder-adder chip as set forth in any one of claims 1-5 and an electric domain inverter connected to the output end of the summation result S of each adder stage or introducing a coherent DC bias light, and by changing the signal loading rule of the addend B, the electric signal B is loaded onto the light to becomeThus, the function of the subtracter can be realized without influencing the cascade connection.
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| CN102736356A (en) * | 2012-06-13 | 2012-10-17 | 华中科技大学 | Implementation method and device for full-adder and full-subtractor |
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| CN102736356A (en) * | 2012-06-13 | 2012-10-17 | 华中科技大学 | Implementation method and device for full-adder and full-subtractor |
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