CN114780476B

CN114780476B - SPI time-sharing multiplexing circuit supporting multiple masters and multiple slaves

Info

Publication number: CN114780476B
Application number: CN202210394811.9A
Authority: CN
Inventors: 李鹏程
Original assignee: Beijing Jingwei Hirain Tech Co Ltd
Current assignee: Beijing Jingwei Hirain Tech Co Ltd
Priority date: 2022-04-15
Filing date: 2022-04-15
Publication date: 2024-03-22
Anticipated expiration: 2042-04-15
Also published as: CN114780476A

Abstract

The invention provides an SPI time-sharing multiplexing circuit supporting multiple masters and multiple slaves, wherein an SPI chip selection CS multiplexing module is used for selecting any master node to be communicated with corresponding slave nodes from a plurality of master nodes and a plurality of slave nodes; the data channel enabling module generates corresponding data channel enabling signals according to the selected corresponding master node and the selected corresponding slave node, meanwhile, when the corresponding master node occupies a bus through a chip selection signal, the bus is locked, other master nodes cannot establish a data channel, and when the corresponding master node is released by canceling the occupation of the bus, the bus can be locked by any master node; the data channel switching module executes corresponding opening and closing actions according to the data channel enabling signal, and establishes a data channel between a corresponding master node and a corresponding slave node so as to enable the corresponding master node and the corresponding slave node to perform data transmission; the time-sharing multiplexing communication of multiple master-slave nodes is realized, and IO resources of slave nodes are saved.

Description

SPI time-sharing multiplexing circuit supporting multiple masters and multiple slaves

Technical Field

The invention belongs to the technical field of time division multiplexing, and particularly relates to an SPI time division multiplexing circuit supporting multiple masters and multiple slaves.

Background

SPI (Serial Peripheral interface ) is used as a common serial data bus, only supports communication of one master and multiple slaves, and cannot directly realize communication of multiple masters and multiple slaves, and the following schemes exist in the past: 1. switching and multiplexing of SPI buses are realized by controlling the on and off of a tri-state logic chip (such as 74H 125D) through IO on a host; 2. switching the SPI bus by using a multi-path switch circuit inherited by the optocoupler module to realize multiplexing of the SPI bus; 3. and writing the priority of the master equipment into a register of the CPLD chip by using the CPLD chip, and selecting a corresponding channel by judging the priority of the master node so as to realize the communication of multiple master nodes to slave nodes.

In the previous scheme, logic chips are used, and the enabling of the logic chips is controlled through the IO of a master node, so that the switching of the communication buses of the SPI is realized; the design cost is high, the dormancy current can be increased, the function of multiple masters and one slave can be realized, and the additional IO of the master node is needed to control the logic chip.

Disclosure of Invention

In view of the above, an object of the present invention is to provide an SPI time division multiplexing circuit supporting multiple masters and multiple slaves, which is configured by a switching transistor, and which realizes time division multiplexing communication between multiple master nodes and multiple slaves of an SPI.

The application discloses an SPI time-sharing multiplexing circuit supporting multiple masters and multiple slaves, wherein the input end of the SPI time-sharing multiplexing circuit is connected with N master nodes, the output end of the SPI time-sharing multiplexing circuit is connected with M slave nodes, and N and M are integers larger than 1;

the SPI time-sharing multiplexing circuit comprises: the SPI chip selection CS multiplexing module, the data channel enabling module and the data channel switching module;

the SPI chip selection CS multiplexing module is used for selecting any master node to be communicated with the corresponding slave node from a plurality of master nodes and a plurality of slave nodes;

the input end of the data channel enabling module is connected with M chip selection pins of N main nodes, the output end of the data channel enabling module is connected with the control end of the data channel switching module, the data channel enabling module is used for generating corresponding data channel enabling signals according to corresponding main nodes and corresponding slave nodes selected by the SPI chip selection CS multiplexing module, meanwhile, when the corresponding main nodes occupy buses through the chip selection signals, the buses are locked, other main nodes cannot establish data channels, and when the corresponding main nodes occupy the buses in a non-occupied mode and are released, the buses can be locked by any main node;

The control end of the data channel switching module is connected with the output end of the data channel enabling module, the input end of the data channel switching module is respectively connected with an MRST pin, an SCLK pin and an MTSR pin of each master node, the output end of the data channel switching module is respectively connected with each chip selection pin, an MRST pin, an MTSR pin and an SCLK pin of each slave node, and the data channel switching module is used for executing corresponding opening and closing actions according to a data channel enabling signal of the data channel enabling module, and establishing a data channel between a corresponding master node and a corresponding slave node so as to enable the corresponding master node to conduct data transmission with the corresponding slave node.

Optionally, in the above SPI time division multiplexing circuit supporting multiple masters and multiple slaves, the SPI chip selection CS multiplexing module includes: an OD gate;

each input end of the OD gate circuit is connected with a chip selection pin of each main node respectively; and the method is used for enabling the chip selection signal of the corresponding slave node to be valid when the chip selection signal of any master node is valid, and completing selection of the corresponding master node and the corresponding slave node to be communicated.

Optionally, in the above SPI time division multiplexing circuit supporting multiple masters and multiple slaves, the OD gate circuit includes: m OD units;

The input end of each OD unit is connected with a corresponding chip selection pin of each main node respectively; the output ends of the OD units are respectively connected with the chip selection pins of the corresponding slave nodes.

Optionally, in the above SPI time division multiplexing circuit supporting multiple masters and multiple slaves, the OD unit includes: multiplexing the switching tube and the N diodes;

the control ends of the multiplexing switch tubes are respectively connected with corresponding chip selection pins of the N main nodes in a one-to-one correspondence manner through N diodes;

the first end of the multiplexing switch tube is respectively connected with one end of the first resistor and one end of the second resistor, and the connection point is connected with the corresponding slave node;

the other end of the first resistor is connected with the control end of the multiplexing switch tube;

the other end of the second resistor is connected with a power supply;

the second end of the multiplexing switch tube is grounded.

Optionally, in the above SPI time division multiplexing circuit supporting multiple masters and multiple slaves, the data channel enabling module includes: n data channel enabling units;

the input end of each data channel enabling unit is connected with the chip selection pin of the corresponding main node respectively;

the output end of each data channel enabling unit is connected with the corresponding input end of the data channel switching module respectively;

And the locking function ends of the data channel enabling units are connected, so that when the master node and the slave node enabled by any one data channel enabling unit carry out data transmission, the other data channel enabling units are locked, and the other master node and the slave node inhibit data transmission.

Optionally, in the above SPI time division multiplexing circuit supporting multiple masters and multiple slaves, the data channel enabling unit includes: a first enabling switching tube, first to N-1 locking switching tubes, a second enabling switching tube and M diodes;

the control ends of the first enabling switch tubes are respectively connected with anodes of the M diodes and one end of the third resistor;

cathodes of the M diodes are respectively connected with M chip selection pins of the corresponding main node;

the first end of the first enabling switch tube is respectively connected with the other end of the third resistor and the power supply;

the second end of the first enabling switch tube is respectively connected with one end of a sixth resistor, the first ends of the first to N-1 locking switch tubes and the control end of the second enabling switch tube, and the connection point is used as a locking output end of the data channel enabling unit and is connected with locking input ends of other data channel enabling units;

The control ends of the first to N-1 locking switching tubes are used as locking input ends of the data channel enabling units and are correspondingly connected with the locking output ends of the other N-1 data channel enabling units one by one;

the second ends of the first to N-1 locking switching tubes are connected, and the connection point is connected with one end of a fifth resistor;

the other end of the fifth resistor, the other end of the sixth resistor and the second end of the second enabling switch tube are grounded;

the first end of the second enabling switch tube is connected with one end of the fourth resistor, and the connection point is used as the output end of the data channel enabling unit;

the other end of the fourth resistor is connected with a power supply.

Optionally, in the above SPI time division multiplexing circuit supporting multiple masters and multiple slaves, the data channel switching module includes: an MRST data channel switching module and an MTSR & SCLK data channel switching module;

the MTSR & SCLK data channel switching module comprises: n MTSR & SCLK data channel switching units; the control end of each MTSR & SCLK data channel switching unit is used as the control end of the data channel switching module, and the input end of each MTSR & SCLK data channel switching unit is respectively connected with the MTSR pin and the SCLK pin of the corresponding master node; the first output ends of the MTSR and SCLK data channel switching units are connected, and the connection points are respectively connected with SCLK pins of the slave nodes; the second output ends of the data channel enabling units are connected, and the connection points are respectively connected with MTSR pins of the slave nodes;

The MRST data channel switching module comprises: m MRST data channel switching units; the output ends of the MRST data channel switching units are connected, and the connection points are grounded and connected to MRST pins of the master nodes; the input ends of the M MRST data channel switching units are respectively connected with MRST pins of M slave nodes in a one-to-one correspondence manner; and the control ends of the MRST data channel switching units are respectively connected with the chip selection pins of the slave nodes in a one-to-one correspondence manner.

Optionally, in the above SPI time division multiplexing circuit supporting multiple masters and multiple slaves, the MTSR & SCLK data channel switching unit includes: the first switching tube, the second switching tube, the third switching tube and the fourth switching tube;

the control ends of the switching tubes are connected, and the connection points are used as the control ends of the MTSR and SCLK data channel switching units and receive data channel enabling signals of the corresponding main nodes of the data channel enabling modules;

the first end of the first switching switch tube is connected with an SCLK pin of the corresponding main node;

the second end of the first switching tube is connected with the second end of the second switching tube;

the first end of the third switching tube is connected with the MTSR pin of the corresponding main node;

The second end of the third switching tube is connected with the second end of the fourth switching tube;

resistors are arranged between the control end and the second end of each switching tube;

the first end of the second switching tube is connected with the first output end of the MTSR & SCLK data channel switching unit;

the first end of the fourth switching tube is connected with the second output end of the MTSR & SCLK data channel switching unit.

Optionally, in the above SPI time division multiplexing circuit supporting multiple masters and multiple slaves, the MRST data channel switching unit includes: a fifth switching tube and a sixth switching tube;

the first end of the fifth transfer switch tube is used as the output end of the MRST data channel switching unit;

the second end of the fifth switching tube is connected with the second end of the sixth switching tube;

the first end of the sixth switching tube is used as an input end of the output end of the MRST data channel switching unit;

the control end of the fifth switching tube is connected with the control end of the sixth switching tube, and the connection point is used as the control end of the MRST data channel switching unit;

corresponding resistors are arranged between the control end and the second end of each switching tube.

Optionally, in the SPI time division multiplexing circuit supporting multiple masters and multiple slaves, a switching transistor in the data channel enabling module is a triode; the switching tube in the data channel switching module is a MOSFET tube.

According to the technical scheme, the SPI time-sharing multiplexing circuit supporting multiple masters and multiple slaves provided by the invention has the input end connected with N master nodes and the output end connected with M slave nodes, and comprises: the SPI chip selection CS multiplexing module, the data channel enabling module and the data channel switching module; the input end of the SPI chip selection CS multiplexing module is respectively connected with M chip selection pins of N master nodes, the output end of the SPI chip selection CS multiplexing module is connected with chip selection pins of M slave nodes, and the SPI chip selection CS multiplexing module is used for selecting any master node to be communicated with corresponding slave nodes from the plurality of master nodes and the plurality of slave nodes; the input end of the data channel enabling module is connected with M chip selection pins of N main nodes, the output end of the data channel enabling module is connected with the control end of the data channel switching module, the data channel enabling module is used for generating corresponding data channel enabling signals according to corresponding main nodes and corresponding slave nodes selected by the SPI chip selection CS multiplexing module, meanwhile, when the corresponding main nodes occupy buses through the chip selection signals, the buses are locked, other main nodes cannot establish data channels, and when the corresponding main nodes occupy the buses in a canceling mode, and after the buses are released, the buses can be locked by any main node; the control end of the data channel switching module is connected with the output end of the data channel enabling module, the input end of the data channel switching module is respectively connected with the MRST pin, the SCLK pin and the MTSR pin of each master node, the output end of the data channel switching module is respectively connected with each chip selection pin, the MRST pin, the MTSR pin and the SCLK pin of each slave node, and the data channel switching module is used for executing corresponding opening and closing actions according to a data channel enabling signal of the data channel enabling module, and establishing a data channel between a corresponding master node and a corresponding slave node so as to enable the corresponding master node and the corresponding slave node to conduct data transmission; the time division multiplexing communication between the multi-master node and the multi-slave node of the SPI is realized; meanwhile, taking a chip selection signal of the master node as a bus switching enabling signal; namely, if the chip selection signal of the corresponding master node is valid, generating a data channel enabling signal corresponding to the master node, establishing a data channel between the master node and the corresponding slave node, realizing bus switching enabling, and saving IO resources of the slave node; in addition, only one master node occupies the bus at the same time, so that the reliability of SPI time-sharing multiplexing is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an SPI time division multiplexing circuit supporting multiple masters and multiple slaves according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another SPI time division multiplexing circuit supporting multiple masters and multiple slaves according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an SPI chip selection CS multiplexing module in an SPI time-sharing multiplexing circuit supporting multiple masters and multiple slaves according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a data channel enabling module in an SPI time division multiplexing circuit supporting multiple masters and multiple slaves according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an MRST data channel switching module in an SPI time division multiplexing circuit supporting multiple masters and multiple slaves according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a MTSR & SCLK data channel switching module in an SPI time division multiplexing circuit supporting multiple masters and multiple slaves according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of another SPI time division multiplexing circuit supporting multiple masters and multiple slaves according to an embodiment of the present invention;

fig. 8 is a schematic diagram of another SPI time division multiplexing circuit supporting multiple masters and multiple slaves according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In this application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The embodiment of the application provides an SPI time-sharing multiplexing circuit supporting multiple masters and multiple slaves, which is used for solving the problem that logic chips are used in the prior art, and switching of a communication bus of an SPI is realized by enabling a master node IO control logic chip; the design cost is high, the dormancy current can be increased, the function of multiple masters and one slave can be realized, and the problem that the logic chip is controlled by extra IO of the master node is required.

Referring to fig. 1, an input end of the SPI time division multiplexing circuit supporting multiple masters and multiple slaves is connected to N master nodes, and an output end of the SPI time division multiplexing circuit supporting multiple masters and multiple slaves is connected to M master nodes.

Specifically, the N master node interface units of the SPI time division multiplexing circuit are respectively connected to N master nodes (e.g., master node 1 and master node 2 and … … shown in fig. 1, master node N) in a one-to-one correspondence.

N is an integer greater than 1; the specific value of N is not described in detail herein, and can be determined according to practical situations, and is within the protection scope of the present application.

Specifically, the 1 st master node interface unit of the SPI time-sharing multiplexing circuit is connected with the 1 st master node (such as the master node 1 shown in fig. 1); the 2 nd main node interface unit of the SPI time-sharing multiplexing circuit is connected with the 2 nd main node (such as the main node 2 shown in figure 1); the 3 rd main node interface unit of the SPI time-sharing multiplexing circuit is connected with the 3 rd main node (not shown); by analogy, the N-1 th main node interface unit of the SPI time-sharing multiplexing circuit is connected with the N-1 st main node (not shown); an nth master node interface unit of the SPI time-sharing multiplexing circuit is connected with an nth master node (such as a master node N shown in fig. 1).

Taking the 1 st main node interface unit as an example for explanation, the M chip select pins of the main node interface unit are connected with the M chip select pins of the main node 1 in a one-to-one correspondence manner (such as CS 1-1 and CS 0-1 shown in FIG. 1); the SCLK pin of the master node interface unit is connected to the SCLK pin of the master node 1 (sclk_1 as shown in fig. 1); the MTSR pin of the master node interface unit is connected to the MTSR pin of the master node 1 (mtsr_1 shown in fig. 1). The MRST pins of the master nodes are connected, and the connection points are connected with the MRST pins of the SPI time division multiplexing circuit (such as MRST shown in figure 1).

The M slave node interface units of the SPI time division multiplexing circuit are respectively connected with M slave nodes (shown in fig. 1 by taking m=2 as an example, and include slave node 0 and slave node 1 shown in fig. 2) in a one-to-one correspondence; m is an integer greater than 1.

M is an integer greater than 1; the specific value of M is not described in detail herein, and can be determined according to practical situations, and is within the protection scope of the present application.

Specifically, the 1 st slave node interface unit of the SPI time-sharing multiplexing circuit is connected with the 1 st slave node (such as the slave node 0 shown in fig. 1); the 2 nd slave node interface unit of the SPI time-sharing multiplexing circuit is connected with the 2 nd slave node (the slave node 1 shown in figure 1); the 3 rd slave node interface unit of the SPI time-sharing multiplexing circuit is connected with the 3 rd slave node (not shown); by analogy, the M-1 slave node interface unit of the SPI time-sharing multiplexing circuit is connected with the M-1 slave node (not shown); the mth slave node interface unit of the SPI time division multiplexing circuit is connected to an mth slave node (not shown).

Taking the 1 st slave node interface unit as an example, the chip select pin of the slave node interface unit is connected with the chip select pin of the slave node 0 (CS 0 shown in fig. 1); the MRST pin of the slave node interface unit is connected to the MRST pin of the slave node (MRST as shown in fig. 1). The SCLK pins of the slave nodes are connected, and the connection point is connected with the SCLK pin of the SPI time division multiplexing circuit (SCLK shown in figure 1); the MTSR pins of each slave node are connected to each other, and the connection points are connected to the MTSR pins of the SPI time division multiplexing circuit (MTSR shown in FIG. 1).

And enabling the corresponding data channel through the chip selection signal of the SPI of the master node, and establishing communication between the slave node and the master node according to the chip selection signal of the master node, so as to realize data transmission.

Multiple master nodes need to access the same slave node, and the number of SPI channels of the slave node controller is insufficient, so that normal communication between multiple master nodes and slave nodes needs to be completed in a bus multiplexing mode.

That is, when the chip select signal of any master node is valid, the master node occupies the bus of the SPI time division multiplexing circuit, and the master node performs data transmission with the corresponding slave node. Specifically, the same time can be one master for communication with multiple slaves; the communication can be performed by a master and a slave, which are not repeated here, and the communication can be performed according to actual conditions and are all within the protection scope of the application.

It should be noted that, in fig. 1, each CS (such as cs1_1, cs0_1, cs1_2, cs0_ … … cs1_ N, CS0 _0_ N, CS0, CS 1) each SCLK (such as sclk_1, sclk_2 … … sclk_ N, SCLK shown in fig. 1), each MTSR (such as mtsr_1, mtsr_ … … mtsr_ N, MTSR shown in fig. 1), and each MRST (such as MRST, MRST2, mrst_ N, MRST0, and MRST1 shown in fig. 1) are pins or signals of a corresponding node, which are not repeated herein, and may be required to be within the scope of the present application according to practical situations.

The SPI time-sharing multiplexing circuit is used for the same time, and is particularly used when only one master node occupies a bus: the SPI time-sharing multiplexing circuit is provided with a bus locking function, so that when any master node occupies a bus, other master nodes cannot occupy the bus. That is, when a certain master node occupies the bus through the chip select signal, the bus will be locked, and the chip select signals of the other master nodes will not enable the data channel; when the bus is released, the bus lock is released simultaneously, and the bus can be locked by any master node, so that the reliability of the time-sharing multiplexing circuit is improved. In this embodiment, a bus locking function is added, and when a certain master node occupies the bus, the other master nodes cannot occupy the bus, so that reliability of SPI time-sharing multiplexing is increased.

Referring to fig. 2, the SPI time division multiplexing circuit includes: the SPI chip selects the CS multiplexing module, the data channel enabling module and the data channel switching module.

The input end of the SPI chip selection CS multiplexing module is respectively connected with M chip selection pins of the N main nodes; that is, the input end of the SPI chip selection CS multiplexing module includes n×m input sub-ends, where the n×m input sub-ends are connected to the n×m chip selection pins in a one-to-one correspondence. The output end of the SPI chip selection CS multiplexing module is connected with the chip selection pins of the M slave nodes. That is, the output end of the SPI chip selection CS multiplexing module comprises M output sub-ends, and the M output sub-ends are connected with the chip selection pins of the M slave nodes.

And the SPI chip selection CS multiplexing module is used for selecting any master node to be communicated with the corresponding slave node from the plurality of master nodes and the plurality of slave nodes.

Specifically, it should be noted that a master node has a plurality of chip select pins, and each chip select pin corresponds to a slave node, so that when the chip select signal of the corresponding chip select pin is valid, the master node and the corresponding slave node are selected.

The input end of the data channel enabling module is connected with M chip selection pins of N main nodes; that is, the input terminal of the data channel enable module includes n×m input sub-terminals, and the n×m input sub-terminals are connected to the n×m chip select pins in a one-to-one correspondence manner.

The data channel enabling module is used for generating corresponding data channel enabling signals according to the corresponding master node and the corresponding slave node selected by the SPI chip selection CS multiplexing module, meanwhile, when the corresponding master node occupies the bus through the chip selection signals, the bus is locked, other master nodes cannot establish the data channel, and when the corresponding master node releases the bus through the bus which is not occupied, the bus can be locked by any master node.

Specifically, on the basis of an SPI chip selection CS multiplexing module, enabling data channels of a master node and a slave node; it should be noted that, because the topology of the SPI time division multiplexing circuit is a multi-master multi-slave structure, and there are cases where different master nodes preempt the bus, based on this point, the bus locking function is added in this scheme, when a certain master node occupies the bus through the chip selection signal, the bus will be locked, the chip selection signals of the other master nodes will not enable the data channel, and when the bus is released, the bus locking is released simultaneously, and the bus can be locked by any master node, thereby increasing the reliability of the time division multiplexing circuit.

The control end of the data channel switching module is connected with the output end of the data channel enabling module; the input end of the data channel switching module is respectively connected with an MRST pin, an SCLK pin and an MTSR pin of each master node; that is, the input end of the data channel switching module comprises a plurality of input sub-ends, so that each input sub-end receives a corresponding signal; for example, N input sub-terminals are connected to SCLK pins of N master nodes, and N input sub-terminals are connected to MTSR pins of N master nodes, and another input sub-terminal is simultaneously connected to MRST pins of each master node.

The output end of the data channel switching module is respectively connected with each chip selection pin, MRST pin, MTSR pin and SCLK pin of each slave node. That is, the output terminal of the data channel switching module includes a plurality of output sub-terminals, so that each output sub-terminal outputs a corresponding signal.

And the data channel switching module is used for executing corresponding opening and closing actions according to the data channel enabling signal of the data channel enabling module, and establishing a data channel between the corresponding master node and the corresponding slave node so as to enable the corresponding master node and the corresponding slave node to perform data transmission.

When the chip selection signal of the master node is enabled, the data channel enabling module selects a corresponding channel, and the data lines of the corresponding master node and the slave node are conducted, so that the function of time-sharing multiplexing of the data channels is realized, and the data transmission of the corresponding master node and the slave node is realized.

In the embodiment, the time division multiplexing communication between the multi-master node and the multi-slave node of the SPI is realized; meanwhile, taking a chip selection signal of the master node as a bus switching enabling signal; namely, if the chip selection signal of the corresponding master node is valid, generating a data channel enabling signal corresponding to the master node, establishing a data channel between the master node and the corresponding slave node, realizing bus switching enabling, and saving IO resources of the slave node; in addition, only one master node occupies the bus at the same time, so that the reliability of SPI time-sharing multiplexing is improved.

In practical application, the SPI chip selection CS multiplexing module comprises: OD gate.

And each input end of the OD gate circuit is connected with a chip selection pin of each main node respectively.

The OD gate circuit is used for enabling the chip selection signal of the corresponding slave node to be valid when the chip selection signal of any master node is valid, and completing selection of the corresponding master node and the corresponding slave node to be communicated.

Specifically, the chip select signal of the chip select pin may be valid at a low level or valid at a high level, which is not described in detail herein, and may be determined according to actual situations, which are all within the protection scope of the present application.

Taking low level as an example, the OD gate circuit realizes the line and function of the master node CS, that is, when the chip select function of any master node is pulled down, the chip select signal of the slave node can be pulled down, so as to select the corresponding slave node and master node.

In practical applications, the OD gate includes: m OD units.

The input end of each OD unit is connected with the corresponding chip selection pin of each main node respectively; the output end of each OD unit is connected with the chip selection pin of the corresponding slave node.

Specifically, the input end of the 1 st OD unit is respectively connected with the 1 st chip selection pin of each main node; the output end of the 1 st OD unit is respectively connected with the chip selection pin of the 1 st slave node; the input end of the 2 nd OD unit is respectively connected with the 2 nd chip selection pin of each main node; the output end of the 2 nd OD unit is respectively connected with the chip selection pin of the 2 nd slave node; the input end of the 3 rd OD unit is respectively connected with the 3 rd chip selection pin of each main node; the output end of the 3 rd OD unit is respectively connected with the chip selection pin of the 3 rd slave node; by analogy, the input end of the Mth OD unit is respectively connected with the Mth chip selection pin of each main node; the output ends of the M-th OD units are respectively connected with the chip selection pins of the M-th slave nodes.

In practical applications, the OD unit includes: the switching tube and the N diodes are multiplexed.

The control ends of the multiplexing switch tubes are respectively connected with corresponding chip selection pins of N main nodes in a one-to-one correspondence manner through N diodes; the first end of the multiplexing switch tube is respectively connected with one end of the first resistor and one end of the second resistor, and the connection point is connected with the corresponding slave node; the other end of the first resistor is connected with the control end of the multiplexing switch tube; the other end of the second resistor is connected with a power supply; the second end of the multiplexing switch tube is grounded.

As shown in fig. 3 (illustrated by taking m=2 as an example), taking the 1 st OD unit as an example, the control end of the multiplexing switch tube u_cs1_0 is respectively connected with the anodes of N diodes (d1_1 and d1_ … … d1_n shown in fig. 3); the cathode of the 1 st diode D1_1 is connected with the chip selection pin CS1_1 of the 1 st main node; the cathode of the 2 nd diode D1_2 is connected with the chip selection pin CS1_2 of the 2 nd main node; by analogy, the cathode of the nth diode d1_n is connected to the chip select pin cs1_n of the nth master node.

The first end of the multiplexing switch tube U_CS1_0 is respectively connected with one end of the first resistor R_CS_1 and one end of the second resistor R_CS1_UP, and the connection point is connected with the 1 st slave node; the other end of the first resistor R_CS_1 is connected with the control end of the multiplexing switch tube U_CS 1_0; the other end of the second resistor R_CS1_UP is connected with a power supply VCC; the second terminal of the multiplexing switch tube U_CS1_0 is grounded.

The 2 nd OD unit (including u_cs0_0, r_cs0_up, r_cs_0, d0_1, d0_ … … d0_n) has the same structure as the 1 st OD unit, and is not described in detail herein, and is within the scope of the present application.

In practical application, the data channel enabling module includes: n data channel enable units.

The input ends of the data channel enabling units are respectively connected with the chip selection pins of the corresponding master nodes.

Specifically, the input end of the 1 st data channel enabling unit is connected with the chip selection pin of the 1 st main node; the input end of the 2 nd data channel enabling unit is connected with the chip selection pin of the 2 nd main node; and so on, the input end of the Nth data channel enabling unit is connected with the chip selection pin of the Nth main node.

It should be noted that the number of chip selection pins of the master node is the same as the number of slave nodes; thus, when the number of slave nodes is plural, plural chip select pins of the same master node are connected to the input terminals of the same data channel enabling unit.

The output end of each data channel enabling unit is connected with the corresponding input end of the data channel switching module.

It should be noted that, the data channel switching module has M input ends, so that the output ends of the M data channel enabling units are connected with the data channel switching module in a one-to-one correspondence manner, and enable signals are transmitted for the data channel switching module.

The locking function ends of the data channel enabling units are connected, so that when the master node and the slave node enabled by any one data channel enabling unit carry out data transmission, other data channel enabling units are locked, and the other master node and the slave node inhibit data transmission.

That is, when any one of the data channel enable units performs a locking action, the other data channel enable units are locked.

In practical application, the data channel enabling unit includes: the first enable switch tube, the first to N-1 locking switch tubes, the second enable switch tube and M diodes.

The first enabling switch tube, the first to N-1 locking switch tubes and the second enabling switch tube are all triodes.

The control ends of the first enabling switch tubes are respectively connected with anodes of the M diodes and one end of the third resistor; cathodes of the M diodes are respectively connected with M chip selection pins of the corresponding main node; the first end of the first enabling switch tube is connected with the other end of the third resistor and the power supply respectively; the second end of the first enabling switch tube is respectively connected with one end of the sixth resistor, the first ends of the first to N-1 locking switch tubes and the control end of the second enabling switch tube, and the connection point is used as a locking output end of the data channel enabling unit and is connected with locking input ends of other data channel enabling units; the control ends of the first to N-1 locking switching tubes are used as locking input ends of the data channel enabling units and are correspondingly connected with locking output ends of other N-1 data channel enabling units one by one; the second ends of the first to N-1 locking switching tubes are connected, and the connection point is connected with one end of a fifth resistor; the other end of the fifth resistor, the other end of the sixth resistor and the second end of the second enabling switch tube are all grounded; the first end of the second enabling switch tube is also connected with one end of the fourth resistor, and the connection point is used as the output end of the data channel enabling unit; the other end of the fourth resistor is connected with a power supply.

As shown in fig. 4 (shown by way of example with m=2), the 1 st data channel switching module is taken as an example:

the control terminal of the first enable switching tube q_en1 is connected to the anodes of the 2 diodes (e.g., DSC0_1 and DSC1_1 shown in fig. 4) and one terminal of the third resistor, respectively.

The cathode of the diode DSC0_1 is connected with a chip selection pin CS0_1 of the 1 st main node; the cathode of diode DSC1_1 is connected to chip select pin cs1_1 of the 1 st master node.

The first end of the first enabling switch tube Q_EN1 is respectively connected with the other end of the third resistor and the power supply VCC.

The second end of the first enabling switch tube Q_EN1 is respectively connected with one end of the sixth resistor, the first end … … of the first locking switch tube Q_EN2_1, the first end of the N-1 locking switch tube Q_ENN_1 and the control end of the second enabling switch tube Q_EN1_1, and the connection point is used as a locking output end of the data channel enabling unit and connected with locking input ends of other data channel enabling units.

The control terminals of the first to N-1 locking switch transistors (q_en2_ … … q_enn_1 shown in fig. 4) are all used as the locking input terminal of the data channel enabling unit and connected with the locking output terminals of other data channel enabling units.

The second ends of the first to N-1 locking switching tubes are connected, and the connection point is connected with one end of the fifth resistor.

The other end of the fifth resistor, the other end of the sixth resistor and the second end of the second enabling switch tube Q_EN1_1 are all grounded; the first end of the second enabling switch tube Q_EN1_1 is also connected with one end of a fourth resistor R_EN_UP, and the connection point is used as the output end of the data channel enabling unit; the other end of the fourth resistor R_EN_UP is connected with a power supply VCC.

It should be noted that, the data channel enabling module is configured to automatically switch the data channel by enabling a chip select signal, where the chip select signal is usually active low, as shown in fig. 4, and takes cs1_1 of the master node 1 as an example in the SPI time division multiplexing circuit diagram: when the cs1_1 signal triggers low, i.e., the gates of u_mrst1_0, u_mrst1_1 are pulled low, i.e., the MRST channel is enabled; at the same time, q_en1 is on and en_1 is high, thus turning on q_en1_1, pulling the gates of u_sclk1_0, u_sclk1_1, u_mtsr1_0, u_mtsr1_1 four POMSs low, i.e., SCLK and MTSR channels are enabled. Pulling CS1 low will turn on q_en1_2, q_en1_n, at which time the chip select signals of the remaining master nodes will not be available. Thereby pulling en_2, en_n low for the purpose of locking the bus.

The 2 nd data channel switching module (including q_en2, DSC0_2, DSC1_2, q_en1_ … … q_enn_2) to the nth data channel switching module (including q_enn, DSC0_ N, DSC _ N, Q _en1_n … … q_enn_n) have the same structure as the 1 st data channel switching module, and are not described in detail herein, and are all within the protection scope of the present application.

In practical application, the data channel switching module includes: and the MRST data channel switching module and the MTSR and SCLK data channel switching module.

And the MRST data channel switching module is used for sending data from the slave node to the master node. Wherein the data transmitted from the slave node to the master node may be an MRST signal.

And the MTSR & SCLK data channel switching module is used for realizing the data transmission of the master node to the slave node. The data transmitted by the master node to the slave node may be an MTSR signal and an SCLK signal.

That is, the data channel switching modules are divided into two groups, namely an MRST data channel switching module and an MTSR & SCLK data channel switching module; the transmission directions of the MRST data channel switching module and the MTSR and SCLK data channel switching module are different; the MRST data channel switching module is a slave node and transmits the data to the master node, the MTSR and SCLK data channel switching modules are all master nodes and transmit the data to the slave nodes, so that the data channels are grouped according to the data transmission direction, when the master node chip selection signal is enabled, the data channel enabling module selects the corresponding channel, the data lines of the corresponding master node and the slave nodes are conducted, and the function of time-sharing multiplexing of the data channels is realized.

In practical application, the MTSR & SCLK data channel switching module includes: n MTSR & SCLK data channel switching units.

The control end of each MTSR & SCLK data channel switching unit is used as the control end of the data channel switching module, so that the control end of each MTSR & SCLK data channel switching unit receives the data channel enabling signal of the corresponding master node of the data channel enabling module. The input end of each MTSR & SCLK data channel switching unit is respectively connected with the MTSR pin and the SCLK pin of the corresponding master node, so that the input end of each MTSR & SCLK data channel switching unit respectively receives the MTSR signal and the SCLK signal of the corresponding master node; the MTSR signal is received by the master node, the slave node sends command signal, and the SCLK signal is serial clock signal.

Specifically, the control end of the 1 st MTSR & SCLK data channel switching unit is connected to the 1 st output end of the data channel enabling module, so as to receive the data channel enabling signal output by the data channel enabling module about the 1 st master node; the control end of the 2 nd MTSR & SCLK data channel switching unit is connected with the 2 nd output end of the data channel enabling module to receive the data channel enabling signal outputted by the data channel enabling module about the 2 nd main node; and so on, the control end of the nth MTSR & SCLK data channel switching unit is connected with the nth output end of the data channel enabling module so as to receive the data channel enabling signal output by the data channel enabling module about the nth master node.

The first output ends of the MTSR and SCLK data channel switching units are connected, and the connection points are used as SCLK pins of the SPI time-sharing multiplexing circuit and are respectively connected with SCLK pins of the slave nodes. The first output terminal of the MTSR & SCLK data channel switching unit is also grounded through a resistor R_PD_0.

The second output end of each data channel enabling unit is connected, and the connection point is used as an MTSR pin of the SPI time-sharing multiplexing circuit and is respectively connected with the MTSR pin of each slave node. The second output terminal of the MTSR & SCLK data channel switching unit is also grounded through a resistor R_PD_1.

In practical application, the MTSR & SCLK data channel switching unit includes: the switching device comprises a first switching tube, a second switching tube, a third switching tube and a fourth switching tube.

The control ends of the switching tubes are connected, and the connection points serve as the control ends of the MTSR and SCLK data channel switching units and receive data channel enabling signals of corresponding master nodes of the data channel enabling modules. The first end of the first switching switch tube is connected with the SCLK pin of the corresponding main node, so that the first end of the first switching switch tube receives the SCLK signal of the corresponding main node; the second end of the first switching tube is connected with the second end of the second switching tube; the first end of the third switching tube is connected with the MTSR pin of the corresponding master node so that the first end of the third switching tube receives the MTSR signal of the corresponding master node; the second end of the third switching tube is connected with the second end of the fourth switching tube; resistors are arranged between the control end and the second end of each switching tube; the first end of the second switching tube is connected with the first output end of the MTSR & SCLK data channel switching unit; the first end of the fourth switching tube is connected with the second output end of the MTSR & SCLK data channel switching unit.

As shown in fig. 6, taking the 1 st MTSR & SCLK data channel switching unit as an example:

the control terminals of the switching transistors (U_SCLK1_0, U_SCLK1_1, U_MTSR1_0, U_MTSR1_1) are connected as shown in FIG. 6, and the connection point receives the enable signal of the data channel enable module with respect to the 1 st master node.

The first end of the first switching tube u_sclk1_0 receives the SCLK signal of the 1 st master node (sclk_1 as shown in fig. 6).

The second end of the first switching tube u_sclk1_0 is connected to the second end of the second switching tube u_sclk1_1.

The first terminal of the third switching transistor U_MTSR1_0 receives the MTSR signal of the 1 st master node (MTSR 1 shown in FIG. 6).

The second terminal of the third switching tube U_MTSR1_0 is connected with the second terminal of the fourth switching tube U_MTSR1_1.

Resistors are arranged between the control end and the second end of each switching tube.

The first end of the second switching tube is connected with the first output end of the MTSR & SCLK data channel switching unit, the SCLK pin of each slave node, and grounded through a resistor R_PD_0.

The first end of the fourth switching tube is connected with the second output end of the MTSR & SCLK data channel switching unit, the MTSR pins of the slave nodes, and grounded through a resistor R_PD_1.

The structures of the 2 nd MTSR & SCLK data channel switching units (shown in fig. 6, including u_sclk2_0, u_sclk2_1, u_mtsr2_0, and u_mtsr2_1) to the nth MTSR & SCLK data channel switching units (shown in fig. 6, including u_sclkn_0, u_sclkn_1, u_mtsrn_0, and u_mtsrn_1) are the same as those of the 1 st MTSR & SCLK data channel switching unit, and they are not repeated here, and they are all within the scope of the present application as required according to practical situations.

MTSR_2 to MTSR_N are the MTSR signals of the corresponding master nodes; sclk_2 to sclk_n are each SCLK signals of the respective master node.

In practical application, the MRST data channel switching module includes: m MRST data channel switching units.

The output ends of the MRST data channel switching units are connected, and the connection points are grounded and connected to MRST pins of the main nodes.

The input ends of the M MRST data channel switching units are connected with MRST pins of M slave nodes in a one-to-one correspondence mode.

Specifically, the input end of the 1 st MRST data channel switching unit is connected with the MRST pin of the 1 st slave node; the input end of the 2 nd MRST data channel switching unit is connected with the MRST pin of the 2 nd slave node; and by analogy, the input end of the Mth MRST data channel switching unit is connected with the MRST pin of the Mth slave node.

The control ends of the MRST data channel switching units are respectively connected with the chip selection pins of the slave nodes in a one-to-one correspondence mode, so that the control ends of the MRST data channel switching units receive the chip selection signals of the corresponding slave nodes.

Specifically, the control end of the 1 st MRST data channel switching unit is connected with the chip selection pin of the 1 st slave node; the control end of the 2 nd MRST data channel switching unit is connected with the chip selection pin of the 2 nd slave node; and by analogy, the control end of the Mst MRST data channel switching unit is connected with the chip selection pin of the Mth slave node.

In practical application, the MRST data channel switching unit includes: a fifth transfer switching tube and a sixth transfer switching tube.

The first end of the fifth transfer switch tube is used as the output end of the MRST data channel switching unit; the second end of the fifth switching tube is connected with the second end of the sixth switching tube; the first end of the sixth switching tube is used as an input end of the output end of the MRST data channel switching unit; the control end of the fifth switching tube is connected with the control end of the sixth switching tube, and the connection point is used as the control end of the MRST data channel switching unit; corresponding resistors are arranged between the control end and the second end of each switching tube.

As shown in fig. 5, taking the 1 st MRST data channel switching unit as an example:

a first end of the fifth switching tube UMRST0_0 is used as an output end of the MRST data channel switching unit; the second end of the fifth switching tube UMRST0_0 is connected with the second end of the sixth switching tube UMRST0_1; a first end of the sixth switching tube UMRST0_1 is used as an input end of the output end of the MRST data channel switching unit; the control end of the fifth switching tube UMRST0_0 is connected with the control end of the sixth switching tube UMRST0_1, and the connection point is used as the control end of the MRST data channel switching unit and receives a chip selection signal CS0 of the 1 st slave node; corresponding resistors are arranged between the control end and the second end of each switching tube.

The 2 nd MRST data channel switching unit (including umrst1_0, umrst1_1 as shown in fig. 5) has the same structure as the 1 st MRST data channel switching unit, and a control terminal of the 2 nd MRST data channel switching unit receives the chip select signal CS1 of the 2 nd slave node.

The first to sixth switching transistors are MOSFETs, specifically PMOS.

In the above data channel switching module, a single data line uses two PMOS as switches, wherein the SCLK and MTSR data lines are turned on and off by a data channel enable signal. When the data channel enable signal is high, the two PMOS are in a closed state, and the body diodes of the two PMOS isolate the data line of the master node from the data line of the slave node. When the data channel enabling signal is in a low level, the data selecting channel is opened, and the master node and the slave node can normally communicate; the MRST data line takes a CS chip selection signal of the slave node as a trigger condition, when CS is in a high level, the PMOS is in a closed state, and the two PMOS body diodes isolate the data line of the master node from the data line of the slave node. When CS is low level, the data selection channel is opened, and the master node and the slave node can normally communicate.

The working modes of the SPI time-sharing multiplexing circuit supporting multiple masters and multiple slaves are divided into three modes, namely a bus release mode, a bus locking mode and a bus data transmission mode. The following will take the structure shown in fig. 7 and 8 as an example:

1. as shown in fig. 7 and 8, in the SPI time division multiplexing circuit diagrams, in the bus release mode, the chip select signals of all the master nodes are at high level, and the chip select signals of the slave nodes are also at high level after passing through the circuit of the scheme. The master node and the slave node do not communicate, and the data line of the master node and the data line of the slave node are isolated by the body diode of the PMOS.

2. As shown in the SPI time division multiplexing circuit diagrams of fig. 7 and 8, in the bus locking mode, all the master nodes have the same control priority on the bus, and the principle of occupying the bus is that the master node that is occupying the bus uses the bus first according to the order of occupying the bus. Taking the master node 1 and the slave node 1 as an example, the specific principle is that when the chip selection signal CS1 of the master node triggers (i.e. is active low), the corresponding q_en1 will be turned on, so that the channel enable signal EN1 changes from low to high; when the channel enable signal EN1 is at a high level, the corresponding q_en1_1, q_en1_2, q_en1_n are turned on, wherein q_en1_2, q_en1_n will force the channel enable signals en_2 and en_n of the other master nodes to be pulled down, so that the chip select chip of the other master nodes cannot enable the data communication module, achieving the function of bus locking, and q_en1_1 is turned on to pull down the gates of the four PMOS of u_sclk1_0, u_sclk1_1, u_mtsr1_0, u_mtsr1_1, and prepare for bus data transmission.

3. As shown in fig. 7 and 8, in the SPI time division multiplexing circuit diagrams, in the bus data transmission mode, for example, when q_en1_1 turns on, the gates of two PMOS of u_sclk1_0 and u_sclk1_1 are pulled down, even if SCLK channels are enabled, when the data line of sclk_1 is low, SCLK is pulled down to low by r_pd_0, and when the data line of sclk_1 is high, the voltages pass through the body diode of u_sclk1_0 to the sources of u_sclk1_0 and u_sclk1_1, and because the sources of u_sclk1_0 and u_sclk1_1 are extremely high, the gates of u_sclk1_0 and u_sclk1_1 will be turned on, and SCLK will also be high. Thereby realizing the transmission of the data lines 0 and 1. The transmission of the other two MRST and MTSR data lines is the same, and is not repeated here, and the transmission is within the protection scope of the application.

Features described in the embodiments in this specification may be replaced or combined, and identical and similar parts of the embodiments may be referred to each other, where each embodiment focuses on differences from other embodiments. In particular, for a system or system embodiment, since it is substantially similar to a method embodiment, the description is relatively simple, with reference to the description of the method embodiment being made in part. The systems and system embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The SPI time-sharing multiplexing circuit supporting multiple masters and multiple slaves is characterized in that the input end of the SPI time-sharing multiplexing circuit is connected with N master nodes, the output end of the SPI time-sharing multiplexing circuit is connected with M slave nodes, and N and M are integers larger than 1; the SPI time-sharing multiplexing circuit comprises: the SPI chip selection CS multiplexing module, the data channel enabling module and the data channel switching module;

the input end of the data channel enabling module is connected with M chip selection pins of N main nodes, the output end of the data channel enabling module is connected with the control end of the data channel switching module, the data channel enabling module is used for generating corresponding data channel enabling signals according to corresponding main nodes and corresponding slave nodes selected by the SPI chip selection CS multiplexing module, meanwhile, when the corresponding main nodes occupy buses through the chip selection signals, the buses are locked, other main nodes cannot establish data channels, and when the corresponding main nodes occupy the buses in a canceling mode, and after the buses are released, the buses can be locked by any main node;

The control end of the data channel switching module is connected with the output end of the data channel enabling module, the input end of the data channel switching module is respectively connected with an MRST pin, an SCLK pin and an MTSR pin of each master node, the output end of the data channel switching module is respectively connected with each chip selection pin, an MRST pin, an MTSR pin and an SCLK pin of each slave node, and the data channel switching module is used for executing corresponding on and off actions according to a data channel enabling signal of the data channel enabling module, and establishing a data channel between a corresponding master node and a corresponding slave node so as to enable the corresponding master node and the corresponding slave node to perform data transmission;

wherein, SPI chip select CS multiplexing module includes: an OD gate;

each input end of the OD gate circuit is connected with a chip selection pin of each main node respectively; when the chip selection signal of any master node is valid, the chip selection signal of the corresponding slave node is valid, and the selection of the corresponding master node and the corresponding slave node to be communicated is completed;

the OD gate circuit includes: m OD units;

the input end of each OD unit is connected with a corresponding chip selection pin of each main node respectively; the output ends of the OD units are respectively connected with the chip selection pins of the corresponding slave nodes;

The OD unit includes: multiplexing the switching tube and the N diodes;

the other end of the second resistor is connected with a power supply;

the second end of the multiplexing switch tube is grounded.

2. The SPI time division multiplexing circuit supporting multiple masters and multiple slaves of claim 1, wherein said data channel enabling module comprises: n data channel enabling units;

and the locking function ends of the data channel enabling units are connected, so that when the master node and the slave node enabled by any one of the data channel enabling units carry out data transmission, the other data channel enabling units are locked, and the other master node and the slave node inhibit data transmission.

3. The SPI time division multiplexing circuit supporting multiple masters and multiple slaves according to claim 2, wherein said data channel enabling unit comprises: a first enabling switching tube, first to N-1 locking switching tubes, a second enabling switching tube and M diodes;

the other end of the fourth resistor is connected with a power supply.

4. The SPI time division multiplexing circuit supporting multiple masters and multiple slaves of claim 1, wherein said data channel switching module comprises: an MRST data channel switching module and an MTSR & SCLK data channel switching module;

the MTSR & SCLK data channel switching module comprises: n MTSR & SCLK data channel switching units; the control end of each MTSR & SCLK data channel switching unit is used as the control end of the data channel switching module, and the input end of each MTSR & SCLK data channel switching unit is respectively connected with the MTSR pin and the SCLK pin of the corresponding master node; the first output ends of the MTSR and SCLK data channel switching units are connected, and the connection points are respectively connected with SCLK pins of the slave nodes; the second output ends of the MTSR and SCLK data channel switching units are connected, and the connection points are respectively connected with the MTSR pins of the slave nodes;

5. The SPI time division multiplexing circuit supporting multiple masters and multiple slaves according to claim 4, wherein said MTSR & SCLK data channel switching unit comprises: the first switching tube, the second switching tube, the third switching tube and the fourth switching tube;

6. The SPI time division multiplexing circuit supporting multiple masters and multiple slaves according to claim 4, wherein said MRST data channel switching unit comprises: a fifth switching tube and a sixth switching tube;

7. The SPI time division multiplexing circuit supporting multiple masters and multiple slaves according to claim 1, wherein the switching transistors in said data channel enabling module are transistors; the switching tube in the data channel switching module is a MOSFET tube.