CN114760008B - Communication method, device, equipment and storage medium for SPI bus - Google Patents
Communication method, device, equipment and storage medium for SPI bus Download PDFInfo
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Abstract
The application discloses a communication method, a device, equipment and a storage medium for an SPI bus, wherein the method comprises the following steps: performing CRC operation on target data of the data packet to obtain a first check value; starting SPI communication, and sequentially sending each byte data in the target data to the FPGA so that the FPGA carries out CRC operation again on the received current byte data combined with the second check value obtained by CRC operation of the last byte data so as to update the second check value; after the target data are sent, receiving a second check value updated by the FPGA, and judging whether the first check value is consistent with the second check value updated; if yes, judging that the target data received by the FPGA is valid; if not, restarting SPI communication operation until the target data received by the FPGA is judged to be valid. The communication method can know whether the writing is successful or not only through one communication process, and further can realize efficient and reliable communication.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a communication method, apparatus, device, and storage medium for an SPI bus.
Background
The micro control unit (Microcontroller Unit, MCU) and the field programmable gate array (Field Programmable Gate Array, FPGA) are communicated through a serial peripheral interface (Serial Peripheral Interface, SPI) bus, the MCU is used as a communication Master, and the FPGA is used as a communication Slave. When the MCU reads data through the SPI bus, the MCU does not know whether the read data is correct or has error codes; when the MCU writes data through the SPI bus, whether the FPGA of the opposite terminal receives correct data or not is not known, and whether the received data is correct or not is also not known by the FPGA of the opposite terminal, so that unreliable communication is caused.
Currently, in order to solve the above-mentioned problems, a conventional method is to add a cyclic redundancy check (Cyclic Redundancy Check, CRC) mechanism to the communication data. When the data is read, the MCU starts communication, the FPGA calculates CRC_FPGA of the transmitted data and is attached to the back of the data, the MCU calculates CRC_MCU of the data according to the received data after receiving the data, if the CRC_MCU is equivalent to the CRC_FPGA, the read data is correct, otherwise, the read data is incorrect, and the read data flow is required to be started again. When writing data, the MCU calculates CRC_MCU of the transmitted data and is attached to the back of the data, the FPGA calculates CRC_FPGA of the received data after receiving the data, and if the CRC_MCU is equal to the CRC_FPGA, the data received by the FPGA is correct; however, at this time, the MCU does not know whether the FPGA normally receives the data, so the MCU needs to start the data reading process to read the data back, if the read value is equal to the written value, the data writing is successful, otherwise, the data writing fails, and needs to start the data writing process again, for example: if the MCU needs to write the register 0x12 to be 0xaabbccdd, even if the MCU adds CRC into the data, after the MCU finishes transmitting, it needs to read whether the register 0x12 is 0xaabbccdd, to know whether the last write of the data succeeds or fails, that is, it needs to go through a "write data, read back the data" that is, the secondary communication, which is inefficient.
Therefore, how to solve the problem of low efficiency when writing data is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a communication method, apparatus, device and storage medium for an SPI bus, which can realize efficient and reliable communication by only one communication procedure. The specific scheme is as follows:
a communication method for an SPI bus, applied to an MCU, comprising:
performing CRC operation on target data of the data packet to obtain a first check value;
starting SPI communication, and sequentially sending each byte data in the target data to the FPGA, so that the FPGA performs CRC operation again on the received current byte data combined with a second check value obtained by CRC operation of the last byte data, and updates the second check value;
after the target data are sent, receiving the second check value updated by the FPGA, and judging whether the first check value is consistent with the second check value updated;
if yes, judging that the target data received by the FPGA are valid; if not, restarting SPI communication operation until the target data received by the FPGA is judged to be valid.
Preferably, in the communication method for an SPI bus provided by the embodiment of the present invention, when receiving the second check value updated by the FPGA, the method further includes:
the first check value is sent to the FPGA so that the FPGA can judge whether the first check value is consistent with the updated second check value; if yes, judging that the target data received by the FPGA are valid; and if not, discarding the target data received by the FPGA.
Preferably, in the foregoing communication method for an SPI bus according to the embodiment of the present invention, the sending the first check value to the FPGA includes:
and under the guidance of the CLK clock, the first check value is sent to the FPGA through the MOSI pin.
Preferably, in the above communication method for an SPI bus provided by the embodiment of the present invention, the receiving the second check value updated by the FPGA includes:
and under the guidance of the CLK clock, receiving the second check value updated by the FPGA through the MISO pin.
Preferably, in the communication method for an SPI bus provided by the embodiment of the present invention, before performing CRC operation on target data of the data packet, the method further includes:
setting a space for storing the data packets, wherein the space is used for storing the set number of bytes in a memory; the first byte of the data packet stores a Header, and the other bytes except the first byte and the last byte store the target data;
after performing the CRC operation on the target data of the data packet to obtain the first check value, the method further includes:
and placing the first check value behind the target data so that the last byte of the data packet stores the first check value.
Preferably, in the communication method for an SPI bus provided by the embodiment of the present invention, the method further includes:
and receiving one byte of data sent by the FPGA and recording the one byte of data in a receiving buffer area while sending the one byte of data in the target data to the FPGA.
Preferably, in the above communication method for an SPI bus provided by the embodiment of the present invention, the time for the FPGA to perform the CRC operation is less than the SPI bus clock period.
The embodiment of the invention also provides a communication device for the SPI bus, which is applied to the MCU and comprises:
the CRC operation module is used for carrying out CRC operation on target data of the data packet to obtain a first check value;
the sending module is used for starting SPI communication and sequentially sending each byte data in the target data to the FPGA so that the FPGA can perform CRC operation again on the received current byte data combined with a second check value obtained by CRC operation of the last byte data so as to update the second check value;
the receiving module is used for receiving the second check value updated by the FPGA after the target data are sent;
the check value judging module is used for judging whether the first check value is consistent with the updated second check value; if yes, judging that the target data received by the FPGA are valid; if not, restarting SPI communication operation until the target data received by the FPGA is judged to be valid.
The embodiment of the invention also provides communication equipment for the SPI bus, which comprises a processor and a memory, wherein the communication method for the SPI bus provided by the embodiment of the invention is realized when the processor executes a computer program stored in the memory.
The embodiment of the invention also provides a computer readable storage medium for storing a computer program, wherein the computer program realizes the communication method for the SPI bus provided by the embodiment of the invention when being executed by a processor.
From the above technical solution, the communication method for the SPI bus provided by the present invention includes: performing CRC operation on target data of the data packet to obtain a first check value; starting SPI communication, and sequentially sending each byte data in the target data to the FPGA so that the FPGA carries out CRC operation again on the received current byte data combined with the second check value obtained by CRC operation of the last byte data so as to update the second check value; after the target data are sent, receiving a second check value updated by the FPGA, and judging whether the first check value is consistent with the second check value updated; if yes, judging that the target data received by the FPGA is valid; if not, restarting SPI communication operation until the target data received by the FPGA is judged to be valid.
After the data packet is sent, the validity of the target data received by the FPGA can be judged according to the received second check value and the first check value obtained by self operation, so that whether the data is successfully written is known only through one communication process when the data is written, whether the data is successfully written is judged without restarting communication read-back, and high-efficiency and reliable communication can be realized.
In addition, the invention also provides a corresponding device, equipment and a computer readable storage medium for the communication method of the SPI bus, so that the method has more practicability, and the device, the equipment and the computer readable storage medium have corresponding advantages.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only embodiments of the present invention, and other drawings may be obtained according to the provided drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of a communication method for an SPI bus provided by an embodiment of the present invention;
fig. 2 is a schematic diagram of a process of the MCU after transmitting the first byte of the data packet according to the embodiment of the present invention;
FIG. 3 is a schematic diagram of a buffer area of an MCU and an FPGA after the MCU sends the first byte of a data packet according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a process of the MCU after transmitting the second byte of the data packet according to the embodiment of the present invention;
FIG. 5 is a schematic diagram of a buffer area of an MCU and an FPGA after the MCU sends the second byte of the data packet according to the embodiment of the present invention;
fig. 6 is a schematic diagram of a process of the MCU after transmitting the third byte of the data packet according to the embodiment of the present invention;
FIG. 7 is a schematic diagram of a buffer area of an MCU and an FPGA after the MCU sends the third byte of the data packet according to the embodiment of the present invention;
fig. 8 is a schematic diagram of a process of the MCU after transmitting the fourth byte of the data packet according to the embodiment of the present invention;
FIG. 9 is a schematic diagram of a buffer area of an MCU and an FPGA after the MCU sends the fourth byte of the data packet according to the embodiment of the present invention;
fig. 10 is a schematic diagram of a process of the MCU after transmitting the fifth byte of the data packet according to the embodiment of the present invention;
FIG. 11 is a schematic diagram of a buffer area of an MCU and an FPGA after the MCU sends the fifth byte of the data packet according to the embodiment of the present invention;
fig. 12 is a schematic diagram of a process of the MCU after transmitting the sixth byte of the data packet according to the embodiment of the present invention;
FIG. 13 is a schematic diagram of a buffer area of an MCU and an FPGA after the MCU sends the sixth byte of the data packet according to the embodiment of the present invention;
fig. 14 is a schematic structural diagram of a communication device for an SPI bus according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a communication method for SPI bus, as shown in figure 1, comprising the following steps:
s101, performing CRC operation on target data of a data packet by the MCU to obtain a first check value;
it should be noted that, the application scenario of the present invention is that the MCU is to write the target DATA in the DATA packet, where the target DATA is DATA and the length is N. Step S101 is a preparation work, specifically, a first check value crc_mcu of the target DATA is calculated by the MCU.
S102, enabling SPI communication by the MCU, and sequentially sending each byte of data in the target data to the FPGA;
s103, the FPGA performs CRC operation again on the received current byte data and the second check value obtained by combining the received last byte data through CRC operation so as to update the second check value;
specifically, after the MCU sends the first byte DATA 1, the FPGA receives DATA 1 at this time, and before the MCU sends the next byte, the FPGA performs CRC operation on the received DATA 1 to obtain a second check value CRC_TEMP;
and then the MCU repeats the steps for N-1 times, so that the DATA with the length of N can be sent out, and the FPGA performs CRC operation on the basis of the second check value CRC_TEMP every time one byte is received, so that a new second check value CRC_TEMP is obtained.
S104, after the MCU transmits the target data, receiving a second check value updated by the FPGA;
specifically, after the MCU has sent the target DATA, the MCU receives the second check value crc_temp after the last update of the FPGA.
S105, the MCU judges whether the first check value is consistent with the updated second check value;
specifically, the first check value crc_mcu obtained in step S101 is compared with the second check value crc_temp received in step S104.
If yes, go to step S105; if not, re-executing step S102 to step S104;
s106, judging that the target data received by the FPGA are valid.
Specifically, when the MCU determines that the crc_temp and the crc_mcu are consistent, it indicates that the data received by the FPGA is valid, and this communication may be ended. When the MCU determines that crc_temp and crc_mcu are not identical, it is necessary to repeatedly perform steps S102 to S104 until an effective transmission is achieved.
In the communication method for the SPI bus provided by the embodiment of the invention, after the data packet is sent, the validity of the target data received by the FPGA can be judged according to the received second check value and the first check value obtained by self operation, so that whether the data is successfully written is known only through one communication process when the data is written, whether the data is successfully written is judged without restarting communication read-back, and high-efficiency and reliable communication can be realized.
Further, in a specific implementation, in the above communication method for an SPI bus provided by the embodiment of the present invention, when step S104 is executed to receive the second check value updated by the FPGA, the method may further include: the MCU sends a first check value CRC_MCU to the FPGA, the MCU receives a second check value CRC_TEMP, and the FPGA receives the first check value CRC_MCU. The FPGA can judge whether the first check value CRC_MCU is consistent with the second check value CRC_TEMP updated last time; if yes, judging that the target data received by the FPGA is valid; if not, discarding the target data received by the FPGA. That is, when the FPGA determines that the first check value crc_mcu and the last updated second check value crc_temp are identical, it indicates that the data received by the FPGA is valid, and it may be used. When the FPGA judges that the first check value CRC_MCU is inconsistent with the second check value CRC_TEMP updated last time, the received data are invalid and cannot be used, and the received data need to be discarded.
In a specific implementation, the sending, by the MCU, the first check value crc_mcu to the FPGA may include: under the guidance of the CLK clock, the MCU sends a first check value CRC_MCU to the FPGA through the MOSI pin. Similarly, the MCU sequentially sends each byte of data in the target data to the FPGA, or sends each byte of data in the target data to the FPGA through the MOSI pin under the direction of the CLK clock.
In specific implementation, executing step S104 to receive the second check value updated by the FPGA may include: under the guidance of the CLK clock, the second check value updated by the FPGA is received through the MISO pin.
In a specific implementation, in the above communication method for an SPI bus provided by the embodiment of the present invention, before performing the CRC operation on the target data of the data packet in step S101, the method may further include: setting a space for storing data packets, wherein the space is used for storing the data packets and is provided with a set number of bytes in a memory; the first byte of the packet stores the Header and the other bytes except the first and last bytes store the target DATA.
Based on this, after performing the CRC operation on the target data of the data packet in step S101 to obtain the first check value crc_mcu, the method may further include: the first check value crc_mcu is placed after the target data such that the last byte of the data packet stores the first check value crc_mcu. Thus, the last byte of the data packet sent to the FPGA is the first check value crc_mcu.
The communication data formats of the MCU and the FPGA can be as shown in the following table one:
| Header | Data | CRC |
| header, 1 byte | Data field, N bytes | Check code, 1 byte |
It will be appreciated that each packet will have a fixed Header to identify the start of the packet; the next is the Data field Data, and finally the CRC check code, both for checking and for identifying the end of the packet. The total length of one packet is n+2 bytes.
In a specific implementation, in the communication method for an SPI bus provided by the embodiment of the present invention, the method may further include: and when the MCU sends one byte of data in the target data to the FPGA, the MCU receives the one byte of data sent by the FPGA and records the one byte of data in the receiving buffer area. The MCU can also receive each byte data sent by the FPGA through a MISO pin under the direction of the CLK clock. After the MCU receives one byte of data sent by the FPGA, the next byte of data can be sent to the FPGA, so that the accuracy of data transmission is improved.
In a specific implementation, in the communication method for an SPI bus provided by the embodiment of the invention, the time for the FPGA to perform CRC operation is less than the SPI bus clock period. It should be noted that, because the FPGA must calculate the CRC in one SPI clock period, the FPGA can send the calculated CRC from the MISO bus during the transmission of the next byte, so the time for the FPGA to calculate the CRC must be shorter than the SPI bus clock period.
Assuming that the length of the target data is 4 (i.e., n=4), and the length of the data packet is 6, the following describes the above communication method for the SPI bus according to the embodiment of the present invention in detail by using a specific example, and the specific steps are as follows:
step one, when the MCU is to write data into the FPGA, a space of 6 bytes is opened up in the memory for storing the data packet transmitted for the second time, wherein the first byte is a fixed Header, and the next 4 bytes are the target data to be transmitted at the time.
And step two, the MCU calculates a CRC value CRC_MCU of the data field and stores the CRC value CRC_MCU in the position of the 6 th byte.
Step three, the MCU starts SPI communication, and when 1 pulse is sent out on the CLK bus, the MOSI signal sends out 1 bit on the Header, and the MISO signal receives 1 bit sent out by the FPGA; after 8 pulses, the MCU sends the Header out and receives one byte of data from the FPGA, here recorded as Resp [1], as shown in FIG. 2. After this step is completed, the buffer conditions of the MCU and the FPGA are shown in FIG. 3.
And step four, after the MCU continues to send the next byte DATA, namely DATA 1, and sends 8 pulses on the CLK bus, the MCU sends out DATA 1, and simultaneously receives one byte DATA sent by the FPGA, which is recorded as Resp 2, and the FPGA receives DATA 1 and calculates CRC of DATA 1 to obtain CRC_TEMP, as shown in FIG. 4. After this step is completed, the buffer conditions of the MCU and the FPGA are shown in FIG. 5.
And step five, after the MCU continues to send the next byte DATA, namely DATA 2, and sends out 8 pulses on the CLK bus, the MCU sends out DATA 2, and simultaneously receives one byte DATA sent out by the FPGA, which is recorded as Resp 3, and the FPGA receives DATA 2 and calculates the CRC of DATA 2 and CRC_TEMP to obtain a new CRC_TEMP, as shown in FIG. 6. After this step is completed, the buffer conditions of the MCU and the FPGA are shown in FIG. 7.
Step six, the MCU continues to send the next byte DATA, namely DATA 3, after 8 pulses are sent out on the CLK bus, the MCU sends out DATA 3, and simultaneously receives one byte DATA sent out by the FPGA, which is recorded as Resp 4, and the FPGA receives DATA 3 and calculates the CRC of DATA 3 and CRC_TEMP to obtain a new CRC_TEMP, as shown in FIG. 8. After this step is completed, the buffer conditions of the MCU and the FPGA are shown in FIG. 9.
And step seven, after the MCU continues to send the next byte DATA, namely DATA 4, and sends 8 pulses on the CLK bus, the MCU sends out DATA 4, and simultaneously receives one byte DATA sent by the FPGA, which is recorded as Resp 5, and the FPGA receives DATA 4 and calculates the CRC of DATA 4 and CRC_TEMP to obtain a new CRC_TEMP, as shown in FIG. 10. After this step is completed, the buffer conditions of the MCU and the FPGA are shown in FIG. 11.
Step eight, the MCU sends the last byte, namely CRC_MCU, every time 1 pulse is sent out on the CLK bus, the MOSI signal sends out 1 bit on the CRC_MCU, and the MISO signal receives 1 bit of the CRC_TEMP sent out by the FPGA; after 8 pulses, the MCU sends out the CRC_MCU and receives the CRC_TEMP sent by the FPGA; the FPGA receives the crc_mcu as shown in fig. 12. After this step is completed, the buffer conditions of the MCU and the FPGA are shown in FIG. 13.
Step nine, the FPGA judges whether the CRC_MCU and the CRC_TEMP are equal, if not, the error code appears in the transmission process, and then the DATA DATA should not be used continuously and should be discarded; if equal, the data is valid, and can be used.
Step ten, the MCU judges whether the CRC_MCU and the CRC_TEMP are equal, if so, the FPGA is informed of receiving correct data, the writing operation is successful, and the communication can be ended; if not, it is indicated that the FPGA may not receive the correct data, and it is necessary to end the communication and restart a write operation until a successful write operation.
After the steps one to ten are executed, in the last byte of the communication, the MCU sends the CRC_MCU calculated by the MCU, the FPGA sends the CRC_TEMP calculated by the FPGA, and the two sides exchange the CRC value calculated by the FPGA to judge whether the data is transmitted correctly or not, so that the MCU does not need to read back to judge whether the communication is correct or not when writing the data, and the communication efficiency is improved.
Based on the same inventive concept, the embodiment of the invention also provides a communication device for the SPI bus, and since the principle of the device for solving the problem is similar to that of the aforementioned communication method for the SPI bus, the implementation of the device can refer to the implementation of the communication method for the SPI bus, and the repetition is omitted.
In specific implementation, the communication device for SPI bus provided in the embodiment of the present invention, as shown in fig. 14, specifically includes:
the CRC operation module 11 is configured to perform a CRC operation on target data of the data packet to obtain a first check value CRC_MCU;
the sending module 12 is configured to start SPI communication, and send each byte data in the target data to the FPGA in turn, so that the FPGA performs CRC operation again on the received current byte data in combination with the second check value obtained by performing CRC operation on the received last byte data, so as to update the second check value;
the receiving module 13 is used for receiving the second check value updated by the FPGA after the target data are sent;
a check value judging module 14, configured to judge whether the first check value is consistent with the updated second check value; if yes, judging that the target data received by the FPGA is valid; if not, restarting SPI communication operation until the target data received by the FPGA is judged to be valid.
In the communication device for the SPI bus provided by the embodiment of the invention, through interaction of the four modules, after the data packet is sent, validity of the target data received by the FPGA can be determined according to the received second check value and the first check value obtained by calculation of the first check value, so that whether writing is successful is known only by one communication process, whether writing is successful is determined without restarting communication read-back, and efficient and reliable communication can be realized.
In a specific implementation, in the communication device for an SPI bus provided by the embodiment of the present invention, the sending module 12 is further configured to send a first check value to the FPGA, so that the FPGA determines whether the first check value is consistent with the updated second check value; if yes, judging that the target data received by the FPGA is valid; if not, discarding the target data received by the FPGA.
In a specific implementation, in the communication device for an SPI bus provided by the embodiment of the present invention, the communication device may further include:
the space setting module is used for setting a space for storing the data packets, wherein the space is used for setting a set number of bytes in the memory; the first byte of the data packet stores the Header, and the other bytes except the first byte and the last byte store the target data;
the CRC operation module 11 may be further configured to place the first check value at the back of the target data, so that the last byte of the data packet stores the first check value.
In a specific implementation, in the above communication device for an SPI bus provided by the embodiment of the present invention, the receiving module 13 may be further configured to receive one byte of data sent by the FPGA and record the one byte of data in the receiving buffer while sending one byte of data in the target data to the FPGA.
For more specific working procedures of the above modules, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
Correspondingly, the embodiment of the invention also discloses communication equipment for the SPI bus, which comprises a processor and a memory; the communication method for the SPI bus disclosed in the foregoing embodiment is implemented when the processor executes the computer program stored in the memory.
For more specific procedures of the above method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
Further, the invention also discloses a computer readable storage medium for storing a computer program; the computer program, when executed by a processor, implements the previously disclosed communication method for the SPI bus.
For more specific procedures of the above method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. The apparatus, device, and storage medium disclosed in the embodiments are relatively simple to describe, and the relevant parts refer to the description of the method section because they correspond to the methods disclosed in the embodiments.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
In summary, a communication method for an SPI bus provided by an embodiment of the present invention includes: performing CRC operation on target data of the data packet to obtain a first check value; starting SPI communication, and sequentially sending each byte data in the target data to the FPGA so that the FPGA carries out CRC operation again on the received current byte data combined with the second check value obtained by CRC operation of the last byte data so as to update the second check value; after the target data are sent, receiving a second check value updated by the FPGA, and judging whether the first check value is consistent with the second check value updated; if yes, judging that the target data received by the FPGA is valid; if not, restarting SPI communication operation until the target data received by the FPGA is judged to be valid. By using the communication method, after the data packet is sent, the validity of the target data received by the FPGA can be judged according to the received second check value and the first check value obtained by self operation, so that whether the data is successfully written is known only through one communication process when the data is written, whether the data is successfully written is judged without restarting communication readback, and high-efficiency and reliable communication can be realized. In addition, the invention also provides a corresponding device, equipment and a computer readable storage medium for the communication method of the SPI bus, so that the method has more practicability, and the device, the equipment and the computer readable storage medium have corresponding advantages.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing has described in detail the communication method, apparatus, device and storage medium for SPI bus provided by the present invention, and specific examples have been applied herein to illustrate the principles and embodiments of the present invention, the above examples being for the purpose of aiding in the understanding of the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (7)
1. A communication method for an SPI bus, applied to an MCU, comprising:
setting a space for storing data packets, wherein the space is used for storing the data packets and is provided with a set number of bytes in a memory; the first byte of the data packet stores a Header, and the other bytes except the first byte and the last byte store target data of the data packet;
performing CRC operation on the target data to obtain a first check value; placing the first check value behind the target data so that the last byte of the data packet stores the first check value;
starting SPI communication, and sequentially sending each byte data in the target data to the FPGA, so that the FPGA performs CRC operation again on the received current byte data combined with a second check value obtained by CRC operation of the last byte data, and updates the second check value; receiving one byte data sent by the FPGA and recording the one byte data in a receiving buffer area while sending the one byte data in the target data to the FPGA; the time of CRC operation by the FPGA is smaller than the SPI bus clock period;
after the target data are sent, receiving the second check value updated by the FPGA, recording the second check value in a receiving buffer area, and judging whether the first check value is consistent with the second check value updated;
if yes, judging that the target data received by the FPGA are valid; if not, restarting SPI communication operation until the target data received by the FPGA is judged to be valid.
2. A communication method for an SPI bus in accordance with claim 1, further comprising, while said receiving said second check value updated by an FPGA:
the first check value is sent to the FPGA so that the FPGA can judge whether the first check value is consistent with the updated second check value; if yes, judging that the target data received by the FPGA are valid; and if not, discarding the target data received by the FPGA.
3. A communication method for an SPI bus according to claim 2, wherein said sending said first check value to an FPGA comprises:
and under the guidance of the CLK clock, the first check value is sent to the FPGA through the MOSI pin.
4. A communication method for an SPI bus as in claim 1, wherein said receiving said second check value updated by an FPGA comprises:
and under the guidance of the CLK clock, receiving the second check value updated by the FPGA through the MISO pin.
5. A communication device for an SPI bus, characterized by being applied to an MCU, comprising:
the space setting module is used for setting a space for storing the data packets, wherein the space is used for setting a set number of bytes in the memory; the first byte of the data packet stores a Header, and the other bytes except the first byte and the last byte store target data of the data packet;
the CRC operation module is used for carrying out CRC operation on target data of the data packet to obtain a first check value; placing the first check value behind the target data so that the last byte of the data packet stores the first check value;
the sending module is used for starting SPI communication and sequentially sending each byte data in the target data to the FPGA so that the FPGA can perform CRC operation again on the received current byte data combined with a second check value obtained by CRC operation of the last byte data so as to update the second check value; the time of CRC operation performed by the FPGA is smaller than the SPI bus clock period;
the receiving module is used for receiving one byte of data sent by the FPGA and recording the one byte of data in the receiving buffer area while sending the one byte of data in the target data to the FPGA; after the target data are sent, receiving the second check value updated by the FPGA and recording the second check value in a receiving buffer area;
the check value judging module is used for judging whether the first check value is consistent with the updated second check value; if yes, judging that the target data received by the FPGA are valid; if not, restarting SPI communication operation until the target data received by the FPGA is judged to be valid.
6. A communication device for an SPI bus comprising a processor and a memory, wherein the processor implements a communication method for an SPI bus as claimed in any of claims 1 to 4 when executing a computer program stored in the memory.
7. A computer readable storage medium for storing a computer program, wherein the computer program when executed by a processor implements a communication method for an SPI bus as claimed in any of claims 1 to 4.
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