CN114741021A - Storage and computing integrated chip - Google Patents

Abstract

The invention provides an integrated storage and computing chip, comprising: an input signal conversion circuit module for performing amplitude modulation on the low N-bit signal of the input signal and pulse modulation on the high M-bit signal of the input signal; a cell array, connected to the input signal conversion circuit module, for performing operations on the modulated input signal; an output signal conversion circuit module, connected to the storage-calculation integrated cell array, for converting the operation result into a digital output signal; wherein , by splitting the input signal into two parts, the low N-bit signal is represented by the voltage amplitude, and the high M-bit signal is represented by the number of pulses or pulse width, which can effectively reduce the DAC complexity caused by the increase of the number of bits. It is beneficial to realize the miniaturization and low power consumption of the chip.

Description

Storage and computing integrated chip

technical field

The invention relates to the field of semiconductor integrated circuits, in particular to an integrated chip for storage and calculation.

Background technique

In order to solve the bottleneck of the traditional von Neumann computing architecture, the integrated memory-computing chip architecture has received extensive attention. The integrated memory and computing chip uses floating gate transistor devices to perform matrix multiplication and addition operations, usually based on level operation, that is, the input signal is represented by voltage or current amplitude. However, as the number of bits increases, the voltage amplitude will exceed the range, and the voltage Or the current amplitude signal needs a DAC to enter the floating gate transistor array. For example, the number of DACs corresponding to 9bit signals is 512, and the number of DACs corresponding to 8bit signals is 256. As the number of bits of the input signal increases, the number of DACs required is exponential. With the increase of DAC, the area of DAC is large and the power consumption is high, which cannot meet the needs of integration and low cost. If all input signals are represented by pulses, the operation delay will be greatly prolonged, which cannot meet the needs of operation speed.

SUMMARY OF THE INVENTION

In view of the problems in the prior art, the present invention provides an integrated chip for storage and computing, which can at least partially solve the problems in the prior art.

In order to achieve the above object, the present invention adopts the following technical solutions:

In a first aspect, a memory-computing integrated chip is provided, including:

The input signal conversion circuit module is used to perform amplitude modulation on the low N-bit signal of the input signal and pulse modulation on the high M-bit signal of the input signal;

an integrated unit array of storage and calculation, connected to the input signal conversion circuit module, for performing operations on the modulated input signal;

The output signal conversion circuit module is connected to the integrated storage and calculation unit array, and is used for converting the operation result into a digital output signal.

Further, the input signal conversion circuit module includes: a pulse modulation circuit, a DAC circuit and a first MUX circuit;

The output terminals of the pulse modulation circuit and the DAC circuit are respectively connected to the two input terminals of the first MUX circuit; the output terminal of the first MUX circuit is used as the output terminal of the input signal conversion circuit module, and is connected to the output terminal of the first MUX circuit. The input terminal of the integrated unit array of storage and calculation.

Further, the pulse modulation circuit is a pulse number modulation circuit or a pulse width modulation circuit.

Further, the pulse modulation circuit is a digital time conversion circuit or a pre-pulse interception circuit or a pulse counter.

Further, the output signal conversion circuit module includes: a charge integration amplifier circuit, an ADC circuit and a second MUX circuit;

The input end of the second MUX circuit is connected to the output end of the integrated storage and calculation unit array; the output end of the second MUX circuit is respectively connected to the input end of the charge integration amplifier circuit and the ADC circuit.

In a second aspect, a memory-computing integrated chip is provided, including: a low N-bit signal operation module and a high M-bit signal operation module;

The low-N-bit signal operation module is used to perform in-memory operation after amplitude modulation of the low-N-bit signal of the input signal; the high-M-bit signal operation module is used to perform an in-memory operation on the high-M-bit signal of the input signal. In-memory operation is performed after pulse modulation.

Further, the high M-bit signal operation module includes: a pulse modulation circuit, an integrated storage and calculation unit array and an output signal conversion circuit; the output end of the pulse modulation circuit is connected to the input end of the integrated storage and calculation unit array; The output end of the integrated storage and calculation unit array is connected to the input end of the output signal conversion circuit.

Further, the pulse modulation circuit is a pulse number modulation circuit or a pulse width modulation circuit.

Further, the pulse modulation circuit is a digital time conversion circuit or a pre-pulse interception circuit or a pulse counter.

Further, the output signal conversion circuit adopts a charge integration amplifier circuit.

The storage-calculation integrated chip provided by the present invention includes: an input signal conversion circuit module for performing amplitude modulation on the low N-bit signal of the input signal and pulse modulation on the high M-bit signal of the input signal; a storage-calculation integrated unit an array, connected to the input signal conversion circuit module, for performing operations on the modulated input signal; an output signal conversion circuit module, connected to the storage-calculation integrated unit array, for converting the operation result into a digital output signal; wherein, By dividing the input signal into two parts, the low N-bit signal is represented by the voltage amplitude, and the high M-bit signal is represented by the number of pulses or pulse width, which can effectively reduce the problem that the complexity of the DAC increases greatly with the increase of the number of bits. , which is conducive to realizing the miniaturization and low power consumption of the chip, and at the same time, it reduces the operation delay and meets the requirements of high-speed operation occasions.

In order to make the above-mentioned and other objects, features and advantages of the present invention more obvious and easy to understand, the preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are For some embodiments of the present application, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort. In the attached image:

Fig. 1 shows the structural block diagram of the integrated chip of storage and calculation in the embodiment of the present invention;

Fig. 2 shows the working principle of the input signal conversion circuit module in the embodiment of the present invention;

FIG. 3 shows the specific structure of the integrated storage and computing chip in the embodiment of the present invention;

Fig. 4 shows the specific structure of the input signal conversion circuit in the embodiment of the present invention;

Fig. 5 shows the working principle of the input signal conversion circuit in the embodiment of the present invention;

Fig. 6 shows the working principle of another input signal conversion circuit in the embodiment of the present invention;

FIG. 7 shows the specific structure of the output signal conversion circuit in the embodiment of the present invention.

Detailed ways

In order to make those skilled in the art better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only The embodiments are part of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the scope of protection of the present application.

The detailed features and advantages of the present invention are described in detail in the following embodiments, and the content is sufficient to enable any person skilled in the art to understand the technical content of the present invention and implement it accordingly, and according to the contents disclosed in this specification, claims and drawings , any person skilled in the art can easily understand the related objects and advantages of the present invention. The following examples further illustrate the concept of the present invention in further detail, but are not intended to limit the scope of the present invention in any way.

It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

In the existing memory-computing integrated chip, the memory-computing integrated cell array (or called flash array, flash memory cell array or floating gate transistor array, etc.) is used to store weights, and the input digital signal is converted into voltage/current amplitude through DAC, and transmitted to the memory-computing integrated chip. The output of the integrated cell array is also to detect the voltage/current amplitude, which is output through the ADC, resulting in a DAC at the front end of the integrated cell array, and an ADC at the back end, which has a large circuit area, high power consumption and high cost.

In the integrated storage and computing chip provided by the embodiment of the present invention, the input signal is divided into two parts, the low N-bit signal is represented by the voltage amplitude, and the high M-bit signal is represented by the number of pulses (the more the number, the higher the value of the input signal). Larger) or pulse width (the wider the width, the larger the input signal value), which can effectively reduce the problem of the large increase in the DAC complexity caused by the increase of the number of bits, which is conducive to the miniaturization and low power consumption of the chip. At the same time, the operation delay is reduced to meet the needs of high-speed operation occasions.

Fig. 1 shows a structural block diagram of an integrated chip for storing and calculating in an embodiment of the present invention; Fig. 2 shows the working principle of an input signal conversion circuit module in an embodiment of the present invention; The integrated chip includes: an input signal conversion circuit module, an integrated storage and calculation unit array, and an output signal conversion circuit module.

The input signal conversion circuit module is used to perform amplitude modulation on the low N-bit signal of the input signal and pulse modulation on the high M-bit signal of the input signal;

Wherein, with reference to FIG. 2 , the integrated storage and computing unit array has multiple rows, each row has an input terminal, and each input terminal is used to input the digital signal to be calculated, for example, the first row inputs the digital signal X ₁ , and the corresponding input signal conversion The circuit performs amplitude modulation on the low N-bit signal in the digital signal, and pulse modulation on the high M-bit signal of the input signal. The modulated signal is as shown in the figure, and then input to the input terminal of the first row for subsequent operations ;

For example, assuming that the input digital signal is a 9-bit signal, the original scheme can be used for the lower 8 bits, that is, the DAC is used to represent the voltage amplitude, and the upper 1 bit is the number of pulses. If the value of the upper 1 bit is 1, it is used 1 fixed-amplitude pulse.

The integrated unit array of storage and calculation is connected to the input signal conversion circuit module, and is used to perform operation on the modulated input signal;

The output signal conversion circuit module is connected to the integrated storage and calculation unit array, and is used for converting the operation result into a digital output signal.

It is worth noting that the memory-computing integrated cell array is composed of a plurality of memory cells arranged, and the memory cells may be programmable semiconductor devices.

Specifically, the programmable semiconductor device may be a floating gate transistor, a resistive memory device, a phase change memory device, a spin memory device, or the like.

For example, the memory-computing integrated cell array may be a NOR-type flash memory processing array or a NAND-type flash memory processing array.

In an optional embodiment, the memory-computing integrated cell array is composed of a plurality of floating gate transistor arrays.

Those skilled in the art can understand that, in practical applications, part of the flash memory processing arrays in the multiple flash memory processing arrays may be used for computing processing, and all flash processing arrays may be used for computing processing. The input quantity of the flash memory processing arrays depends on the computing requirements Depends. Similarly, for each flash memory processing array, some of its devices can be used for computing processing, and all of its devices can be used for computing processing, and the number of devices invested depends on computing requirements.

In an optional embodiment, referring to FIG. 3 , the input signal conversion circuit module includes a plurality of input signal conversion circuits, and each input signal conversion circuit corresponds to a row of the integrated unit array for storing and calculating the digital input of the row. The low N-bit signal of the signal is amplitude modulated, and the high M-bit signal of the input signal is pulse modulated, and the modulated signal is input into the line storage and calculation integrated unit; in addition, the output signal conversion circuit module includes a plurality of output signal conversion Each output signal conversion circuit corresponds to a column of the integrated unit array, and is used to convert the analog operation result output by the column into a digital output signal.

In an optional embodiment, referring to FIG. 4 , the input signal conversion circuit module includes: a MUX1 pulse modulation circuit, a DAC circuit, and a MUX2;

The input terminal of MUX1 is used to access the digital input signal of the input signal conversion circuit, and the two output terminals of MUX1 are used as selection terminals, which are respectively connected to the DAC and the pulse signal modulation circuit;

The output terminals of the pulse modulation circuit and the DAC circuit are respectively connected to the two input terminals of the MUX2; the output terminal of the MUX2 is used as the output terminal of the input signal conversion circuit, and is connected to the input terminal of the corresponding row of the integrated storage and calculation unit array.

The DAC or pulse signal modulation circuit is selectively turned on by timing control MUX1 and MUX2, so that the DAC is turned on for amplitude modulation when a low N-bit signal is input, and the pulse signal modulation circuit is turned on for pulse modulation when a high M-bit signal is input.

In an optional embodiment, the pulse modulation circuit is a pulse number modulation circuit or a pulse width modulation circuit.

In another optional embodiment, the pulse modulation circuit is a DTC circuit (Digital to Time Converter, Digital to Time Converter) or a pre-pulse interception circuit or a pulse counter.

It is worth noting that, referring to Figure 5, the MUX1 is used for gating. After the low N-bit signal passes through the DAC, the input size is represented by the voltage/current amplitude. When the high M-bit signal passes through the pulse generator, the input pulse signal is used as the input pulse. The number represents the input size.

In an alternative embodiment, the pulse generator may be a pre-pulse truncation circuit or a pulse counter.

In another optional embodiment, the pulse generator can also be a delay locked loop DLL or a digital to time converter. Taking the digital input signal as 101 as an example, through the delay-locked loop, the obtained pulse input signal is a pulse signal whose effective time width of the pulse accounts for 5/8 of the clock period.

FIG. 6 shows the working principle of another input signal conversion circuit in the embodiment of the present invention; as shown in FIG. 6, the MUX1 is used for gating, and after the low N-bit signal passes through the DAC, the input signal is represented by the voltage/current amplitude. size, when the high M-bit signal is used, after the pulse signal passes through the pulse generator, the input pulse width is used to represent the input size.

In an optional embodiment, referring to FIG. 7 , the output signal conversion circuit includes: MUX3, a charge integrating amplifier circuit, an ADC, and a MUX4;

The input terminal of MUX3 is connected to the output terminal of the corresponding column in the integrated storage and calculation unit array, which is used to receive the operation result of the column. The two output terminals of MUX3 are used as selection terminals, which are respectively connected to the input terminal of the charge integration amplifier and the input terminal of the ADC. The output end of the charge integration amplifier and the output end of the ADC are respectively connected to the two input ends of the MUX4, and the output end of the MUX4 is used as the output end of the output signal conversion circuit to output the output signal that converts the operation result of the column into a digital signal .

The embodiment of the present invention also provides an integrated storage and computing chip, including: a low N-bit signal operation module and a high M-bit signal operation module;

The low-N-bit signal operation module is used to perform in-memory operations after amplitude modulation of the low-N-bit signal of the input signal; the high-M-bit signal operation module is used to pulse-modulate the high-M-bit signal of the input signal. in-memory operations.

That is, the memory cell array of the integrated memory and computing chip is divided into multiple sub-arrays in advance to realize different operations. The low-N-bit signal operation module includes one or more sub-arrays. The one or more sub-arrays are used to The N-bit signal part is operated; the high M-bit signal operation module corresponds to one or more sub-arrays, and is used to operate the high M-bit signal signal part; the low N-bit signal operation module and the high M-bit signal The operation result of the operation module is processed in the digital domain of the integrated storage and calculation chip.

Among them, one or more sub-arrays in the low-N-bit signal operation module and the high-M-bit signal operation module including sub-arrays can be implemented by different sub-arrays. In the case of better requirements on chip area and power consumption, low-N - One or more sub-arrays in the bit signal operation module and the high-M-bit signal operation module including sub-arrays can be implemented by the same sub-array, and the sub-array module is controlled to execute the low-N-bit signal in a time-division multiplexing manner operation or high M-bit signal operation.

It is worth noting that a memory-computing integrated chip usually includes a digital domain and an analog domain. The analog domain is mainly an integrated memory-computing unit array that performs analog operations and supporting peripheral analog circuits. The digital domain mainly includes processors, controllers, etc. for digital signals. Processed circuit modules.

In an optional embodiment, the high M-bit signal operation module includes: a pulse modulation circuit, an integrated storage-calculation unit sub-array, and an output signal conversion circuit; an output end of the pulse modulation circuit is connected to an input end of the storage-calculation integrated unit sub-array ; The output end of the integrated storage and calculation unit array is connected to the input end of the output signal conversion circuit.

Among them, the input terminal of the pulse modulation circuit is used to receive the high M-bit signal of the digital signal to be calculated, and the pulse modulation circuit is used to modulate the high M-bit signal into pulse signals of different pulse widths or different numbers of pulses; In an optional embodiment, the pulse modulation circuit is a pulse number modulation circuit or a pulse width modulation circuit.

In another optional embodiment, the pulse modulation circuit is a DTC circuit or a pre-pulse truncation circuit or a pulse counter.

In an optional embodiment, the output signal conversion circuit adopts a charge integration amplifier circuit.

In another optional embodiment, the output signal conversion circuit adopts a pulse counter.

It should be noted that, in the above embodiments, the low-N-bit signal operation module includes a DAC, an integrated storage-calculation unit sub-array, and an ADC; wherein, the input end of the DAC circuit is used to receive the low-N-bit signal of the digital signal to be calculated. bit signal, the output terminal of the DAC is connected to the input terminal of the integrated storage and calculation unit sub-array, and is used to transmit the analog signal after amplitude modulation of the low N-bit signal to the integrated storage and calculation unit sub-array for analog operation; The output end of the integrated unit sub-array is connected to the input end of the ADC, and the ADC is used to convert the analog operation result into a digital signal.

An embodiment of the present invention also provides an electronic device, including the above-mentioned integrated storage and computing chip.

For example, the electronic device may be a mobile phone, a computer, a tablet computer, a wearable device, etc., which is not limited in this embodiment of the present invention.

Electronic equipment can be miniaturized and low power consumption by using integrated memory and computing chips.

In the present invention, the principles and implementations of the present invention are described by using specific embodiments, and the descriptions of the above embodiments are only used to help understand the method and the core idea of the present invention; The idea of the invention will have changes in the specific implementation and application scope. To sum up, the content of this specification should not be construed as a limitation to the present invention.

It should also be noted that the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device comprising a series of elements includes not only those elements, but also Other elements not expressly listed, or which are inherent to such a process, method, article of manufacture, or apparatus are also included. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, article of manufacture, or device that includes the element.

Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for related parts, please refer to the partial descriptions of the method embodiments.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention in any form. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art, Within the scope of not departing from the technical solution of the present invention, when the technical content disclosed above can be used to make some changes or modifications to equivalent embodiments with equivalent changes, but any content that does not depart from the technical solution of the present invention, according to the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solutions of the present invention.

Claims (10)

1. An integrated chip for storing and computing, characterized in that, comprising: The input signal conversion circuit module is used to perform amplitude modulation on the low N-bit signal of the input signal and pulse modulation on the high M-bit signal of the input signal; an integrated unit array of storage and calculation, connected to the input signal conversion circuit module, for performing operations on the modulated input signal; The output signal conversion circuit module is connected to the integrated storage and calculation unit array, and is used for converting the operation result into a digital output signal. 2. The integrated storage and computing chip according to claim 1, wherein the input signal conversion circuit module comprises: a pulse modulation circuit, a DAC circuit and a first MUX circuit; The output terminals of the pulse modulation circuit and the DAC circuit are respectively connected to the two input terminals of the first MUX circuit; the output terminal of the first MUX circuit is used as the output terminal of the input signal conversion circuit module, and is connected to the output terminal of the first MUX circuit. The input terminal of the integrated unit array of storage and calculation. 3 . The integrated storage and computing chip according to claim 2 , wherein the pulse modulation circuit is a pulse number modulation circuit or a pulse width modulation circuit. 4 . 4 . The integrated storage and calculation chip according to claim 3 , wherein the pulse modulation circuit is a digital time conversion circuit, a pre-pulse interception circuit, or a pulse counter. 5 . 5. The integrated storage and computing chip according to claim 1, wherein the output signal conversion circuit module comprises: a charge integration amplifier circuit, an ADC circuit and a second MUX circuit; The input end of the second MUX circuit is connected to the output end of the integrated storage and calculation unit array; the output end of the second MUX circuit is respectively connected to the input end of the charge integration amplifier circuit and the ADC circuit. 6. An integrated chip for storage and calculation, characterized in that it comprises: a low N-bit signal operation module and a high M-bit signal operation module; The low-N-bit signal operation module is used to perform in-memory operation after amplitude modulation of the low-N-bit signal of the input signal; the high-M-bit signal operation module is used to perform an in-memory operation on the high-M-bit signal of the input signal. In-memory operation is performed after pulse modulation. 7. The integrated storage and calculation chip according to claim 6, wherein the high M-bit signal operation module comprises: a pulse modulation circuit, an integrated storage and calculation unit array and an output signal conversion circuit; The output terminal is connected to the input terminal of the integrated storage and calculation unit array; the output terminal of the integrated storage and calculation unit array is connected to the input terminal of the output signal conversion circuit. 8 . The integrated storage and computing chip according to claim 7 , wherein the pulse modulation circuit is a pulse number modulation circuit or a pulse width modulation circuit. 9 . 9 . The integrated storage and calculation chip according to claim 7 , wherein the pulse modulation circuit is a digital time conversion circuit, a pre-pulse interception circuit, or a pulse counter. 10 . 10 . The integrated storage and calculation chip according to claim 7 , wherein the output signal conversion circuit adopts a charge integration amplifier circuit. 11 .

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