CN114695253A - Method for improving etching process window of metal gate contact hole - Google Patents

Abstract

The invention provides a method for improving a metal gate contact hole etching process window, which comprises the steps of providing a substrate, forming a plurality of device areas on the substrate, forming a metal gate in each device area, forming an interlayer dielectric layer on the substrate, and grinding the interlayer dielectric layer to expose the metal gate; forming a diffusion barrier layer on the interlayer dielectric layer and the metal gate; forming an etching barrier layer and an isolation layer which are overlapped from bottom to top on the diffusion barrier layer; forming a photoresist layer on the isolation layer, and opening the photoresist layer by photoetching to expose the region except the metal gate on at least one device region; removing the exposed isolation layer and the etching barrier layer and the diffusion barrier layer below the exposed isolation layer; removing the photoresist layer, and then continuously forming an interlayer dielectric layer on the substrate; and etching the interlayer dielectric layer to form contact holes respectively communicated with the source region, the drain region and the metal gate. The invention does not change the matching process conditions of the interlayer dielectric layer, the contact hole etching and the like, improves the process window of the through hole etching and improves the product reliability.

Description

Method for improving metal gate contact hole etching process window

technical field

The present invention relates to the field of semiconductor technology, in particular to a method for improving the etching process window of a metal gate contact hole.

Background technique

28nm high-voltage high-K metal gate process platform, as shown in Figure 1, there are three operating voltage regions in the chip: low-voltage region (0.9V), medium-voltage region (8V) and high-voltage region (32V); ) There is a metal gate (MG) with a larger size. After the aluminum chemical mechanical planarization process, the wear of the metal gate in the high voltage region is more serious than that in the low voltage region and the medium voltage region. Therefore, during the subsequent contact hole etching, the low voltage region and The etching of the contact hole in the medium voltage region stops above the metal gate, but the metal gate in the high voltage region has the risk of being etched through the contact hole due to the small wear thickness, which has serious side effects on the performance of the product, such as a reduction in rated voltage, reliable Decreased sex, etc.

Therefore, there is a need for a method for improving the etching process window of the metal gate contact hole, so as to reduce the risk that the metal gate in the high voltage region is etched through the contact hole due to the smaller wear thickness.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for improving the etching process window of the metal gate contact hole, which is used to solve the problem that the wear of the metal gate in the high voltage region in the prior art is more serious, so the subsequent contact holes are During etching, the etching of the contact holes in the low-voltage region and the medium-voltage region stops above the metal gate, but the metal gate in the high-voltage region has a risk of being etched through by the contact hole due to the smaller thickness of wear.

In order to achieve the above object and other related objects, the present invention provides a method for improving the etching process window of a metal gate contact hole, comprising:

Step 1. Provide a substrate, a plurality of device regions are formed on the substrate, each of the device regions is formed with a metal gate, and a plurality of the device regions and the metal gate are formed on the substrate to cover the plurality of device regions and the metal gate the interlayer dielectric layer, and then grinding the interlayer dielectric layer to expose the metal gate;

Step 2, forming a diffusion barrier layer on the ground interlayer dielectric layer and the exposed metal gate;

Step 3, forming an etching barrier layer and an isolation layer on the etching barrier layer in sequence on the diffusion barrier layer;

Step 4, forming a photoresist layer on the isolation layer, and opening the photoresist layer by photolithography so that the region other than the metal gate on at least one of the device regions is exposed;

Step 5, removing the exposed isolation layer and the etching barrier layer and the diffusion barrier layer below it;

Step 6, removing the photoresist layer, and then continuing to form an interlayer dielectric layer covering a plurality of the device regions and the metal gate on the substrate;

Step 7: Etch the interlayer dielectric layer to form a contact hole connected to the source region, the drain region and the metal gate of each device region.

Preferably, the substrate in step 1 is a silicon substrate.

Preferably, the material of the interlayer dielectric layer in steps 1 and 6 is silicon dioxide.

Preferably, the material of the metal grid in step 1 is aluminum.

Preferably, the polishing in step 1 adopts a chemical mechanical planarization process.

Preferably, the material of the diffusion barrier layer in step 2 is titanium nitride.

Preferably, the material of the etching barrier layer in step 3 is silicon nitride.

Preferably, the material of the diffusion barrier layer in step 3 is silicon dioxide.

Preferably, in step 1, the plurality of device regions include a low-voltage device region, a medium-voltage device region and a high-voltage device region.

Preferably, at least one of the device regions in step 4 includes a high-voltage device region.

Preferably, the size of the metal gate on the high voltage device region is larger than the size of the metal gate in the medium voltage device region and the low voltage device region.

Preferably, in step 5, dry etching is used to remove the exposed isolation layer and the etching barrier layer below it, and then wet etching is used to remove the diffusion barrier layer.

As described above, the method for improving the etching process window of the metal gate contact hole of the present invention has the following beneficial effects:

The invention can prevent the thin metal gate from being etched and etched through by the through hole under the condition that the wear of the large-sized metal gate is weakly improved, and the modification is small on the basis of the original process, and the interlayer dielectric layer and the contact hole are not changed. Etching and other supporting process conditions, thereby increasing the process window of through hole etching and improving product reliability.

Description of drawings

FIG. 1 shows a schematic structural diagram of a chip in the existing structure;

FIG. 2 is a schematic diagram showing the structure of the substrate after forming the etching barrier layer of the present invention;

Fig. 3 shows the photolithography schematic diagram of the present invention;

FIG. 4 is a schematic diagram showing the continuous formation of an interlayer dielectric layer according to the present invention;

FIG. 5 is a schematic diagram showing the formation of contact holes according to the present invention;

Figure 6 shows a schematic diagram of the process flow of the present invention.

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Referring to FIG. 6, the present invention provides a method for improving the etching process window of the contact hole of the metal gate 15, including:

Step 1, referring to FIG. 2, a substrate 10 is provided, a plurality of device regions are formed on the substrate 10, each device region is formed with a metal gate 15, and a plurality of device regions and a metal gate 15 are formed on the substrate 10 covering the plurality of device regions The interlayer dielectric layer 14 is then ground, and then the interlayer dielectric layer 14 is ground to expose the metal gate 15;

In an optional implementation manner, the substrate 10 in step 1 is a silicon substrate 10. Multiple device regions can be formed on the silicon substrate 10, and then the structures in each device region can be formed. After the epitaxial layer is formed on the bottom 10, a plurality of device regions are formed on the epitaxial layer.

In an optional embodiment, the material of the interlayer dielectric layer 14 in steps 1 and 6 is silicon dioxide.

In an optional embodiment, the material of the metal grid 15 in step 1 is aluminum.

In an optional embodiment, in step 1, the plurality of device regions include a low-voltage device region, a medium-voltage device region and a high-voltage device region, and the metal gate 15 in the high-voltage device region is easily worn during grinding, resulting in the formation of contact holes later The metal gate 15 is etched through at all times.

In an optional embodiment, the polishing in step 1 adopts a chemical mechanical planarization process.

Step 2, forming a diffusion barrier layer 11 on the ground interlayer dielectric layer 14 and the exposed metal gate 15;

In an optional embodiment, the material of the diffusion barrier layer 11 in step 2 is titanium nitride, which can be used to prevent the diffusion of the metal gate 15 in the subsequent process flow.

Step 3, sequentially forming an etching barrier layer 12 and an isolation layer 13 on the etching barrier layer 12 on the diffusion barrier layer 11, and the etching barrier layer 12 is used to protect the metal gate 15 when the contact holes are formed later , so as to prevent the metal gate 15 from being etched through, and the isolation layer 13 is used to isolate the etching barrier layer 12 and the subsequent photoresist layer 16;

In an optional embodiment, the material of the etching barrier layer 12 in step 3 is silicon nitride.

In an optional embodiment, the material of the diffusion barrier layer 11 in step 3 is silicon dioxide.

In an optional embodiment, the diffusion barrier layer 11 made of titanium nitride also serves as a bonding layer with the etch barrier layer 12 made of silicon nitride.

Step 4, referring to FIG. 3 , a photoresist layer 16 is formed on the isolation layer 13, and the photoresist layer 16 is opened by photolithography so that the area other than the metal gate 15 on at least one device area is exposed;

In an optional implementation manner, at least one device region in step 4 includes a high-voltage device region, and if the metal gates in other device regions are also larger in size, other device regions may also be included.

In an optional embodiment, the size of the metal gate 15 on the high-voltage device region is larger than the size of the metal gate 15 in the medium-voltage device region and the low-voltage device region, which is likely to cause more wear during chemical mechanical planarization polishing .

Step 5, remove the exposed isolation layer 13 and the etching barrier layer 12 and diffusion barrier layer 11 below it, so that the etching barrier layer 12, diffusion barrier layer 11 and isolation layer 13 on the metal gate 15 on the high voltage device area remain ;

In an optional embodiment, in step 5, dry etching is used to remove the exposed isolation layer 13 and the etching barrier layer 12 below it, and then the diffusion barrier layer 11 is removed by wet etching.

Step 6, please refer to FIG. 4 , remove the photoresist layer 16, usually by an ashing process and wet cleaning, and then continue to form an interlayer dielectric covering a plurality of device regions and the metal gate 15 on the substrate 10 layer 14;

Step 7, referring to FIG. 5, the interlayer dielectric layer 14 is etched to form contact holes connected to the source region, the drain region and the metal gate 15 in each device region. Since the metal gate 15 on the high-voltage device region is formed with The etching barrier layer 12 reduces the risk of the metal gate 15 being etched through when the contact hole is formed.

It should be noted that the diagrams provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, and the drawings only show the components related to the present invention rather than the number, shape and number of components in actual implementation. For dimension drawing, the type, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complicated.

To sum up, the present invention can prevent the thin metal gate from being etched and etched through by the through hole under the condition that the wear of the large-sized metal gate is weakly improved, and the modification is small on the basis of the original process, and the interlayer is not changed. Dielectric layer, contact hole etching and other supporting process conditions, so as to improve the process window of through hole etching and improve product reliability. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (12)

1. A method for improving the etching process window of a metal gate contact hole is characterized by at least comprising the following steps:

providing a substrate, wherein a plurality of device areas are formed on the substrate, a metal gate is formed in each device area, an interlayer dielectric layer covering the device areas and the metal gate is formed on the substrate, and then the interlayer dielectric layer is ground to expose the metal gate;

forming a diffusion barrier layer on the ground interlayer dielectric layer and the exposed metal gate;

sequentially forming an etching barrier layer and an isolation layer on the etching barrier layer on the diffusion barrier layer;

forming a photoresist layer on the isolation layer, and opening the photoresist layer by photoetching to expose the region except the metal gate on at least one device region;

fifthly, removing the exposed isolation layer, the etching barrier layer and the diffusion barrier layer below the isolation layer;

removing the photoresist layer, and then continuously forming an interlayer dielectric layer covering the plurality of device areas and the metal gates on the substrate;

and seventhly, etching the interlayer dielectric layer to form contact holes communicated with the source region, the drain region and the metal gate of each device region.

2. The method for improving the etching process window of the metal gate contact hole according to claim 1, wherein: the substrate in the first step is a silicon substrate.

3. The method for improving the etching process window of the metal gate contact hole according to claim 1, wherein: and in the first step and the sixth step, the interlayer dielectric layer is made of silicon dioxide.

4. The method for improving the etching process window of the metal gate contact hole according to claim 1, wherein: and the metal grid in the first step is made of aluminum.

5. The method for improving the etching process window of the metal gate contact hole according to claim 1, wherein: and the grinding in the first step adopts a chemical mechanical planarization process.

6. The method for improving the etching process window of the metal gate contact hole according to claim 1, wherein: and the material of the diffusion impervious layer in the second step is titanium nitride.

7. The method for improving the etching process window of the metal gate contact hole according to claim 1, wherein: and the material of the etching barrier layer in the third step is silicon nitride.

8. The method for improving the etching process window of the metal gate contact hole according to claim 1, wherein: the material of the diffusion impervious layer in the third step is silicon dioxide.

9. The method for improving the etching process window of the metal gate contact hole according to claim 1, wherein: in the first step, the plurality of device areas comprise a low-voltage device area, a medium-voltage device area and a high-voltage device area.

10. The method for improving the etching process window of the metal gate contact hole according to claim 9, wherein: at least one of the device regions in step four comprises a high voltage device region.

11. The method for improving the etching process window of the metal gate contact hole according to claim 10, wherein: the size of the metal gate on the high-voltage device region is larger than the size of the metal gate in the medium-voltage device region and the low-voltage device region.

12. The method for improving the etching process window of the metal gate contact hole according to claim 1, wherein: and fifthly, removing the exposed isolation layer and the etching barrier layer below the isolation layer by adopting dry etching, and then removing the diffusion barrier layer by adopting wet etching.

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