CN114679415B - Non-blocking banyan network meeting AXI5-Lite protocol standard - Google Patents

Abstract

The disclosed non-blocking banyan network meeting AXI5-Lite protocol standard includes multiple switching units forming switching network, and 5 kinds of dual transmission channels without interference are set inside; a buffer unit group is correspondingly arranged at each input port of the switching network, and the buffer units of different numbers and different types are arranged in the buffer unit groups of the host and the slave and are used for receiving signals from the host and the slave, storing and transmitting information packets; the buffer unit is provided with a plurality of buffer queues, and the number of the buffer queues is the same as that of the receiving end; a scheduler is arranged in the dual transmission channel, and a priority is allocated to the information packets to be transmitted in the buffer queue; the data information package in the transmission channels is provided with effective control bits and subsequent data bits, and the transmission bus width of each transmission channel is consistent with the length of the data information package. The non-blocking banyan network meeting the AX I5-LIte protocol standard ensures non-blocking, high-performance and low-delay transmission of data resources and can reduce the complexity of the network.

Description

A non-blocking banyan network that meets the AXI5-Lite protocol standard

Technical Field

The present application relates to the field of communications, and mainly to a non-blocking banyan network that meets the AXI5-Lite protocol standard.

Background technique

As the demand for communication between electronic devices continues to expand, various industries have increasing requirements for the rate, delay and accuracy of resource data transmission. The Internet determines the performance of electronic systems to a certain extent. A good Internet must meet the following requirements: on the one hand, it can enable each part of the resources to be mobilized with high performance, low latency and non-blocking; on the other hand, it can ensure that the resources occupied by the Internet itself are not large.

Only when the switching network is matched with the appropriate communication protocol can the various modules be linked efficiently, and the advantages of the switching network and the communication protocol can be highlighted. Therefore, how to design a good Internet network through the combination of the switching network and the communication protocol has become one of the focuses of the development of communication technology. The traditional switching network that meets the AXI protocol standard has problems such as high blocking rate and high network transmission delay. Although the networks with low blocking rates such as crossbar and clos can effectively transmit data, their network complexity is high. Using separate switching networks to implement channels with different protocols makes the switching network more complex, and it cannot achieve non-blocking effect, and even data packet loss may occur.

The AXI5-Lite bus structure is simpler, the internal logic is easier to understand, easy to modify and verify, AXI5-Lite allows variable data width transmission, can achieve out-of-order transmission, can simplify communication transmission, and has strong compatibility. The banyan network is a representative type of multi-level interconnected network. Its advantages are simple structure, small number of intermediate nodes, low network complexity, and easy expansion.

Therefore, a new network structure is needed to combine the AXI5-Lite bus protocol with the banyan network, so that it can be very well applied to various transmissions requiring high performance and low latency, and ensure efficient transmission between various communication modules.

Summary of the invention

In view of the problems in the prior art, the present application proposes a non-blocking banyan network that meets the AXI5-Lite protocol standard, including:

A plurality of switching units constituting a switching network, wherein each switching unit comprises five pairs of dual transmission channels;

A host I/O port cache unit group is arranged between the switching network and the host to cache data packets from the host to be sent to the switching network, wherein each host I/O port cache unit in the host I/O port cache unit group has a plurality of host cache queues inside.

A slave I/O port cache unit group is arranged between the switching network and the slave to cache data packets from the slave to be sent to the switching network, wherein each of the slave I/O port cache units in the slave I/O port cache unit group has multiple slave cache queues inside.

The dual transmission channel can meet the data transmission between multiple hosts and multiple slaves. By setting the host I/O port cache unit group and the slave I/O port cache unit group, the data that cannot be transmitted immediately is stored, thereby solving the problem of banyan network congestion caused by the inability to transmit information packets that apply for transmission at the same time at all times. Each cache unit has multiple cache queues inside, and each cache queue stores information packets from the same channel and the same input port to different destinations, thereby preventing the occurrence of head-of-line blocking.

In an optional embodiment, the host I/O port cache unit group includes three types of cache units respectively used for reading address information packets, writing address information packets and writing data information packets, and the slave I/O port cache unit group includes two types of cache units respectively used for reading data information packets and response information packets.

The setting method of the cache units in the host I/O port cache unit group and the slave I/O port cache unit group meets the communication requirements of the host and the slave, solves the problem that the efficiency will be slow when multiple different types of information packets transmitted in the same direction are transmitted using one network, and also greatly reduces hardware consumption.

In an optional embodiment, the host I/O port buffer unit group accepts a ready signal directly sent from the slave, and the slave I/O port buffer unit group accepts a ready signal directly sent from the host.

The host I/O port buffer unit group and the slave I/O port buffer unit group can determine whether the slave and the host are still in operation through the received ready signal, and prohibit or allow the information packet to be transmitted to the switching network according to the ready signal.

In an optional embodiment, the number of the plurality of host cache queues is equal to the number of slaves connected to the switching network, and the number of the plurality of slave cache queues is equal to the number of hosts connected to the switching network.

The number of cache queues is the same as the number of externally connected hosts and slaves, which greatly improves the transmission efficiency of information packets and avoids blocking.

In a further optional embodiment, the five pairs of dual transmission channels include five pairs of dual transmission channels respectively used for writing data, writing addresses, reading data, reading addresses and responses.

The five pairs of dual transmission channels in the switching unit correspond to five different channels of the AXI5-Lite protocol, giving full play to the advantages of the AXI protocol.

In a further optional embodiment, the banyan network further comprises five schedulers connected to the switching network, and the five schedulers respectively assign priorities to the information packets to be transmitted in the cache queue for five pairs of dual transmission channels.

Priority is assigned based on the delay of each storage queue head packet and the remaining storage data space of the storage queue. The smaller the remaining storage space of the specified queue and the longer the delay of the storage queue head packet, the higher the priority, and the internally stored packets should be transmitted first. By setting priorities for scheduling, the switching network transmission can achieve high performance and low latency.

In an optional embodiment, for a write address channel and a read address channel, the data information packet includes a 7-bit valid control signal bit and a control signal corresponding to the valid control signal bit;

For a write response channel, the data information packet includes 5-bit valid control signal bits and a control signal corresponding to the 5-bit valid control signal bits.

In a further optional embodiment, for a channel for writing data and a channel for reading data, the data information packet includes a 4-bit valid control signal bit and a control signal corresponding to the 4-bit valid control signal bit, and the data information packet also includes a data signal, and the size of the valid data of the data signal is determined by the corresponding control signal.

In an optional embodiment, the control signal and the data signal are organized into a complete information packet for transmission. Since each bit in the information packet corresponds to a signal with a fixed function, the information packet only needs to be separated by bit and transmitted to the corresponding receiving end interface when it is output, and the effective control signal bit is used to determine which control information is effective, and the control signal is used to determine which data signal is effective.

The effective control signal bit is set in front of each data packet. For the five pairs of channels, the effective control signal bit is different from the sum of the control signal bits, and only the write data packet and the read data packet have data signal bits. Therefore, the packet size of each channel is different. By setting the effective control signal bit, the receiving end is told which signals can be directly skipped, ensuring the convenience of packet reading.

In an optional embodiment, each transmission channel of the five pairs of dual transmission channels has a transmission bus width consistent with the length of the data packet. Since there are data signals in the read data packet and the write data packet, the length of the packet is longer, and the transmission width of the read data transmission channel and the write data transmission channel is correspondingly wider.

After integration, the bus width and packet length of each channel in the banyan network are kept consistent, ensuring that the packets are transmitted in parallel and can be transmitted in one go.

In an optional embodiment, the host I/O port cache unit group receives a valid signal from the host to confirm whether the host wants to send data, and the host I/O port cache unit group gives the host a ready signal that is always set to 1, so that the data is directly transmitted to the host cache unit group, and the slave I/O port cache unit group receives a valid signal from the slave to confirm whether the slave wants to send data, and the slave I/O port cache unit group gives the slave a ready signal that is always set to 1, so that the data is directly transmitted to the slave cache unit.

In an optional embodiment, when an information packet is transmitted from a host to a slave, once an output port of the switching network detects that the information packet has passed, the output port of the switching network gives a valid signal to the destination slave corresponding to the channel of the information packet;

When a packet is transmitted from a slave to a host, once the output port of the switching network detects that the packet has passed, the output port of the switching network gives the destination host a valid signal for the channel corresponding to the packet.

In a further embodiment, the output port of the switching network reads the phase OR result of the valid control signal bit to determine whether an information packet passes through. If the phase OR result of the valid control signal bit is 1, it is determined that an information packet passes through, and a valid signal set to 1 is given to the receiving end.

The cache unit group gives the sender a ready signal that is always set to 1. At the same time, the cache unit group receives a valid signal from the sender. When the valid signal bit of the sender's transmission channel is 1, the cache unit of the corresponding transmission channel knows that the channel's sending device is going to send data, so that the cache unit group can directly process the signal received from the sender and aggregate it into information packets and store them in the corresponding internal queue without considering the status of the receiving device, so that the sender can continuously send data when the receiving end does not respond.

The cache unit will connect the information packets stored in the corresponding internal queue to the network input port only when it determines that the ready signal of the receiving end is 1. Once the information packet from the sending end in the corresponding internal queue is selected for transmission, when the information packet passes through the output port of the switching network, the output port of the switching network gives the receiving end a valid signal that sets the transmission channel corresponding to the information packet to 1, so that the information packet stored in the internal queue of the cache unit can be successfully transmitted to the receiving end. The present invention proposes a non-blocking banyan network that meets the AXI5-Lite protocol standard, including multiple switching units constituting a switching network, and 5 mutually non-interfering dual transmission channels are arranged inside; a cache unit group is arranged corresponding to each input port of the switching unit, and different numbers and types of cache units are arranged in the cache unit group, which are used to receive signals from a host and a slave, store and transmit information packets, and the cache unit is provided with multiple cache queues, and the number of cache queues is the same as that of the transmitting end; a scheduler is arranged in the dual transmission channel, which assigns priorities to the information packets to be transmitted in the cache queue, and sets effective control bits and subsequent data bits for the data information packets in the transmission channel, and each transmission channel has a transmission bus width consistent with the length of the data information packet; the basic unit of the banyan network is re-established, which greatly reduces the consumption of hardware. The present invention ensures the non-blocking, high-performance, and low-latency transmission of data resources, and can reduce the complexity of the network itself.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and are used together with the description to explain the principles of the present invention. It will be easy to recognize other embodiments and many expected advantages of the embodiments because they become better understood by reference to the following detailed description. The elements of the accompanying drawings are not necessarily to scale with each other. The same reference numerals refer to corresponding similar parts.

FIG. 1a shows a block diagram of a banyan basic switching unit according to an embodiment of the present invention;

FIG. 1 b shows a structural diagram of a banyan-modified exchange unit according to an embodiment of the present invention;

FIG2 shows a schematic diagram of an example working principle of a switching network according to an embodiment of the present invention;

FIG3 shows a detailed structural diagram of a banyan according to an embodiment of the present invention;

FIG4 shows an example diagram of components of a write data and read data information packet according to an embodiment of the present invention;

FIG5 shows an example diagram of AXI5-Lite protocol compatibility according to an embodiment of the present invention;

FIG. 6 shows a schematic diagram of the structure of a computer system 600 of an electronic device according to an embodiment of the present invention.

Detailed ways

The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It should also be noted that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

Figure 1a shows a structural diagram of a banyan basic switching unit according to an embodiment of the present invention. As shown in Figure 1a, when an information packet passes through the switching unit of the basic banyan network, it can go from input port 0 to output port 0, from input port 0 to output port 1, from input port 1 to output port 0, or from input port 1 to output port 1, which can satisfy the successful transmission of information packets input from different input ports to different output ports.

However, this simple switching unit can only meet the transmission requirements of a unidirectional transmission channel. If the AXI protocol is to be transmitted smoothly, five such ordinary switching units are required to form a banyan network.

FIG1b shows a structural diagram of a banyan-modified switching unit according to an embodiment of the present invention, where five common switching units are assembled on one switching unit to satisfy five pairs of AXI channels with different attributes in different directions. In a specific embodiment, the write data channel is configured to transmit from left to right, the input port is configured with input port 0 and input port 1, marked as W0 and W1 respectively, and the output port is configured with output port 0 and output port 1, marked as W′0 and W′1 respectively, W0 can freely transmit information packets to W′0 or W′1 to the right, and W1 can freely transmit information packets to W′0 or W′1 to the right;

The write address channel is set to transmit from left to right. The input port is set to input port 0 and input port 1, marked as AW0 and AW1 respectively. The output port is set to output port 0 and output port 1, marked as AW′0 and AW′1 respectively. AW0 can freely transmit information packets to AW′0 or AW′1 to the right, and AW1 can freely transmit information packets to AW′0 or AW′1 to the right.

The read address channel is set to transmit from left to right. The input port is set to input port 0 and input port 1, marked as AR0 and AR1 respectively. The output port is set to output port 0 and output port 1, marked as AR′0 and AR′1. AR0 can freely transmit information packets to AR′0 or AR′1 to the right, and AR1 can freely transmit information packets to AR′0 or AR′1 to the right.

The read data channel is set to transmit from right to left. The input port is set to input port 0 and input port 1, marked as R0 and R1 respectively. The output port is correspondingly set to output port 0 and output port 1, marked as R′0 and R′1. R0 can freely transmit information packets to R′0 or R′1 to the left, and R1 can freely transmit information packets to R′0 or R′1 to the left.

The write response channel is set to transmit from right to left. The input port is set with input port 0 and input port 1, marked as Res0 and Res1 respectively. The output port is correspondingly set with output port 0 and output port 1, marked as Res′0 and Res′1. Res0 can freely transmit information packets to Res′0 or Res′1 to the left, and Res1 can freely transmit information packets to Res′0 or Res′1 to the left.

Five pairs of dual transmission channels pass through one switching unit without interfering with each other. Compared with a banyan switching network composed of ordinary switching units, which requires five switching units, the switching unit shown in FIG1b greatly reduces the hardware consumption.

FIG2 shows a schematic diagram of a working example of a switching network according to an embodiment of the present invention. As shown in FIG1 , four host devices and four slave devices exchange data using a banyan switching network based on the AXI5-Lite protocol. The four host devices are respectively host 11, host 12, host 13 and host 14, and the four slave devices are respectively slave 21, slave 22, slave 23 and slave 24.

In a specific embodiment, the host device and the slave device are directly connected to the ports corresponding to the transport channel of the switching network when acting as receiving ends.

In a specific embodiment, when the host device and the slave device act as sending ends, a host I/O port cache unit group and a slave I/O port cache unit group are set at the input port, which are respectively host I/O port cache unit group 31, host I/O port cache unit group 32, host I/O port cache unit group 33, host I/O port cache unit group 34, slave I/O port cache unit group 41, slave I/O port cache unit group 42, slave I/O port cache unit group 43, and slave I/O port cache unit group 44.

In a specific embodiment, since there are three types of AXI channels from the host to the slave, the host I/O port cache unit group includes three different cache units for storing read addresses, write addresses and write data packets respectively.

In a specific embodiment, since there are two AXI channels from the slave to the host and the transmission is performed from right to left, the slave I/O port cache unit group includes two different cache units, which respectively store response packets and read data packets.

In a specific embodiment, host 11 is connected to host I/O port cache unit group 31, host 12 is connected to host I/O port cache unit group 32, host 13 is connected to host I/O port cache unit group 33, and host 14 is connected to host I/O port cache unit group 34.

In a specific embodiment, slave 21 is connected to slave I/O port cache unit group 41, slave 22 is connected to slave I/O port cache unit group 42, slave 23 is connected to slave I/O port cache unit group 43, and slave 24 is connected to slave I/O port cache unit group 44.

In a specific embodiment, the cache unit group gives a ready signal that is always set to 1 to the sending end, and the cache unit group receives a valid signal from the sending end;

In a specific embodiment, the host sends a valid signal to the host I/O port cache unit group, and the host I/O port cache unit group gives the host a ready signal that is always set to 1; the slave sends a valid signal to the slave I/O port cache unit group, and the slave I/O port cache unit group gives the slave a ready signal that is always set to 1; the ready signal from the slave is directly sent to the host I/O port cache unit group without passing through the switching unit, and the ready signal from the host is directly sent to the slave I/O port cache unit group without passing through the switching unit; when the information packet from the host passes through the switching network output port, the switching network output port gives the slave a vaild signal that is set to 1, and when the information packet from the slave passes through the switching network output port, the switching network output port gives the host a valid signal that is set to 1.

The host, slave, host I/O port buffer unit group, and slave I/O port buffer unit group send and receive valid and ready signals to buffer the information packets from the sender in the buffer unit group, so that the sender can continuously send data when the receiver does not respond.

The receiving end gives the cache unit group a ready signal, and the switching network output port gives the receiving end a valid signal, so that the information packets stored in the internal queue of the cache unit can be successfully transmitted to the receiving end.

In a specific embodiment, each cache unit has the same number of cache queues as the host or slave devices, which respectively store information packets from the same channel and the same input port to different destinations to prevent head-of-line blocking.

In a specific embodiment, the switching network is provided with a scheduler 7 for identifying the priority value of the storage queue and transmitting the information packets with longer delays first, thereby meeting the low delay and high performance requirements of the switching network.

In a specific embodiment, the signal bus 5 is a signal bus of rready and bready from the host, and the signal bus 6 is a signal bus of awready, arready and wready from the slave.

Specifically, rready, bready, awready, arready, and wready are ready signals for the five transmission channels of read data, write response, write address, read address, and write data.

In a specific embodiment, the switching units may form a switching network that can accommodate a larger number of N host devices and N slave devices transmitting simultaneously.

FIG3 shows a specific internal structure diagram of banyan according to an embodiment of the present invention. The five different channel protocols of AXI5-Lite can separate the transmission information. The read address information, write address information, and write data information of any host can be transmitted from left to right without affecting each other, and the response data information and read data information of any slave can be transmitted from right to left without affecting each other.

In a specific embodiment, there are 5 schedulers, which are used to schedule information transmission of 5 different channels. Each different type of scheduler schedules the information packet transmission of each different channel. Therefore, if a blockage occurs inside the write data packet, it does not affect the transmission of other types of information packets. The information packet transmission of each channel is managed separately, occupying different physical lines of the banyan network based on the AXI5-Lite protocol. Only when the information packets of the same channel are blocked, the scheduler needs to schedule them, otherwise they will not affect each other. This transmission method enables the data to be transmitted smoothly.

FIG4 shows an example diagram of the components of a write data and read data information packet according to an embodiment of the present invention. The beginning of the information packet is a valid control signal bit. The valid control signal bit determines which of the following control signals are valid data. The control signal itself can determine which of the following data signals are valid data. By setting the valid control signal bit, control signal and data signal, data at the required position can be extracted based on these signals, thereby reducing consumption.

In a specific embodiment, the effective control signal bit, the control signal, and the data signal are integrated into one information packet and transmitted in parallel from the output port.

FIG5 shows an example diagram of AXI5-Lite protocol compatibility according to an embodiment of the present invention. AXI5-Lite is directly compatible with interface protocols such as AXI4-Lite and AXI5. For protocols such as AHB and APB, only a simple interface protocol converter is needed to satisfy the interface connection.

In a specific embodiment, data is transmitted between two hosts and two slaves, the transmission interface protocol of each device is different, and the same switching network based on the AXI5-Lite protocol is used for data transmission.

In a specific embodiment, two hosts and two slaves are included, and an AXI4-Lite interface host 501 and an AXI interface slave 502 are directly connected to an AXI5-Lite protocol switching network for data transmission.

In a specific embodiment, the AHB interface host 500 can directly access a switching network based on the AXI5-Lite protocol by using a protocol conversion interface 505 that converts the AHB protocol to the AXI5-Lite protocol.

In a specific embodiment, the APB interface slave 503 uses an AXI5-Lite protocol to APB protocol protocol conversion interface 506 to connect to the AXI5-Lite protocol switching network. Although each device uses a different transmission protocol, it can be transmitted on the switching network of the same protocol, reflecting the forward and backward compatibility of the AXI5-Lite protocol.

Referring to Figure 6, a schematic diagram of a computer system 600 suitable for implementing an electronic device of an embodiment of the present application is shown. The electronic device shown in Figure 6 is only an example and should not limit the functions and scope of use of the embodiment of the present application.

As shown in FIG6 , the computer system 600 includes a central processing unit (CPU) 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage portion 608 into a random access memory (RAM) 603. Various programs and data required for the operation of the system 600 are also stored in the RAM 603. The CPU 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input/output (I/O) interface 605 is also connected to the bus 604.

The following components are connected to the I/O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 606 including a liquid crystal display (LCD), etc. and a speaker, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, a modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I/O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed, so that a computer program read therefrom is installed into the storage section 608 as needed.

In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable storage medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 609, and/or installed from the removable medium 611. When the computer program is executed by the central processing unit (CPU) 601, the above functions defined in the method of the present application are executed. It should be noted that the computer-readable storage medium described in the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, - but not limited to - an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, an apparatus or a device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable storage medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, an apparatus or a device. The program code contained on a computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

Computer program code for performing the operations of the present application may be written in one or more programming languages or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and/or flow chart, and the combination of the boxes in the block diagram and/or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

The modules involved in the embodiments described in the present application may be implemented by software or hardware. The units described may also be arranged in a processor, and the names of these units do not constitute limitations on the units themselves in certain circumstances.

An embodiment of the present invention further relates to a computer-readable storage medium having a computer program stored thereon, which implements the method described above when the computer program is executed by a computer processor. The computer program includes program code for executing the method shown in the flowchart. It should be noted that the computer-readable medium of the present application may be a computer-readable signal medium or a computer-readable medium or any combination of the above two.

The present invention discloses a non-blocking banyan network that meets the AXI5-Lite protocol standard. The banyan network is used to construct a switching network that meets the AXI5-Lite protocol standard. The network channel lines are gathered in a switching unit, the complexity of the switching network is reduced, a scheduler is respectively set in 5 pairs of channels, and the low latency and high performance of the switching network are achieved. The cache unit has the ability to output and read signals, avoiding transmission blocking. The cache queue in the cache unit corresponds to the number of the host and the slave, further reducing the blocking. The effective control signal bit and the control signal bit and the data signal bit are set for the data information packet in the transmission channel, ensuring the convenience of information packet reading. The transmission bus width of each transmission channel is consistent with the length of the data information packet, so that the transmission can be completed at one time without excessive consumption. The switching network structure of the present invention is relatively simple, and can be applied to non-blocking transmission between various AMBA bus interface modules that require high performance, low latency and low network complexity.

The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above invention concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims (8)

1. A non-blocking banyan network that meets AXI5-Lite protocol standards, comprising:

A plurality of switching units forming a switching network, wherein each switching unit is provided with 5 common switching units in an integrated manner to meet 5 pairs of AXI channels with different attributes in different directions, and each transmission channel in the 5 pairs of AXI channels with different attributes in different directions has a transmission bus width consistent with the length of a data information packet;

A host I/O port buffer unit group provided between the switching network and a host to buffer a packet from the host to be transmitted to the switching network, wherein each host I/O port buffer unit in the host I/O port buffer unit group has a plurality of host buffer queues inside,

A slave I/O port buffer unit group provided between the switching network and a slave to buffer a packet from the slave to be transmitted to the switching network, wherein each of the slave I/O port buffer units in the slave I/O port buffer unit group has a plurality of slave buffer queues inside, wherein the master I/O port buffer unit group receives a valid signal from the master to confirm whether the master is to transmit data, the master I/O port buffer unit group gives a ready signal always set to 1 to the master so that the data is directly transmitted into the master buffer unit group, and the slave I/O port buffer unit group receives a valid signal from the slave to confirm whether the slave is to transmit data, and the slave I/O port buffer unit group gives a ready signal always set to 1 to the slave so that the data is directly transmitted into the slave buffer unit;

when an information packet is transmitted from a host to a slave, once an output port of a switching network detects that the information packet passes, the output port of the switching network gives a valid signal of a channel corresponding to the information packet to the target slave;

when the information packet is transmitted from the slave to the host, once the output port of the switching network detects that the information packet passes, the output port of the switching network gives the valid signal of the channel corresponding to the information packet to the target host.

2. The non-blocking banyan network of claim 1, wherein the master I/O port cache unit group includes three types of cache units for read address packets, write address packets, and write data packets, respectively, and the slave I/O port cache unit group includes two types of cache units for read data packets and response packets, respectively.

3. The non-blocking banyan network of claim 1, wherein the master I/O port cache unit group receives a ready signal sent directly from a slave and the slave I/O port cache unit group receives a ready signal sent directly from a master.

4. The non-blocking banyan network of claim 1, wherein the number of the plurality of master cache queues is equal to the number of slaves connected to the switching network, and the number of the plurality of slave cache queues is equal to the number of masters connected to the switching network.

5. The non-blocking banyan network of claim 2, wherein the 5 pairs of different-direction different-attribute AXI channels include 5 pairs of AXI channels for write data, write address, read data, read address, and response, respectively.

6. The non-blocking banyan network according to claim 5, wherein the banyan network further comprises 5 schedulers connected to the switching network, the 5 schedulers assigning priorities to packets to be transmitted in the cache queue for 5 pairs of AXI channels of different direction and different properties, respectively.

7. The non-blocking banyan network according to claim 5, wherein for a channel of a write address, a channel of a read address, a data packet includes 7 bits of valid control signal bits and a control signal corresponding to the 7 bits of valid control signal bits;

for the channel of the write response, the data information packet comprises 5 bits of valid control signal bits and a control signal corresponding to the 5 bits of valid control signal bits.

8. The non-blocking banyan network according to claim 7, wherein for a channel to write data and a channel to read data, the data packet includes 4 valid control signal bits and a control signal corresponding to the 4 valid control signal bits, the data packet further includes a data signal, and the size of the valid data of the data signal is determined by the corresponding control signal.