CN114664818A

CN114664818A - Semiconductor structure and forming method thereof

Info

Publication number: CN114664818A
Application number: CN202011541274.3A
Authority: CN
Inventors: 张海洋; 陈卓凡; 刘骁兵
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-12-23
Filing date: 2020-12-23
Publication date: 2022-06-24

Abstract

A semiconductor structure and a method for forming the same, the forming method includes: providing a substrate, a gate structure is formed on the substrate, source and drain doped layers are formed in the substrate on both sides of the gate structure, and a first gate structure is formed on the substrate exposed by the gate structure. An interlayer dielectric layer, the first interlayer dielectric layer covers the top of the gate structure; an opening is formed through the first interlayer dielectric layer between the gate structures, and the opening exposes the source and drain doped layers; a bottom source is formed in the opening a drain plug, the top of the bottom source-drain plug is lower than the top of the opening, and the top of the bottom source-drain plug is higher than the top of the gate structure; an etching barrier layer is formed on the sidewall of the opening exposed by the bottom source-drain plug; forming a gate contact hole located between adjacent etching barrier layers and passing through the first interlayer dielectric layer, and the gate structure is exposed at the bottom of the gate contact hole; forming a gate contact hole located between adjacent etching barrier layers and passing through the second interlayer Source-drain contact holes of the dielectric layer. The alignment accuracy of the top source-drain plug and the bottom source-drain plug is improved by etching the barrier layer.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

With the continuous development of integrated circuit manufacturing technology, the requirements for the integration level and performance of integrated circuits become higher and higher. In order to improve the integration level and reduce the cost, the critical dimensions of the devices are continuously reduced, and the circuit density inside the integrated circuits is increased, so that the wafer surface cannot provide enough area for manufacturing the required interconnection lines.

In order to meet the requirement of the interconnection line after the critical dimension is reduced, the conduction of different metal layers or metal layers and the substrate is realized by an interconnection structure at present. The interconnect structure includes an interconnect line and a contact hole plug formed within the contact opening. The contact hole plugs are connected with the semiconductor device, and the interconnection lines realize connection between the contact hole plugs, thereby forming a circuit. The contact hole plug in the transistor structure comprises a grid contact hole plug positioned on the surface of the grid structure and used for realizing the connection between the grid structure and an external circuit, and a source drain contact hole plug positioned on the surface of the source drain doping layer and used for realizing the connection between the source drain doping layer and the external circuit.

Currently, in order to further reduce the area of the transistor, a Contact Over Active Gate (COAG) process is introduced. Compared with the conventional gate contact hole plug positioned above the gate structure of the isolation region, the COAG process can make the gate contact hole plug above the gate structure of the Active Area (AA), thereby further saving the Area of a chip.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: the transistor comprises a substrate, a grid structure, a first interlayer dielectric layer and a second interlayer dielectric layer, wherein the grid structure is formed on the substrate, active drain doping layers are formed in the substrate on two sides of the grid structure, the first interlayer dielectric layer is formed on the substrate exposed out of the grid structure, and the top of the grid structure is covered by the first interlayer dielectric layer; the bottom source drain plug is positioned in the first interlayer dielectric layer between the grid structures and connected with the source drain doping layer, and the top of the bottom source drain plug is lower than the top of the first interlayer dielectric layer and higher than the top of the grid structures; the second interlayer dielectric layer penetrates through the first interlayer dielectric layer at the top of the bottom source drain plug; the etching barrier layer is positioned between the side wall of the second interlayer dielectric layer and the first interlayer dielectric layer; the grid plug penetrates through the first interlayer dielectric layer between the adjacent etching barrier layers, and the bottom of the grid plug is connected with the grid structure; and the top source drain plug penetrates through the second interlayer dielectric layer between the adjacent etching barrier layers, and the bottom of the top source drain plug is connected with the bottom source drain plug.

Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, wherein a grid structure is formed on the substrate, active drain doping layers are formed in the substrate on two sides of the grid structure, a first interlayer dielectric layer is formed on the substrate exposed out of the grid structure, and the first interlayer dielectric layer covers the top of the grid structure; forming an opening penetrating through the first interlayer dielectric layer between the grid structures, wherein the opening exposes the source drain doping layer; forming a bottom source drain plug in the opening, wherein the top of the bottom source drain plug is lower than the top of the opening, and the top of the bottom source drain plug is higher than the top of the gate structure; forming an etching barrier layer on the exposed side wall of the opening of the bottom source drain plug; after the etching barrier layer is formed, forming a second interlayer dielectric layer in the rest of the opening; forming a grid contact hole which is positioned between the adjacent etching barrier layers and penetrates through the first interlayer dielectric layer, wherein the bottom of the grid contact hole exposes the grid structure; forming a source drain contact hole which is positioned between the adjacent etching barrier layers and penetrates through the second interlayer dielectric layer, wherein the bottom source drain plug is exposed at the bottom of the source drain contact hole; and forming a grid plug in the grid contact hole, and forming a top source drain plug in the source drain contact hole.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

the embodiment of the invention provides a semiconductor structure, wherein a bottom source drain plug is positioned in a first interlayer dielectric layer between grid structures and connected with a source drain doping layer, a second interlayer dielectric layer penetrates through the first interlayer dielectric layer at the top of the bottom source drain plug, an etching barrier layer is positioned between the side wall of the second interlayer dielectric layer and the first interlayer dielectric layer, a grid plug penetrates through the first interlayer dielectric layer between adjacent etching barrier layers, the bottom of the grid plug is connected with the grid structures, a top source drain plug penetrates through the second interlayer dielectric layer between the adjacent etching barrier layers, and the bottom of the top source drain plug is connected with the bottom source drain plug. The invention forms an etching barrier layer between the side wall of the second interlayer dielectric layer and the first interlayer dielectric layer, the etching barrier layer can realize self-alignment in the process of forming the gate contact hole and the source drain contact hole, which is beneficial to improving the position accuracy of the gate contact hole and the source drain contact hole, thereby improving the alignment accuracy of the top source drain plug and the corresponding bottom source drain plug and the alignment accuracy of the gate plug and the corresponding gate structure, further improving the performance of the semiconductor structure, and only considering the etching selection ratio between the second interlayer dielectric layer and the etching barrier layer in the process of forming the gate contact hole, only considering the etching selection ratio between the first interlayer dielectric layer and the etching barrier layer in the process of forming the gate contact hole, therefore, self-alignment is easily realized in the process of forming the gate contact hole and the source drain contact hole.

The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of forming an opening penetrating through a first interlayer dielectric layer between grid structures, wherein a source-drain doping layer is exposed from the opening; forming a bottom source drain plug in the opening, wherein the top of the bottom source drain plug is lower than the top of the opening; forming an etching barrier layer on the exposed side wall of the opening of the bottom source drain plug; forming a second interlayer dielectric layer in the rest openings; forming a grid contact hole which is positioned between the adjacent etching barrier layers and penetrates through the first interlayer dielectric layer, wherein the bottom of the grid contact hole exposes the grid structure; forming a source drain contact hole which is positioned between the adjacent etching barrier layers and penetrates through the second interlayer dielectric layer, wherein the bottom source drain plug is exposed out of the bottom of the source drain contact hole; and forming a grid plug in the grid contact hole, and forming a top source drain plug in the source drain contact hole. The invention forms the etching barrier layer on the exposed opening side wall of the bottom source drain plug, so that the self-alignment is realized in the process of forming the source drain contact hole and the grid contact hole, which is favorable for improving the position accuracy of the grid contact hole and the source drain contact hole, thereby improving the alignment precision of the top source drain plug and the corresponding bottom source drain plug, and the alignment precision of the grid plug and the corresponding grid structure, further improving the performance of the semiconductor structure, in the process of forming the source-drain contact holes, only the etching selection ratio between the second interlayer dielectric layer and the etching barrier layer needs to be considered, in the process of forming the grid contact hole, only the etching selection ratio between the first interlayer dielectric layer and the etching barrier layer needs to be considered, therefore, self-alignment is easily realized in the process of forming the gate contact hole and the source drain contact hole.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

FIG. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;

FIGS. 3 to 15 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 16 is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention.

Detailed Description

Currently, the performance of semiconductor structures is still in need of improvement. The reason why the performance of a semiconductor structure needs to be improved is analyzed in combination with a method for forming the semiconductor structure.

Fig. 1 is a schematic structural diagram of a semiconductor structure.

The semiconductor structure includes: the substrate comprises a substrate 10 and a fin part 11 positioned on the substrate 10; a gate structure 22 crossing the fin 11 and covering part of the top and part of the sidewall of the fin 11; the source-drain doping layer 20 is positioned in the fin parts 11 on two sides of the gate structure 22; a bottom source drain plug 18 located on top of the source drain doping layer 20; the etching stop layer 21 is positioned at the top of the bottom source drain plug 18; the side wall 14 is positioned on the side wall of the gate structure 22; the first interlayer dielectric layer 12 is positioned on the substrate where the gate structure 22 is exposed, and the first interlayer dielectric layer 12 covers the top of the gate structure 22 and the top of the etching stop layer 21; a second interlayer dielectric layer 15 positioned on top of the first interlayer dielectric layer 12; a gate plug 19 penetrating through the first interlayer dielectric layer 12 and the second interlayer dielectric layer 15 on the top of the gate structure 22; and the top source drain plug 16 penetrates through the second interlayer dielectric layer 15 and the etching stop layer 21 at the top of the bottom source drain plug 18.

In the forming process of the semiconductor structure, a grid plug 19 is formed in a grid contact hole, and a top source drain plug 16 is formed in a source drain contact hole.

Research shows that as the feature size of a device is continuously reduced, the distance between adjacent fins 11 is also smaller, so that the distance between adjacent gate structures 22 is correspondingly continuously reduced, and accordingly, in the process of forming source and drain contact holes, overlay shift (overlay shift) has a large influence on the position accuracy of the source and drain contact holes, thereby easily causing the problem that the top source and drain plugs 16 and the corresponding bottom source and drain plugs 18 cannot be completely aligned (as indicated by a dashed circle in fig. 1), and further easily causing the performance degradation of the semiconductor structure.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a grid structure is formed on the substrate, active drain doping layers are formed in the substrate on two sides of the grid structure, a first interlayer dielectric layer is formed on the substrate exposed out of the grid structure, and the first interlayer dielectric layer covers the top of the grid structure; forming an opening penetrating through the first interlayer dielectric layer between the grid electrode structures, wherein the opening exposes the source-drain doping layer; forming a bottom source drain plug in the opening, wherein the top of the bottom source drain plug is lower than the top of the opening, and the top of the bottom source drain plug is higher than the top of the gate structure; forming an etching barrier layer on the side wall of the opening exposed by the bottom source drain plug; after the etching barrier layer is formed, forming a second interlayer dielectric layer in the rest of the opening; forming a grid contact hole which is positioned between the adjacent etching barrier layers and penetrates through the first interlayer dielectric layer, wherein the bottom of the grid contact hole exposes the grid structure; forming a source drain contact hole which is positioned between the adjacent etching barrier layers and penetrates through the second interlayer dielectric layer, wherein the bottom source drain plug is exposed at the bottom of the source drain contact hole; and forming a grid plug in the grid contact hole, and forming a top source drain plug in the source drain contact hole.

In the scheme disclosed by the embodiment of the invention, an opening penetrating through a first interlayer dielectric layer between grid structures is formed, and the source-drain doping layer is exposed from the opening; forming a bottom source drain plug in the opening, wherein the top of the bottom source drain plug is lower than the top of the opening; forming an etching barrier layer on the exposed side wall of the opening of the bottom source drain plug; forming a second interlayer dielectric layer in the rest openings; forming a grid contact hole which is positioned between the adjacent etching barrier layers and penetrates through the first interlayer dielectric layer, wherein the bottom of the grid contact hole exposes the grid structure; forming a source drain contact hole which is positioned between the adjacent etching barrier layers and penetrates through the second interlayer dielectric layer, wherein the bottom source drain plug is exposed at the bottom of the source drain contact hole; and forming a grid plug in the grid contact hole, and forming a top source drain plug in the source drain contact hole. The invention forms the etching barrier layer on the side wall of the opening exposed by the bottom source drain plug, so that the self-alignment is realized in the process of forming the source drain contact hole and the grid contact hole, which is favorable for improving the position accuracy of the grid contact hole and the source drain contact hole, thereby improving the alignment precision of the top source-drain plug and the corresponding bottom source-drain plug, and the alignment precision of the gate plug and the corresponding gate structure, and further improving the performance of the semiconductor structure, in the process of forming the source-drain contact holes, only the etching selection ratio between the second interlayer dielectric layer and the etching barrier layer needs to be considered, in the process of forming the grid contact hole, only the etching selection ratio between the first interlayer dielectric layer and the etching barrier layer needs to be considered, therefore, self-alignment is easily realized in the process of forming the gate contact hole and the source drain contact hole.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the invention.

The semiconductor structure includes: a gate structure 307 is formed on the substrate, an active drain doping layer 308 is formed in the substrate on two sides of the gate structure 307, a first interlayer dielectric layer 302 is formed on the substrate exposed out of the gate structure 307, and the first interlayer dielectric layer 302 covers the top of the gate structure 307; a bottom source-drain plug 312, located in the first interlayer dielectric layer 302 between the gate structures 307 and connected to the source-drain doping layer 308, wherein the top of the bottom source-drain plug 312 is lower than the top of the first interlayer dielectric layer 302 and higher than the top of the gate structure 307; a second interlayer dielectric layer 314 penetrating the first interlayer dielectric layer 302 on the top of the bottom source drain plug 312; an etch stop layer 313 between a sidewall of the second interlayer dielectric layer 314 and the first interlayer dielectric layer 302; a gate plug 316 penetrating through the first interlayer dielectric layer 302 between the adjacent etching barrier layers 313, wherein the bottom of the gate plug 316 is connected with the gate structure 307; and the top source-drain plug 317 penetrates through the second interlayer dielectric layer 314 between the adjacent etching barrier layers 313, and the bottom of the top source-drain plug 317 is connected with the bottom source-drain plug 312.

The gate plug 316 is formed in the gate contact hole, the top source drain plug 317 is formed in the source drain contact hole, and by forming the etching barrier layer 313 between the sidewall of the second interlayer dielectric layer 314 and the first interlayer dielectric layer 302, the etching barrier layer 313 can realize self-alignment in the process of forming the gate contact hole and the source drain contact hole, which is beneficial to improving the position accuracy of the gate contact hole and the source drain contact hole, thereby improving the alignment accuracy of the top source drain plug 317 and the corresponding bottom source drain plug 312, and the alignment accuracy of the gate plug 316 and the corresponding gate structure 307, further improving the performance of the semiconductor structure, and in the process of forming the source drain contact hole, only the etching selection ratio between the second interlayer dielectric layer 314 and the etching barrier layer 313 needs to be considered, only the etching selection ratio between the first interlayer dielectric layer 302 and the etching barrier layer 313 needs to be considered, so that self-alignment is easily realized in the process of forming the gate contact hole and the source drain contact hole.

In this embodiment, the semiconductor structure is a fin field effect transistor (FinFET). The base includes a substrate 300 and a fin 301 on the substrate 300. In this embodiment, the substrate 300 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the fin portion 301 is separated on the substrate 300, and the material of the fin portion 301 is the same as that of the substrate, and is silicon.

In other embodiments, when the semiconductor structure is a planar transistor, the base may also be a planar substrate.

In this embodiment, the semiconductor structure further includes: the isolation layer 350 is located on the substrate 300 where the fin portion 301 is exposed, and the isolation layer 350 covers a portion of the sidewall of the fin portion 301.

The isolation layer 350 serves to isolate adjacent devices. The material of the isolation layer 350 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation layer 350 is made of silicon oxide.

In this embodiment, the gate structure 307 is a metal gate structure, and is used for controlling the on and off of a channel of a transistor.

The gate structure 307 includes a high-k gate dielectric layer, a work function layer on the high-k gate dielectric layer, and a gate electrode layer on the work function layer.

In this embodiment, the source-drain doping layer 308 is located in the fin portion 301 on two sides of the gate structure 307.

When the semiconductor device is a PMOS transistor, the source-drain doping layer 308 is made of silicon germanium doped with P-type ions, and the P-type ions include B, Ga or In. When the semiconductor device is an NMOS transistor, the source-drain doping layer 308 is made of silicon carbide or silicon doped with N-type ions, and the N-type ions include P, As or Sb.

In this embodiment, the semiconductor structure further includes: and the side wall 304 is positioned on the substrate where the gate structure 307 is exposed, and the side wall 304 covers the side wall of the gate structure 307.

The sidewall spacers 304 are used for protecting the sidewalls of the gate structure 307, and the sidewall spacers 304 are further used for defining the formation position of the source/drain doping layer 308. The sidewall 304 may have a single-layer structure or a stacked-layer structure, and the material of the sidewall 304 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacer 304 has a single-layer structure, and the material of the sidewall spacer 304 is silicon nitride.

In this embodiment, the semiconductor structure further includes: a gate cap 306 on top of the gate structure 307.

The gate capping layer 306 protects the gate structure 307.

In this embodiment, the gate capping layer 306 is made of silicon nitride.

In this embodiment, the first interlayer dielectric layer 302 is located on the substrate where the gate structure 307 is exposed, and the first interlayer dielectric layer 302 further covers the top of the gate structure 307.

The first interlayer dielectric layer 302 is used to isolate adjacent transistors. The first interlayer dielectric layer 302 is made of an insulating material, and the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the first interlayer dielectric layer 302 is made of silicon oxide.

In this embodiment, in the first interlayer dielectric layer 302 located at the top of the gate structure 307, a surface opposite to a sidewall of the etch stop layer 313 is a first side surface, a surface opposite to a sidewall of the bottom source drain plug 312 is a second side surface, and the first side surface protrudes relative to the second side surface.

Specifically, the first side surface protrudes relative to the second side surface, so that the probability that the etching blocking layer 313 covers the top surface of the bottom source drain plug 312 is reduced, that is, the etching blocking layer 313 exposes more top surfaces of the bottom source drain plug 312, and accordingly, after the top source drain plug 317 is formed on the top surface of the bottom source drain plug 312, the contact area between the bottom source drain plug 312 and the top source drain plug 317 is larger, so that the electrical connection effect between the bottom source drain plug 312 and the top source drain plug 317 is improved, and the performance of the semiconductor structure is improved.

It should be noted that the protruding dimension of the first side surface relative to the second side surface is not too large or too small. If the protruding dimension of the first side surface relative to the second side surface is too large, the top space position of the gate structure 307 is easily occupied too much, so that the formation of a gate plug is affected, and the structural performance of a semiconductor is affected; if the protruding size of the first side surface is too small relative to the second side surface, the etching blocking layer 313 has a certain lateral size, which easily causes the etching blocking layer 313 to cover the top surface of the top source drain plug 317, thereby affecting the electrical connection effect between the top source drain plug 317 and the corresponding bottom source drain plug 312. For this reason, in this embodiment, the dimension of the first side surface protruding with respect to the second side surface is 50 to 200 angstroms. For example, the dimension of the first side that protrudes relative to the second side is 70 angstroms, 100 angstroms, or 150 angstroms.

In this embodiment, the bottom source-drain plug 312 is located in the first interlayer dielectric layer 302 between the gate structures 307 and connected to the source-drain doping layer 308, and the top of the bottom source-drain plug 312 is lower than the top of the first interlayer dielectric layer 302 and higher than the top of the gate structure 307.

The bottom source drain plugs 312 contact the source drain doped layers 308 for making electrical connection between the source drain doped layers 308 and external circuitry or other interconnect structures.

In this embodiment, the top of the bottom source-drain plug 312 is lower than the top of the first interlayer dielectric layer 302.

The top of the bottom source-drain plug 312 is lower than the top of the first interlayer dielectric layer 302, and is used for providing a spatial position for the etching blocking layer 313 and the second interlayer dielectric layer 314.

In this embodiment, the bottom source/drain plug 312 is made of tungsten. The resistivity of tungsten is low, which is beneficial to improving the signal delay of the rear-section RC and improving the processing speed of the chip, and is also beneficial to reducing the resistance of the bottom source drain plug 312, and correspondingly reducing the power consumption. In other embodiments, the material of the bottom source-drain plug may also be a conductive material such as cobalt or ruthenium.

In this embodiment, the distance from the top of the bottom source-drain plug 312 to the top of the first interlayer dielectric layer 302 is 50 to 500 angstroms.

It should be noted that the distance from the top of the bottom source drain plug 312 to the top of the first interlayer dielectric layer 302 is not too large or too small. If the distance from the top of the bottom source-drain plug 312 to the top of the first interlayer dielectric layer 302 is too large, the spatial position of the bottom source-drain plug 312 is easily occupied too much, so that the electric connection effect between the top source-drain plug 317 and the bottom source-drain plug 312 is reduced, and the electrical performance of a semiconductor is influenced; the distance from the top of the bottom source-drain plug 312 to the top of the first interlayer dielectric layer 302 affects the height of the etching barrier layer 313, and if the distance from the top of the bottom source-drain plug 312 to the top of the first interlayer dielectric layer 302 is too small, the height of the etching barrier layer 313 is too small due to excessive occupation of the spatial position of the etching barrier layer 313, so that the etching barrier layer 313 cannot perform a corresponding function in the process of forming the top source-drain plug 317, and the alignment precision of the top source-drain plug 317 and the corresponding bottom source-drain plug 312 is reduced, thereby affecting the structural performance of a semiconductor. Therefore, in this embodiment, the distance from the top of the bottom source/drain plug 312 to the top of the first interlayer dielectric layer 302 is 50 to 500 angstroms. For example, the distance from the top of the bottom source drain plugs 312 to the top of the first interlayer dielectric layer 302 is 100 angstroms, 150 angstroms, 200 angstroms, 300 angstroms, 350 angstroms, or 400 angstroms.

In this embodiment, the second interlayer dielectric layer 314 penetrates through the first interlayer dielectric layer 302 on the top of the bottom source-drain plug 312.

The second interlayer dielectric layer 314 is made of an insulating material, and the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the first interlayer dielectric layer 314 is made of silicon oxide.

In this embodiment, the etching stop layer 313 is located between the sidewall of the second interlayer dielectric layer 314 and the first interlayer dielectric layer 302.

The etching barrier layer 313 can better define the alignment precision of the overlay, namely, self-alignment is realized in the process of forming the gate contact hole and the source drain contact hole, which is beneficial to improving the position precision of the gate contact hole and the source drain contact hole, thereby improving the alignment accuracy of the top source drain plugs with the corresponding bottom source drain plugs 312 and the alignment accuracy of the gate plugs with the corresponding gate structures 307, thereby improving the performance of the semiconductor structure, and, in the process of forming the source-drain contact holes, only the etching selection ratio between the second interlayer dielectric layer 314 and the etching barrier layer 313 needs to be considered, in the process of forming the gate contact hole, only the etching selection ratio between the first interlayer dielectric layer 302 and the etching barrier layer 313 needs to be considered, therefore, self-alignment is easily realized in the process of forming the gate contact hole and the source drain contact hole.

It should be noted that the lateral dimension of the etching stop layer 313 is not too large or too small. If the lateral dimension of the etching barrier layer 313 is too large, the spatial position of the top of the gate structure 307 is easily occupied too much, so that the formed gate plug 316 does not meet the process requirement, thereby affecting the structural performance of the semiconductor; if the lateral dimension of the etching barrier layer 313 is too small, the etching barrier layer 313 cannot perform a corresponding function in an etching process for forming a gate contact hole or a source/drain contact hole, so that self-alignment cannot be achieved in the process of forming the gate contact hole or the source/drain contact hole. For this reason, in this embodiment, the direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure 307 is taken as a lateral direction, and the lateral dimension of the etch stop layer 313 is 50 to 200 angstroms. For example, the lateral dimensions of the etch stop layer 313 are 70, 100, 150 angstroms.

In this embodiment, the material of the etch stop layer 313 includes one or more of silicon nitride, silicon carbide, and silicon oxycarbide.

The silicon nitride, the silicon carbide or the silicon oxycarbide generally has the characteristics of high hardness, wear resistance and etching resistance, so that the etching blocking layer 313 can keep a good appearance.

In this embodiment, the semiconductor structure further includes: and the protective layer 311 is positioned on the side wall of the bottom source drain plug 312, and the top of the protective layer 311 is flush with the top of the bottom source drain plug 312.

Specifically, the protection layer 311 protects the sidewalls of the bottom source drain plugs 312.

The material of the protection layer 311 includes one or more of silicon nitride or silicon oxycarbonitride.

In the present embodiment, the lateral dimension of the protection layer 311 is 50 to 200 angstroms, taking the direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure 307 as the lateral direction.

It should be noted that the lateral dimension of the protection layer 311 is not too large nor too small. If the lateral size of the protection layer 311 is too large, the spatial position of the bottom source drain plug 312 is occupied too much, so that the bottom source drain plug 312 does not meet the process requirements; if the lateral size of the protection layer 311 is too small, the size of the bottom source drain plug 312 is easily too large, and the probability of short circuit between the bottom source drain plug 312 and the adjacent gate structure 307 is increased, so that the structural performance of the semiconductor is affected. For this reason, in the present embodiment, the lateral dimension of the protection layer 311 is 50 to 200 angstroms with the direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure as the lateral direction. For example, the lateral dimensions of the protective layer 311 are 70 angstroms, 100 angstroms, 150 angstroms.

It should be noted that, in this embodiment, the semiconductor structure further includes: and the bottom residual layer 346 is positioned between the top of the bottom source drain plug 312 and the second interlayer dielectric layer 314, the barrier layer 313 is connected with the bottom of the etching barrier layer 313, and the barrier layer 313 and the etching barrier layer 313 are of an integral structure.

In the process of forming the top source drain plugs 317 on the top of the bottom source drain plugs 312, the second interlayer dielectric layer 314 needs to be etched, in the process of etching the second interlayer dielectric layer 314, the bottom residual layer 346 can play a role of an etching stop layer, and the bottom residual layer 346 plays a role of protecting the bottom source drain plugs 312.

In this embodiment, the semiconductor structure further includes: and a third interlayer dielectric layer 315 on top of the first interlayer dielectric layer 302, the second interlayer dielectric layer 314, and the etch stop layer 313.

The third interlayer dielectric layer 315 is used to realize electrical isolation between the gate plug 316 and the top source drain plug 317.

Therefore, the material of the third interlayer dielectric layer 315 is an insulating material. The material of the third interlayer dielectric layer 315 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the third interlayer dielectric layer 315 is made of silicon oxide.

In this embodiment, the gate plug 316 penetrates through the first interlayer dielectric layer 302 between the adjacent etching stop layers 313, and the bottom of the gate plug 316 is connected to the gate structure 307.

The gate plug 316 is used to make an electrical connection between the gate structure 307 and an external circuit or other interconnect structure.

In this embodiment, the top source drain plug 317 penetrates through the second interlayer dielectric layer 314 between the adjacent etching blocking layers 313, and the bottom of the top source drain plug 317 is connected to the bottom source drain plug 312.

The top source drain plug 317 and the bottom source drain plug 312 form a source drain plug, so that the source drain doping layer 308 is electrically connected with other interconnection structures or external circuits.

It should be noted that, in this embodiment, the gate plug 316 and the top source drain plug 317 also penetrate through the third interlayer dielectric layer 315.

Specifically, the gate plug 316 and the top source drain plug 317 penetrate through the third interlayer dielectric layer 315, so that the volumes of the gate plug 316 and the top source drain plug 317 are increased, and a better electrical connection effect is obtained in an electrical connection process with other interconnection structures or external circuits.

In this embodiment, under the action of the etching blocking layer 313, self-alignment is easily achieved in the process of forming the Gate Contact hole and the source/drain Contact hole, so that the Gate plug 316 can be formed above the Gate structure 307 of the Active region, and the Gate plug 316 is an Active Gate Contact hole plug (COAG). Compared with the scheme that the gate plug is in contact with the gate structure of the isolation region, the embodiment omits the portion of the gate structure 307 in the isolation region, which is beneficial to saving the area of the chip and realizing further reduction of the chip size.

Fig. 3 to fig. 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for fabricating a semiconductor structure according to the present invention.

Referring to fig. 3, a substrate is provided, a gate structure 107 is formed on the substrate, an active drain doping layer 108 is formed in the substrate on two sides of the gate structure 107, a first interlayer dielectric layer 102 is formed on the substrate where the gate structure 107 is exposed, and the first interlayer dielectric layer 102 covers the top of the gate structure 107.

The base includes a substrate 100 and a fin 101 on the substrate 100. In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the fin portion 102 is discrete on the substrate 100, and the material of the fin portion 102 is the same as that of the substrate, and is silicon.

In other embodiments, when the formation method is used to form a planar transistor, the base may also be a planar substrate.

With continued reference to fig. 3, in this embodiment, the method for manufacturing a semiconductor structure further includes: after the fin portion 102 is formed, an isolation layer 150 is formed on the substrate 100 exposed by the fin portion 102, and the isolation layer 150 covers a portion of the sidewall of the fin portion 102.

The isolation layer 150 serves to isolate adjacent devices. The material of the isolation layer 150 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 150 is silicon oxide.

In this embodiment, the gate structure 107 is a metal gate structure, and is used for controlling the on and off of a channel of a transistor.

The gate structure 107 includes a high-k gate dielectric layer, a work function layer conformally covering the high-k gate dielectric layer, and a gate electrode layer covering the work function layer.

In this embodiment, the gate structure 107 is formed by a process of forming a gate electrode layer (high-k metal gate last) after forming a high-k gate dielectric layer, so that the position of the gate structure 107 is occupied by a dummy gate structure (dummy gate) before forming the gate structure 107.

In this embodiment, after the dummy gate structure is formed, the source-drain doping layer 108 is formed in the fin 101 on both sides of the dummy gate structure.

When the formed semiconductor device is a PMOS transistor, the source-drain doping layer 108 is made of silicon germanium doped with P-type ions, and the P-type ions include B, Ga or In. When the formed semiconductor device is an NMOS transistor, the material of the source-drain doping layer 108 is silicon carbide or silicon doped with N-type ions, and the N-type ions include P, As or Sb.

In the step of providing the substrate, a sidewall 104 is formed on a sidewall of the gate structure 107. Specifically, before the source-drain doping layer 108 is formed, the sidewall spacer 104 is formed.

The sidewall spacers 104 are used for protecting the sidewalls of the gate structures 107, and the sidewall spacers 104 are further used for defining the formation positions of the source-drain doping layers 108.

The sidewall 104 may have a single-layer structure or a stacked-layer structure, and the material of the sidewall 104 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacer 104 has a single-layer structure, and the material of the sidewall spacer 104 is silicon nitride.

In this embodiment, a first interlayer dielectric layer 102 is formed on the substrate exposed by the gate structure 107, and the first interlayer dielectric layer 102 also covers the top of the gate structure 107.

The first interlayer dielectric layer 102 is used to isolate adjacent transistors. The first interlayer dielectric layer 102 is also used for providing a process foundation for the subsequent formation of an opening exposing the source-drain doping layer 108.

The first interlayer dielectric layer 102 is made of an insulating material, and the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the first interlayer dielectric layer 102 is made of silicon oxide.

In the step of providing the substrate, a gate capping layer 106 is formed on top of the gate structure 107.

The gate capping layer 106 protects the gate structure 107 during subsequent process steps. In this embodiment, the gate capping layer 106 is made of silicon nitride.

In this embodiment, after the gate structure 107 with a part of thickness is etched back to form a groove surrounded by the sidewall 104 and the gate structure 107, the gate capping layer 106 is formed in the groove.

Referring to fig. 4, an opening 109 penetrating through the first interlayer dielectric layer 102 between the gate structures 107 is formed, and the source drain doping layer 108 is exposed by the opening 109.

And subsequently forming a bottom source drain plug in the opening 109, forming an etching barrier layer on the side wall of the opening exposed by the bottom source drain plug, wherein the bottom source drain plug and the remaining space of the opening 109 exposed by the etching barrier layer are used for forming a second interlayer dielectric layer.

The step of forming the opening includes: forming a masking material layer (not shown) on top of the first interlayer dielectric layer 102; patterning the mask material layer, wherein the rest mask material layer is used as a mask layer 103; and etching the first interlayer dielectric layer 102 by using the mask layer 103 as a mask to form an opening 109 exposing the source-drain doping layer 108.

In this embodiment, the first interlayer dielectric layer 102 is etched by a dry etching process.

After the opening 109 is formed, the method further includes: the mask layer 103 is removed.

With reference to fig. 5 to 6, after the opening 109 is formed, the method further includes: and laterally etching the first interlayer dielectric layer 102 exposed from the side wall of the opening 109 with a preset height H at a position close to the top of the opening 109.

The direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure 107 is a lateral direction.

Forming a bottom source-drain plug in the opening 109 subsequently, wherein the distance from the top of the bottom source-drain plug to the top of the first interlayer dielectric layer 102 is equal to the preset height, and the lateral wall of the opening 109 exposed by the bottom source-drain plug protrudes relative to the lateral wall of the bottom source-drain plug after the bottom source-drain plug is formed by performing transverse etching on the first interlayer dielectric layer 102 exposed on the lateral wall of the opening 109 with the preset height H, so that after an etching barrier layer is formed on the lateral wall of the opening exposed by the bottom source-drain plug subsequently, the probability that the etching barrier layer covers the top surface of the bottom source-drain plug is reduced, that is, the etching barrier layer exposes more top surfaces of the bottom source-drain plug, and correspondingly, after the top source-drain plug is formed on the top surface of the bottom source-drain plug subsequently, the contact area between the bottom source-drain plug and the top source-drain plug is larger, therefore, the electric connection effect of the bottom source drain plug and the top source drain plug is improved, and the performance of the semiconductor structure is improved.

In addition, compared with the scheme that the bottom source-drain plug is formed first and then the lateral etching is performed on the exposed opening sidewall of the bottom source-drain plug, in this embodiment, the lateral etching is performed on the sidewall of the opening 109 with the preset height H first, so that the bottom source-drain plug is prevented from being damaged by the lateral etching.

With reference to fig. 5 to 6, before performing the lateral etching on the first interlayer dielectric layer 102 exposed from the sidewall of the opening 109 with the preset height H, the method further includes: and forming a protective layer 111 on part of the side wall of the opening 109, wherein the protective layer 111 exposes the side wall of the opening with a preset height H.

The protective layer 111 is used to define the height of the opening 109 to be etched laterally.

In addition, in the subsequent process of forming the bottom source drain plug, the process of forming the bottom source drain plug includes a back etching step, and the protective layer 111 can also play a role in stopping etching.

In this embodiment, since the protection layer 111 needs to be retained, a dielectric material is selected as the material of the protection layer 111.

Moreover, when the first interlayer dielectric layer 102 exposed from the sidewall of the opening 109 with the preset height H is subjected to lateral etching, a higher etching selection ratio is provided between the material of the first interlayer dielectric layer 102 and the material of the protective layer 111; in the subsequent process of forming the bottom source drain plug, the material of the bottom source drain plug and the material of the protective layer 111 also have a higher etching selection ratio.

Accordingly, the etching resistance of the protective layer 111 is high.

Specifically, the material of the protective layer 111 includes one or more of silicon nitride and silicon oxycarbonitride.

As an example, the material of the protection layer 111 is silicon nitride.

Specifically, the step of forming the protective layer 111 includes: as shown in fig. 5, a protective material layer 110 is formed on the sidewall and bottom of the opening 109 and on the top of the first interlayer dielectric layer 102; forming a filling layer 142 in the opening 109, wherein the distance from the top of the filling layer 142 to the top of the first interlayer dielectric layer 102 is the preset height H; as shown in fig. 6, the exposed protective material layer 110 of the filling layer 142 is removed, and the remaining protective material layer 110 serves as a protective layer 111.

The filling layer 142 serves as an etching mask for etching the exposed protective material layer 110, and the filling layer 142 protects the covered protective material layer 110, so that a partial height of the protective material layer 110 can be maintained.

In this embodiment, the filling layer 142 is a material that can function as a mask and is easy to remove.

In this embodiment, the material of the filling layer 142 is an organic material, such as: BARC (bottom-antireflective coating) material, ODL (organic dielectric layer) material, photoresist, DARC (dielectric-antireflective coating) material, spin-on carbon (SOC), DUO (Deep UV Light Absorbing Oxide) material, or APF (Advanced Patterning Film) material.

In this embodiment, a dry etching process is adopted to remove the protection material layer 110 exposed by the filling layer 142.

Specifically, the dry etching process is an anisotropic dry etching process.

The anisotropic dry etching process has a longitudinal etching rate far greater than a transverse etching rate, can obtain quite accurate pattern conversion, has small damage to the side wall of the first interlayer dielectric layer 102, and is favorable for accurately controlling the height of the protective layer 111 positioned on the side wall of the opening 109.

In this embodiment, the protection material layer 110 is formed by using an Atomic Layer Deposition (ALD) process.

Specifically, the atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the protective material layer 110, so that the protective material layer 110 can cover the bottom and the side wall of the opening 109 and the top of the first interlayer dielectric layer 102; in addition, the atomic layer deposition process has good gap filling performance and step coverage, and accordingly improves the conformal coverage capability of the protective material layer 110. In other embodiments, the protective material layer may also be formed by a Chemical Vapor Deposition (CVD) process.

After removing the protective material layer 110 exposed by the filling layer 142, the method further includes: the filling layer 142 is removed.

Specifically, the filling layer 142 is removed to provide a spatial position for forming the bottom source drain plug.

In this embodiment, an ashing process is used to remove the filling layer 142.

In this embodiment, after removing the filling layer 142, the method further includes: and removing the protective layer 111 at the bottom of the opening 109, thereby exposing the surface of the source-drain doping layer 108.

Correspondingly, referring to fig. 6, in the step of performing the lateral etching on the first interlayer dielectric layer 102 exposed on the sidewall of the opening 109 with the preset height H, the protective layer 111 is used as a mask to perform the lateral etching.

In this embodiment, a dry etching process is adopted to laterally etch the first interlayer dielectric layer 102 exposed from the sidewall of the opening 109 with the preset height H.

Specifically, the dry etching process is an anisotropic dry etching process

The anisotropic dry etching process has the advantage that the longitudinal etching rate is far greater than the transverse etching rate, so that the transverse etching amount can be accurately controlled.

Before the lateral etching, a mask layer (not shown) is further formed on the top of the first interlayer dielectric layer 102, and the mask layer is used for defining a region to be laterally etched of the first interlayer dielectric layer 102. For example, the material of the mask layer may be photoresist.

In this embodiment, in the step of performing lateral etching on the first interlayer dielectric layer 102 exposed on the sidewall of the opening 109 with the preset height H, the lateral etching amount is 50 to 200 angstroms.

It should be noted that the lateral etching amount should not be too large, nor too small. If the lateral etching amount is too large, the lateral etching amount is easy to occupy the top space position of the gate structure 107 too much, so that the gate plug formed on the top of the gate structure 107 subsequently cannot meet the process requirement, thereby affecting the structural performance of the semiconductor; if the lateral etching amount is too small, an etching barrier layer is formed on the exposed side wall of the bottom source drain plug, and the etching barrier layer easily covers the top surface of the top source drain plug due to a certain lateral size, so that the subsequent electric connection effect of the top source drain plug and the corresponding bottom source drain plug is influenced. Therefore, in this embodiment, in the step of performing lateral etching on the first interlayer dielectric layer 102 exposed on the sidewall of the opening 109 with the preset height H, the lateral etching amount is 50 to 200 angstroms.

With reference to fig. 7 to 8, a bottom source drain plug 112 is formed in the opening 109, where the top of the bottom source drain plug 112 is lower than the top of the opening 109, and the top of the bottom source drain plug 112 is higher than the top of the gate structure 107.

The bottom source drain plug 112 is in contact with the source drain doped layer 108 for electrically connecting the source drain doped layer 108 with an external circuit or other interconnect structure.

A top source-drain plug in contact with the bottom source-drain plug 112 is formed on the bottom source-drain plug 112 subsequently, and the top source-drain plug is electrically connected with the source-drain doping layer 108 through the bottom source-drain plug 112.

In this embodiment, the top of the bottom source drain plug 112 is lower than the top of the opening 109.

The top of the bottom source drain plug 112 is lower than the top of the opening 109, and is used for providing a spatial position for forming an etching barrier layer on the sidewall of the opening exposed by the bottom source drain plug 112 in the following step.

In this embodiment, the bottom source drain plug 112 is made of tungsten. The resistivity of tungsten is low, which is beneficial to improving the signal delay of the rear-section RC and improving the processing speed of the chip, and is also beneficial to reducing the resistance of the bottom source drain plug 112, and correspondingly reducing the power consumption. In other embodiments, the material of the bottom source-drain plug may also be a conductive material such as cobalt or ruthenium.

In this embodiment, the step of forming the bottom source drain plug 112 includes: as shown in fig. 7, the opening 109 (shown in fig. 6) is filled with a conductive material layer 140; as shown in fig. 8, the conductive material layer 140 is planarized with the top of the first interlayer dielectric layer 102 as a stop position; after the planarization treatment, the top of the protection layer 111 is used as a stop position, the conductive material layer 140 with a part of thickness is etched back, and the remaining conductive material layer 140 after the etching back is used as the bottom source drain plug 112.

The conductive material layer 140 is first planarized to retain the conductive material layer 140 in the opening 109, and the top surface of the remaining conductive material layer 140 has a higher flatness, so that the etching uniformity is improved when the conductive material layer 140 in the opening 109 is etched back in the following step, and accordingly, the top surface flatness and the height uniformity of the bottom source drain plug 112 are improved.

In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is used to etch back a portion of the thickness of the conductive material layer 140.

Correspondingly, in this embodiment, the distance from the top of the bottom source-drain plug 112 to the top of the first interlayer dielectric layer 102 is equal to the preset height H.

Referring to fig. 9, an etch stop layer 113 is formed on the sidewall of the opening 109 exposed by the bottom source drain plug 112.

And subsequently forming a second interlayer dielectric layer in the rest openings, forming a grid contact hole which is positioned between the adjacent etching barrier layers and penetrates through the first interlayer dielectric layer, exposing the grid structure at the bottom of the grid contact hole, forming a source drain contact hole which is positioned between the adjacent etching barrier layers and penetrates through the second interlayer dielectric layer, exposing the bottom source drain plug at the bottom of the source drain contact hole, forming a grid plug in the grid contact hole, and forming a top source drain plug in the source drain contact hole. In the embodiment, the etching barrier layer 113 is formed on the sidewall of the opening 109 exposed by the bottom source-drain plug 112, so that in the subsequent process of forming the source-drain contact hole and the gate contact hole, the etching barrier layer 113 can better define the overlay alignment accuracy, that is, self-alignment is realized in the process of forming the gate contact hole and the source-drain contact hole, which is beneficial to improving the position accuracy of the gate contact hole and the source-drain contact hole, thereby improving the alignment accuracy of the top source-drain plug and the corresponding bottom source-drain plug 112, and the alignment accuracy of the gate plug and the corresponding gate structure 107, further improving the performance of the semiconductor structure, and in the process of forming the source-drain contact hole, only the etching selection ratio between the second interlayer dielectric layer and the etching barrier layer 113 needs to be considered, in the process of forming the gate contact hole, only the etching selection ratio between the first interlayer dielectric layer 102 and the etching barrier layer 113 needs to be considered, so that self-alignment is easily realized in the process of forming the gate contact hole and the source drain contact hole.

In this embodiment, the step of forming the etching blocking layer 113 on the sidewall of the opening 109 exposed by the bottom source-drain plug 112 includes: and forming an etching barrier material layer 143 on the sidewall of the opening 109 exposed by the bottom source-drain plug 112, the top of the bottom source-drain plug 112, and the top of the first interlayer dielectric layer 102, wherein the etching barrier material layer 143 on the sidewall of the opening 109 is used as an etching barrier layer 113.

The etch stop material layer 143 provides a process basis for forming the etch stop layer 113.

In this embodiment, the etching barrier material layer 143 is formed by an atomic layer deposition process. In other embodiments, the etching barrier material layer may also be formed by using a chemical vapor deposition process.

In this embodiment, in the process of forming the etching stopper layer 113, the etching stopper material layer 143 on the top of the bottom source/drain plug 112 and on the top of the first interlayer dielectric layer 102 is retained, so that the etching stopper material layer 143 on the top of the first interlayer dielectric layer 102 is removed in the subsequent process of forming the second interlayer dielectric layer, thereby simplifying the process steps.

In this embodiment, each interlayer dielectric layer has a higher etching selection ratio with respect to the etching stopper layer 113, so that self-alignment can be achieved in the subsequent formation process of the source/drain contact hole and the gate contact hole.

As an example, the material of the etch stop layer 113 needs to satisfy: the etching selection ratio between each interlayer dielectric layer and the etching barrier layer 113 is more than 3.

For example, the etching selectivity between each interlayer dielectric layer and the etch stop layer 113 is greater than 3 and less than 10.

Specifically, the etch resistance of the etch stop layer 113 is greater than that of each interlayer dielectric layer.

In this embodiment, the material of the etch stop layer 113 includes one or two of silicon nitride, silicon carbide, and silicon oxycarbide.

As an example, the material of the etch stop layer 113 is silicon nitride. In other embodiments, the material of the etch stop layer is silicon carbide.

Referring to fig. 10 to 11, after the etch stop layer 113 is formed, a second interlayer dielectric layer 114 is formed in the remaining opening 109.

The second interlayer dielectric layer 114 provides a spatial position for the subsequent formation of the top source drain plug.

In this embodiment, the step of forming the second interlayer dielectric layer 114 in the remaining opening 109 includes: as shown in fig. 10, a dielectric material layer 150 is formed in the remaining opening 109, and the dielectric material layer 150 covers the etching barrier material layer 143; as shown in fig. 11, with the top of the first interlayer dielectric layer 102 as a stop position, the dielectric material layer 150 is planarized, and the remaining dielectric material layer 150 is used as a second interlayer dielectric layer 114, wherein in the planarization process, the etching stop material layer 143 higher than the top of the first interlayer dielectric layer 102 is removed.

The dielectric material layer 150 provides a process basis for forming the second interlayer dielectric layer 114.

It should be noted that, in the process of planarizing the dielectric material layer 150, the planarization treatment is further performed on the etching stop material layer 143 higher than the top of the first interlayer dielectric layer 102. Accordingly, the process steps are simplified, and the process cost is reduced.

In this embodiment, after removing the etching blocking material layer 143 higher than the top of the first interlayer dielectric layer 102, the remaining etching blocking material layer 143 on the top of the bottom source drain plug 112 is retained as the bottom residual layer 146.

Referring to fig. 12, after forming the second interlayer dielectric layer 114, the method further includes: a third interlayer dielectric layer 115 is formed on top of the first interlayer dielectric layer 102 and the second interlayer dielectric layer 114.

The third interlayer dielectric layer 115 provides a spatial position for forming a gate contact hole and a source drain contact hole, and is used for realizing subsequent electrical isolation between a gate plug and a top source drain plug.

In this embodiment, through the third interlayer dielectric layer 115, while the heights of the gate plug and the top source-drain plug meet the process requirements, the height of the second interlayer dielectric layer 102 is not too high, and correspondingly, the aspect ratio of the opening 109 is not too large, so as to facilitate the formation of the bottom source-drain plug 112, the formation of the etching barrier layer 113, and the transverse etching of the first interlayer dielectric layer 102 exposed from the wall of the opening 109 with the preset height H, and accordingly, the process difficulty is reduced, and the process cost is reduced.

The material of the third interlayer dielectric layer 115 is an insulating material, and for example, includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the third interlayer dielectric layer 115 is silicon oxide.

Referring to fig. 13, a gate contact hole 130 is formed between adjacent etch stop layers 113 and through the first interlayer dielectric layer 102, and the bottom of the gate contact hole 130 exposes the gate structure 107.

The gate contact opening 130 provides a spatial location for the subsequent formation of a gate plug.

In this embodiment, in the step of forming the gate contact hole 130, the gate contact hole 130 penetrates through the third interlayer dielectric layer 115 and the first interlayer dielectric layer 102.

In this embodiment, a dry etching process is used to remove the third interlayer dielectric layer 115 and the first interlayer dielectric layer 102 on the top of the gate structure 107, so as to form a gate contact hole 130 exposing the gate structure 107.

In this embodiment, in the process of forming the gate contact hole 130, the method further includes: the gate capping layer 106 is removed atop the gate structure 107.

Referring to fig. 14, a source/drain contact hole 131 is formed between adjacent etching stop layers 113 and penetrates through the second interlayer dielectric layer 114, and the bottom of the source/drain contact hole 131 exposes the bottom source/drain plug 112.

The source drain contact hole 131 provides a spatial location for the subsequent formation of a top source drain plug.

In this embodiment, in the step of forming the source/drain contact hole 131, the source/drain contact hole 131 penetrates through the third interlayer dielectric layer 115 and the second interlayer dielectric layer 114.

In this embodiment, the third interlayer dielectric layer 115 and the second interlayer dielectric layer 114 on the top of the bottom source-drain plug 112 are removed by a dry etching process, so as to form a source-drain contact hole 131 exposing the bottom source-drain plug 112.

It should be noted that, in the process of forming the source/drain contact hole 131, the method further includes: and removing the bottom residual layer 146 on the top of the bottom source drain plug 112. In the process of etching the third interlayer dielectric layer 115 and the first interlayer dielectric layer 102, the bottom residual layer 146 can also play a role in stopping etching, so that the probability that the bottom source drain plug 112 is over-etched is reduced.

Referring to fig. 15, a gate plug 116 is formed in the gate contact hole 130, and a top source drain plug 117 is formed in the source drain contact hole 131.

Gate plug 116 is used to make electrical connections between gate structure 107 and external circuitry or other interconnect structures.

The top source drain plug 117 and the bottom source drain plug 112 constitute a source drain plug, so that the source drain doping layer 108 is electrically connected with other interconnection structures or external circuits.

Specifically, after filling the gate contact hole 130 and the source drain contact hole 131 with a conductive material, performing planarization on the conductive material, and keeping the conductive material in the gate contact hole 130 as the gate plug 116 and the conductive material in the source drain contact hole 131 as the top source drain plug 117.

The detailed description of the gate plug 116 and the top source drain plug 117 is omitted here.

In this embodiment, under the action of the etching barrier layer 113, self-alignment is easily achieved in the process of forming the Gate Contact hole 130 and the source/drain Contact hole 131, so that the Gate plug 116 can be formed above the Gate structure 107 of the Active region, and the Gate plug 116 is an Active Gate Contact hole plug (COAG). Compared with the scheme that the gate plug is in contact with the gate structure located in the isolation region, the embodiment omits the portion of the gate structure 107 located in the isolation region, which is beneficial to saving the area of the chip and realizing further reduction of the chip size.

The same parts of the embodiment of the present invention as those of the first embodiment are not described herein again, and the embodiment of the present invention is different from the first embodiment in that:

referring to fig. 16, the gate contact hole 230 and the source-drain contact hole 231 are formed in the same step.

The gate contact hole 230 and the source/drain contact hole 231 are formed in the same step, so that the process steps are simplified, the process cost is reduced, and the manufacturing efficiency is improved.

In addition, in this embodiment, the gate capping layer 206 is formed at the top of the gate structure 207, and the bottom residual layer 246 is formed at the top of the bottom source-drain plug 212, so that the gate capping layer 206 and the bottom residual layer 246 can be used as etching stop positions in the process of etching the third interlayer dielectric layer 215, the second interlayer dielectric layer 214 and the first interlayer dielectric layer 202, the gate contact hole 230 and the source-drain contact hole 231 can be easily formed in the same etching step, and the damage to the gate contact hole 230 and the source-drain contact hole 231 is small.

For a detailed description of the forming method of the present embodiment, please refer to the corresponding description of the first embodiment, which is not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. a semiconductor structure, is characterized in that, comprises:

a substrate, a gate structure is formed on the substrate, source and drain doped layers are formed in the substrate on both sides of the gate structure, a first interlayer dielectric layer is formed on the substrate exposed by the gate structure, and the a first interlayer dielectric layer covers the top of the gate structure;

a bottom source-drain plug, located in the first interlayer dielectric layer between the gate structures and connected to the source-drain doped layer, the top of the bottom source-drain plug is lower than the first interlayer the top of the dielectric layer is higher than the top of the gate structure;

a second interlayer dielectric layer, penetrating the first interlayer dielectric layer on the top of the bottom source-drain plug;

an etch stop layer, located between the sidewall of the second interlayer dielectric layer and the first interlayer dielectric layer;

a gate plug, penetrating the first interlayer dielectric layer between the adjacent etching barrier layers, and the bottom of the gate plug is connected to the gate structure;

The top source-drain plug penetrates through the second interlayer dielectric layer between the adjacent etching barrier layers, and the bottom of the top source-drain plug is connected to the bottom source-drain plug.

2 . The semiconductor structure of claim 1 , wherein in the first interlayer dielectric layer located at the top of the gate structure, the surface opposite to the sidewall of the etch stop layer is the first side surface. 3 . , the surface opposite to the side wall of the bottom source-drain plug is a second side surface, and the first side surface is protruding relative to the second side surface.

3 . The semiconductor structure of claim 1 , wherein the semiconductor structure further comprises: a protective layer located on the sidewall of the bottom source-drain plug, and the top of the protective layer is connected to the bottom source. 4 . The top of the drain plug is flush.

4 . The semiconductor structure of claim 1 , wherein the semiconductor structure further comprises: a third interlayer dielectric layer located on the first interlayer dielectric layer, the second interlayer dielectric layer and the etch stopper. 5 . the top of the layer;

The gate plug and the top source-drain plug also penetrate the third interlayer dielectric layer.

5 . The semiconductor structure of claim 1 , wherein a direction parallel to the surface of the substrate and perpendicular to the sidewall of the gate structure is a lateral direction, and a lateral dimension of the etch stop layer is 50 angstroms. 6 . meters to 200 angstroms.

6 . The semiconductor structure of claim 1 , wherein the distance from the top of the bottom source-drain plug to the top of the first interlayer dielectric layer is 50 angstroms to 500 angstroms. 7 .

7 . The semiconductor structure of claim 2 , wherein the protruding size of the first side surface relative to the second side surface is 50 angstroms to 200 angstroms. 8 .

8 . The semiconductor structure of claim 3 , wherein a direction parallel to the surface of the substrate and perpendicular to the sidewall of the gate structure is a lateral direction, and a lateral dimension of the protective layer is 50 to 50 angstroms. 9 . 200 Angstroms.

9. The semiconductor structure of claim 1, wherein the material of the etch stop layer comprises one or more of silicon nitride, silicon carbide and silicon oxycarbide.

10. The semiconductor structure of claim 3, wherein a material of the protective layer comprises one or more of silicon nitride and silicon oxycarbonitride.

11. A method for forming a semiconductor structure, comprising:

A substrate is provided, a gate structure is formed on the substrate, source and drain doped layers are formed in the substrate on both sides of the gate structure, and a first interlayer dielectric layer is formed on the substrate exposed by the gate structure, so the first interlayer dielectric layer covers the top of the gate structure;

forming an opening through the first interlayer dielectric layer between the gate structures, and the opening exposes the source-drain doped layer;

forming a bottom source-drain plug in the opening, the top of the bottom source-drain plug is lower than the top of the opening, and the top of the bottom source-drain plug is higher than the top of the gate structure;

forming an etch barrier layer on the sidewall of the opening exposed by the bottom source-drain plug;

After forming the etching barrier layer, forming a second interlayer dielectric layer in the remaining openings;

forming a gate contact hole located between the adjacent etching barrier layers and passing through the first interlayer dielectric layer, and the gate structure is exposed at the bottom of the gate contact hole;

forming a source-drain contact hole located between the adjacent etching barrier layers and passing through the second interlayer dielectric layer, and the bottom source-drain plug is exposed at the bottom of the source-drain contact hole;

A gate plug is formed in the gate contact hole, and a top source-drain plug is formed in the source-drain contact hole.

12 . The method for forming a semiconductor structure according to claim 11 , wherein a direction parallel to the surface of the substrate and perpendicular to the sidewall of the gate structure is a lateral direction; 12 .

After forming the opening through the first interlayer dielectric layer between the gate structures, and before forming the bottom source-drain plug in the opening, the method further includes: at a position close to the top of the opening, adjusting a preset height performing lateral etching on the first interlayer dielectric layer exposed on the sidewall of the opening;

In the step of forming the bottom source-drain plug in the opening, the distance from the top of the bottom source-drain plug to the top of the first interlayer dielectric layer is equal to the predetermined height.

13 . The method for forming a semiconductor structure according to claim 12 , wherein after forming the opening through the first interlayer dielectric layer between the gate structures, the sidewall of the opening with a preset height is exposed. 14 . Before performing the lateral etching on the first interlayer dielectric layer, the method further includes: forming a protective layer on a part of the sidewall of the opening, and the protective layer exposes the sidewall of the opening with a preset height;

In the step of performing lateral etching on the first interlayer dielectric layer exposed from the sidewall of the opening with a preset height, the lateral etching is performed using the protective layer as a mask.

14. The method for forming a semiconductor structure according to claim 13, wherein the step of forming the protective layer comprises: forming on the sidewall and bottom of the opening and on the top of the first interlayer dielectric layer a protective material layer; a filling layer is formed in the opening, and the distance from the top of the filling layer to the top of the first interlayer dielectric layer is the preset height; the protective material layer exposed by the filling layer is removed, The remaining said protective material layer is used as a protective layer;

After removing the protective material layer exposed by the filling layer, the method further includes: removing the filling layer.

15 . The method for forming a semiconductor structure according to claim 12 , wherein a dry etching process is used to laterally etch the first interlayer dielectric layer exposed on the sidewall of the opening with a preset height. 16 .

16. The method for forming a semiconductor structure according to claim 14, wherein the material of the filling layer comprises an organic material.

17 . The method for forming a semiconductor structure according to claim 14 , wherein a dry etching process is used to remove the protective material layer exposed by the filling layer. 18 .

18. The method for forming a semiconductor structure according to claim 11, wherein the step of forming an etch stop layer on the sidewall of the opening exposed by the bottom source-drain plug comprises: exposing the bottom source-drain plug The sidewall of the opening, the top of the bottom source-drain plug, and the top of the first interlayer dielectric layer form an etching stopper material layer, and the etching stopper material layer located on the sidewall of the opening serves as an etching stopper layer ;

The step of forming the second interlayer dielectric layer in the remaining openings includes: forming a dielectric material layer in the remaining openings, the dielectric material layer covering the etch stop material layer; The top of the interlayer dielectric layer is used as a stop position, the dielectric material layer is subjected to a planarization process, and the remaining dielectric material layer is used as the second interlayer dielectric layer, wherein, during the planarization process, the removal of the etch stop material layer above the top of the first interlayer dielectric layer.

19. The method for forming a semiconductor structure according to claim 13, wherein the step of forming the bottom source-drain plug comprises: filling the opening with a conductive material layer; using the first interlayer dielectric layer The top of the protective layer is used as a stop position, and the conductive material layer is planarized; after the planarization process, the top of the protective layer is used as a stop position to etch back a partial thickness of the conductive material layer, and etch back The remaining conductive material layer after etching serves as the bottom source-drain plug.

20 . The method for forming a semiconductor structure according to claim 11 , wherein after forming the second interlayer dielectric layer and before forming the gate contact hole and the source-drain contact hole, the method further comprises: before the gate contact hole and the source-drain contact hole are formed. A third interlayer dielectric layer is formed on top of the first interlayer dielectric layer and the second interlayer dielectric layer;

In the step of forming the gate contact hole, the gate contact hole penetrates the third interlayer dielectric layer and the first interlayer dielectric layer;

In the step of forming the source-drain contact hole, the source-drain contact hole penetrates the third interlayer dielectric layer and the second interlayer dielectric layer.

21. The method for forming a semiconductor structure according to claim 14, wherein the protective material layer is formed by an atomic layer deposition process.

22. The method of claim 11, wherein the gate contact hole and the source-drain contact hole are formed in the same step.