CN114650073B - Linearization correction method and device for radio frequency receiver - Google Patents

Abstract

The invention belongs to the technical field of radio frequency integrated circuits, and particularly relates to a linearization correction method and device of a radio frequency receiver. The invention comprises the following steps: the device comprises a radio frequency receiver, an active combiner, a second-order intermodulation component generator, an amplitude regulator, a phase regulator, a baseband multiplier and an analog switch; the input differential radio frequency signal is amplified by a main path and a correction branch circuit to obtain a differential linear baseband signal output; in the correction branch, an input radio frequency signal is converted into a second-order intermodulation product by a second-order intermodulation product generator, amplitude phase conditioning is carried out, and multiplication operation is carried out on the second-order intermodulation product and an output signal of a main path receiver to obtain a conditioned third-order intermodulation distortion component; the third order intermodulation distortion component is superimposed on the third order distortion component in the receiver output signal by an active combiner and cancelled in the final output signal. The invention suppresses the distortion in the signal, improves the linear fundamental frequency term, and realizes higher signal-to-noise ratio and communication effect.

Description

A linearization correction method and device for a radio frequency receiver

technical field

The invention relates to a linearization correction method and device, in particular to a linearization correction method and device for a radio frequency receiver.

Background technique

Communication circuits usually have intermodulation distortion and intermodulation distortion.

Non-linear DUT (such as LNA, PA, tower amplifier), when multiple frequency signals are input, the various spectral components will interact to generate new spectral components (spectrum regeneration); when the input signal is small enough, the amplifier works online In the neutral region, the intermodulation distortion will not deteriorate and remain at a relatively balanced level; as the power input to the DUT increases, the amplifier gradually enters the compression region, and the intermodulation distortion will deteriorate rapidly.

Two or more signals of different frequencies pass through amplifiers or speakers to generate new frequency components. This distortion is usually generated by active devices (such as transistors and electronic tubes) in the circuit. The size of the distortion is related to the output power. Because these newly generated frequency components have no similarity with the original signal, less intermodulation distortion is also easily perceived by the human ear.

Intermodulation distortion (intermodulation distortion) refers to the sum and difference distortion of an input signal introduced by the amplifier. For example, intermodulation distortion components are generated when a mixed signal is fed to an amplifier.

Intermodulation distortion refers to the distortion caused by mutual modulation of signals. The word modulation originally refers to a technique used in communication technology to improve the efficiency of signal transmission. Because the original signal containing sound, image, text, etc. is "added" to the high-frequency signal, and then the composite signal is sent out at the same time. This process and method of "adding" high and low frequencies is called modulation technology, and the synthesized signal is called modulated signal. In addition to retaining the main characteristics of high-frequency signals, modulated signals also contain all the information of low-frequency signals.

The research on the linearization technology of radio frequency receivers has always been the technical focus of continuous attention. With the congestion and density of wireless frequency protocols, there are more and more interferences in the available spectrum, which challenges the linear performance of monolithic integrated wireless receiver front-ends. It is also getting more and more serious. In the sub-6GHz frequency band, mainstream receiver architectures include LNA+MIXER+TIA structure and mixer front-end structure. Both structures have their own performance advantages and disadvantages. However, in terms of small-signal linearity, both structures have considerable room for improvement. In principle, each module in the circuit contributes more or less nonlinear components when performing linear amplification processing. Therefore, the linearization technology of the circuit units in the two receivers becomes more and more important, if one wants to obtain high linearity capability at the system level.

In retrospect, the representative literature on the linearization technique of the mixer circuit is [W.Cheng, A.J.Annema, G.J.M.Wienk, and B.Nauta, "A Flicker Noise/IM3 Cancellation Technique for Active Mixer Using Negative Impedance," IEEE J. Solid-State Circuits, vol.48, no.10, pp.2390–2402, Oct.2013, doi:10.1109/JSSC.2013.2272339.]. In this report, as shown in Figure 2, the source node of the mixer switch adopts a negative resistance topology, which can cancel the inherent IM3 component generated in the mixer. The measured IIP3 result reached 11.8dBm. In addition to suppressing the third-order nonlinearity, this method also significantly improves the flicker noise of the current commutation mixer.

On the other hand, for low-noise amplifier circuits, common linearization techniques include derivative superposition and post-distortion techniques. For example [B.Guo, G.Wen, and S.An, "6.8mW 15dBm IIP3 CMOS common-gate LNA employing post-linearisation technique," Electron.Lett., vol.50, no.3, pp.149–151, 2014.] A post-distortion technology was proposed to improve IIP3, which achieved a point frequency improvement effect better than 8dB, as shown in Figure 3. Later, in order to improve the linearization effect of broadband, digital auxiliary technology was introduced to adjust the distortion component as the frequency of the input signal changes, so as to balance the final linear output signal [representative literature, B.Guo, J. Chen, H.Chen, and X.Wang, "A 0.1–1.4GHz inductorless low-noise amplifier with 13dBm IIP3 and24dBm IIP2 in 180nm CMOS," Mod.Phys.Lett.B, vol.32, no.02, p.1850009 ,2018, as shown in Figure 4]. Later, the literature [H.Yu, Y.Chen, C.C.Boon, P.-I.Mak, and R.P.Martins, "A 0.096-mm$^{2}～1$–20-GHz Triple-Path Noise-Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration,”IEEE Trans. 】With the help of advanced process lines, the performance effect of ultra-wideband is designed for the same circuit. However, it is noticed that its IP3 linearity fluctuates sharply within the bandwidth, and it cannot linearly amplify signals in all passbands.

From the design of the LNA+MIXER+TIA receiving system, the LNA module mainly contributes the third-order distortion component (hereinafter referred to as IP3); the second-order distortion component (hereinafter referred to as IP2) mainly comes from the random mismatch of the mixer; The baseband TIA affects the second-order and third-order distortion components at the same time, and requires sufficient feedback depth to ensure the linear processing capability of the passive feedback network; in general, based on traditional isolated module linearization circuit technology, it is difficult for us to guarantee circuit-level Linked together, it presents high linearity characteristics as a whole, because some complex nonlinear behaviors may cause undesired linearity degradation behaviors between circuit modules (such as second-order interaction mechanisms, crossover caused by capacitive memory characteristics at high frequencies) modulation).

Therefore, it can be concluded that the technical situation is as follows: the previous linearization technology was more innovative and improved in the circuit module unit. Neither can guarantee the overall linear performance of the circuit after system integration. The linearization of the circuit mostly presents the characteristics of point frequency or narrowband, which cannot meet the needs of today's broadband communication. Also, for current direct conversion receivers, both IP2 and IP3 are linearity metrics to consider. The previous technology is more reflected in the design optimization of IP3. These limitations call for new solutions.

Contents of the invention

Aiming at the problems existing in the background technology, the present invention provides a linearization correction method and device for a radio frequency receiver, the purpose of which is to suppress the distortion in the signal, improve the linear fundamental frequency term, and achieve a higher signal-to-noise ratio and communication effect.

The present invention solves the above technical problems and provides the following technical solutions:

A linearization correction method for a radio frequency receiver, comprising the following steps:

Step 1: Input the dual-tone signals frf1 and frf2, set the amplitude correction range of the dual-tone signal as Prf[1, 2, 3...N], and set the phase correction range of the dual-tone signal as Δf[1, 2, 3...M]; Where Δf=f1-f2, and the initial parameter is [Prf _i ,Δf _j ];

Step 2: Disconnect the correction branch switches sw1-3, and only measure the fundamental frequency amplitude P1st and the third-order intermodulation distortion amplitude P3rd at the output end when the main path is working; and calculate the initial value result of IP3;

Step 3: Close the correction branch switch sw1~3, and the auxiliary path can be connected. At this time, the amplitude of the linear feedforward branch is adjusted by controlling the switch K5-9, the resistor R8-11 and the resistor R13-15; Variable resistor R18 and variable capacitor C9 are used to correct the phase adjustment;

When the correction branch is enabled, re-measure the amplitude P1st and P3rd of the output terminal of the final stage of the receiver, and obtain the result after IP3 correction;

Step 4: Combining the initial IP3 results without correction, compare the results after IP3 correction, and obtain the effect of IP3 before and after correction improvement ΔIP3;

Repeat step 3 until the correction effect reaches the expected value; and record that when [Prf _i ,Δf _j ] is input, the obtained correction cell information is [A _ij ,φ _ij ];

Step 5: Carry out a new round of calibration and adjustment of different signal powers Prf _i and signal spacing Δf _j until all input powers and baseband bandwidth ranges are covered, then the calibration process ends;

该校正数据存放于接收机后端DSP的查找表中供调用。The obtained storage value matrix is [A _ij ] _{M, N} and

The correction data is stored in the look-up table of the DSP at the back end of the receiver for calling.

Preferably, the correction branch includes an intermodulation distortion correction branch for correcting third-order intermodulation distortion and an intermodulation distortion correction branch for correcting second-order intermodulation distortion;

The intermodulation distortion correction branch includes: a second-order intermodulation component generator, an amplitude regulator, a phase regulator, an amplifier A2 and a baseband multiplier;

The intermodulation distortion correction branch includes: a second-order intermodulation component generator, an amplitude regulator, and a phase regulator.

Preferably, the device for implementing a linearization correction method for a radio frequency receiver includes a main path for receiving and amplifying signals and an intermodulation distortion correction branch for correcting signals;

The main path consists of sequentially coupled input, RF receiver, active combiner and output;

The intermodulation distortion correction branch includes sequentially coupled second-order intermodulation product generators, amplitude regulators, phase regulators, amplifier A2 and baseband multipliers;

The input terminal includes ports Vin+ and Vin-; the output terminal includes ports Vout+ and Vout-;

The first input terminal of the radio frequency receiver is coupled to the port Vin+, and the second input terminal of the radio frequency receiver is coupled to the port Vin-;

The first input end of the active combiner is coupled to the first output end Vout1 of the radio frequency receiver, and the second input end of the active combiner is coupled to the second output end Vout2 of the radio frequency receiver; One output port constitutes port Vout+, and the second output port of the active combiner constitutes port Vout-;

The first input terminal of the second-order intermodulation component generator is coupled to the port Vin+ through the switch K1; the second input terminal of the second-order intermodulation component generator is coupled to the port Vin- through the switch K2;

The first output terminal of the second-order intermodulation component generator is coupled to the first input terminal of the amplitude regulator, and the second output terminal of the second-order intermodulation component generator is coupled to the second input terminal of the amplitude regulator;

The first output terminal of the amplitude regulator is coupled to the first input terminal of the phase regulator, and the second output terminal of the amplitude regulator is coupled to the second input terminal of the phase regulator;

The first output end of the phase adjuster is coupled to the first input end of the baseband multiplier, and the second output end of the phase adjuster is coupled to the second input end of the baseband multiplier;

The positive input terminal Vin1 of the amplifier A2 is coupled to the first output terminal Vout1 of the radio frequency receiver, the reverse input terminal Vin2 of the amplifier A2 is coupled to the second output terminal Vout2 of the radio frequency receiver, and the positive phase output terminal Vout3 of the amplifier A2 is coupled to the baseband multiplier The third input terminal, the inverting output terminal Vout4 of the amplifier A2 is coupled to the fourth input terminal of the baseband multiplier;

The first output terminal of the baseband multiplier is coupled to the third input terminal of the active combiner through the switch K3, and the second output terminal of the baseband multiplier is coupled to the fourth input terminal of the active combiner through the switch K4;

The input differential radio frequency signal is input by the port Vin+ and Vin-, and is respectively amplified by the main path and the correction branch, and the differential linear baseband signal is output at the Vout+ and Vout-ports;

Input the differential RF signal, in the correction branch, the input RF signal is converted into a second-order intermodulation product by the second-order intermodulation component generator, and the amplitude is regulated by the amplitude regulator, and the phase is regulated by the phase regulator , the conditioned signal is multiplied with the differential linear baseband signal output by the main path RF receiver through the amplifier A2, and then superimposed with the differential linear baseband signal output by the RF receiver through an active combiner to obtain an output signal, which is passed through After the source combiner, the third-order distortion components are canceled, and finally the output signal only contains the linear fundamental frequency term.

Preferably, the active combiner includes a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor R28, and an amplifier A1;

One end of the resistor R23 is connected to the positive input terminal Vin3 of the amplifier A1, and the other end forms the first input terminal of the active combiner; one end of the resistor R25 is connected to the negative input terminal Vin4 of the amplifier A1, and the other end forms an active combiner The second input terminal of the device;

One end of the resistor R26 is connected to the negative input terminal Vin4 of the amplifier A1, and the other end forms the third input terminal of the active combiner; one end of the resistor R24 is connected to the positive input terminal Vin3 of the amplifier A1, and the other end forms an active combiner The fourth input terminal of the device;

One end of the resistor R27 is connected to the positive input terminal Vin3 of the amplifier A1, the other end is connected to the negative output terminal Vout5 of the amplifier A1, one end of the resistor R28 is connected to the negative input terminal Vin4 of the amplifier A1, and the other end is connected to the positive output of the amplifier A1 Terminal Vout6 is connected;

The negative output terminal Vout5 of the amplifier A1 forms the first output terminal of the active combiner, and the positive output terminal Vout6 of the amplifier A1 forms the second output terminal of the active combiner.

Preferably, the second-order intermodulation component generator includes: NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, NMOS transistor M4, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, resistor R1 , resistance R2, resistance R3, resistance R4, resistance R5 and resistance R6;

The first input terminal of the second-order intermodulation component generator is connected to the gate terminal of the NMOS transistor M3 of the second-order intermodulation component generator and one end of the resistor R1 through the capacitor C1, and the second input terminal of the second-order intermodulation component generator is connected through The capacitor C2 is connected to the gate terminal of the NMOS transistor M2 of the second-order intermodulation component generator and one terminal of the resistor R2;

The source terminal of the NMOS transistor M1 is connected to the drain terminal of the NMOS transistor M2 and the drain terminal of the NMOS transistor M3, the drain terminal of the NMOS transistor M1 is connected to the gate terminal of the NMOS transistor M4 through a capacitor C5, and the drain terminal of the NMOS transistor M1 is connected through a parallel connection. The resistor R3 and the capacitor C3 are connected to the power supply voltage Vdd, the gate terminal of the NMOS transistor is connected to the bias voltage Vb2, and the source terminal of the NMOS transistor M2 and the source terminal of the NMOS transistor M3 are grounded;

The drain end of the NMOS transistor M4 is connected to the power supply voltage Vdd through the parallel resistor R5 and capacitor C4, and the drain end of the NMOS transistor M4 forms the first output end of the second-order intermodulation component generator through the capacitor C7; the source end of the NMOS transistor M4 The resistor R6 and the capacitor C6 connected in parallel are grounded, and the source end of the NMOS transistor M4 constitutes the second output end of the second-order intermodulation component generator; the gate end of the NMOS transistor M4 is connected to one end of the capacitor C5 and one end of the resistor R4, and the resistor The other end of R4 is connected to the bias voltage Vb3;

The other ends of the resistors R1 and R2 are connected to the bias voltage Vb1.

Preferably, the amplitude regulator includes: NMOS transistor M5, NMOS transistor M6, NMOS transistor M13, NMOS transistor M14, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14, resistor R15, Resistor R9a, resistor R11a, capacitor C8, switch K5, switch K6, switch K7, switch K8, switch K9;

The first input terminal of the amplitude regulator is connected to the gate terminal of the NMOS transistor M5, and the second input terminal of the amplitude regulator is connected to the gate terminal of the NMOS transistor M6 through a capacitor C8;

The gate end of the NMOS transistor M5 is connected to one end of the capacitor C7 and one end of the resistor R7, and the other end of the resistor R7 is connected to the bias voltage Vb4;

The drain end of the NMOS transistor M5 is connected to the power supply voltage Vdd through the resistor R9a, the resistor R9 and the resistor R8 in sequence, the source end of the NMOS transistor M5 is connected to the drain end of the NMOS transistor M13, and the source end of the NMOS transistor M13 is grounded;

The switch K7 and the resistor R13 connected in series are connected in parallel with the switch K8 and the resistor R14 connected in series, and the switch K9 and the resistor R15 connected in series;

The drain end of NMOS transistor M13 is connected to one end of switch K7, switch K8 and switch K9, the drain end of NMOS transistor M14 is connected to one end of resistor R13, resistor R14 and resistor R15, the source end of NMOS transistor M14 is grounded, and the end of NMOS transistor M6 The source terminal is connected to the drain terminal of the NMOS transistor M14, and the gate terminal of the NMOS transistor M13 and the gate terminal of the NMOS transistor M14 are connected to the bias voltage Vb0;

The gate end of the NMOS transistor M6 is connected to one end of the capacitor C8 and one end of the resistor R12, and the other end of the resistor R12 is connected to the bias voltage Vb5;

The drain end of the NMOS transistor M6 is connected to the power supply voltage Vbb through the resistor R11a, the resistor R11 and the resistor R10 in turn, one end of the switch K5 is connected to one end of the resistor R8 and the resistor R9, and the other end of the switch K5 is connected to one end of the resistor R10 and the resistor R11 ;

One end of switch K6 is connected with resistor R9 and one end of resistor R9a, and the other end of switch K6 is connected with resistor R11 and one end of resistor R11a;

One end of the resistor R11 and the resistor R11a forms the first output end of the amplitude regulator, and one end of the resistor R9 and the resistor R9a forms the second output end of the amplitude adjuster.

Preferably, the phase adjuster includes: a resistor R16, a resistor R17, a resistor R18, and a capacitor C9;

The resistor R16 and the resistor R17 connected in series are connected in parallel with the resistor R18 connected in series and the capacitor C9;

One end of the resistor R16 and the resistor R18 constitutes the first input end of the phase regulator, and one end of the resistor R17 and the capacitor C9 constitutes the second input end of the phase regulator;

One end of the resistor R18 and the capacitor C9 is connected to one end of the resistor R20 through the capacitor C11 to form the first output end of the phase regulator;

One end of the resistor R16 and the resistor R17 is connected to one end of the resistor R19 through the capacitor C10 to form the second output end of the phase regulator;

The other end of the resistor R19 and the other end of the resistor R20 are connected to the bias voltage Vb6.

Preferably, the baseband multiplier includes: NMOS transistor M7, NMOS transistor M8, NMOS transistor M9, NMOS transistor M10, NMOS transistor M11, NMOS transistor M12, NMOS transistor M15, NMOS transistor M16, resistor R19, resistor R20, resistor R21 , resistance R22;

The gate end of the NMOS transistor M9 is connected to the gate end of the NMOS transistor M10 to form the first input end of the baseband multiplier;

The gate terminal of the NMOS transistor M8 is connected to the gate terminal of the NMOS transistor M11 to form a second input terminal of the baseband multiplier;

The drain end of the NMOS transistor M9 is connected to the drain end of the NMOS transistor M11 and connected to the power supply voltage Vbb through the resistor R22, the drain end of the NMOS transistor M8 is connected to the drain end of the NMOS transistor M10 and connected to the power supply voltage Vbb through the resistor R21, and the NMOS transistor M7 The drain terminal is connected to the power supply voltage Vbb;

The drain end of the NMOS transistor M9 is connected to the drain end of the NMOS transistor M11 to form the first output end of the baseband multiplier;

The drain end of the NMOS transistor M8 is connected to the drain end of the NMOS transistor M10 to form a second output end of the baseband multiplier;

The gate terminal of the NMOS transistor M7 is connected to the non-inverting output terminal Vout3 of the amplifier A2, the drain terminal of the NMOS transistor M12 is connected to the power supply voltage Vbb, and the gate terminal of the NMOS transistor M12 is connected to the inverting output terminal Vout4 of the amplifier A2;

The source end of the NMOS transistor M7, the source end of the NMOS transistor M8, and the source end of the NMOS transistor M9 are connected to the drain end of the NMOS transistor M15;

The source end of the NMOS transistor M10, the source end of the NMOS transistor M11 and the source end of the NMOS transistor M12 are connected to the drain end of the NMOS transistor M16;

The source terminal of the NMOS transistor M15 is grounded, the source terminal of the NMOS transistor M16 is grounded, and the gate terminals of the NMOS transistor M15 and the gate terminals of the NMOS transistor M16 are connected to the bias voltage Vb0.

In summary, owing to adopting above-mentioned technical scheme, the beneficial effect of the present invention is:

1. The present invention uses an additional parallel correction branch to offset the nonlinearity on the main path. The circuit proposed by the present invention covers the main path and the correction branch. The main path includes a radio frequency receiver and an active combiner; The correction branch includes a second-order intermodulation component generator, an amplitude regulator, a phase regulator, and a baseband multiplier. It employs an additional parallel correction branch to counteract nonlinearities on the main path. A nonlinear component with the same magnitude and opposite sign as the main path is generated on the correction branch. Through the linear superposition of the final stage combiner, the nonlinear signal component of the receiving path is eliminated, and a linear signal is obtained at the output.

2. This design is flexible, because the correction branch operates at baseband frequency, consumes low power, and is not as sensitive to parasitic effects as radio frequency circuits.

3. Different from the previous modular unit linearization technology, the present invention performs linearization correction on the entire front end of the receiver. The invention does not depend on the topological structure inside the radio frequency receiver and the radio frequency coverage range, and has wide applicability.

4. Different from the traditional IP3 optimization technology, the present invention can realize the simultaneous optimization of IP2 and IP3, and adapt to the application requirements of current direct conversion receivers.

5. Different from the linearization and narrow-band characteristics of traditional circuits, the present invention can optimize and adjust the correction branch in a suitable state by means of digital control technology to obtain a linearization effect within a wide frequency range. It is more competent for today's broadband communication needs.

Description of drawings

Fig. 1 is a diagram of specific technical steps of linearization correction proposed by the present invention.

Figure 2 is a mixer linearization structure based on negative resistance technology.

Figure 3 is the linearization structure of the low noise amplifier based on post-distortion technology.

Fig. 4 is the linearization structure of the broadband low noise amplifier based on the numerical aid technique.

Fig. 5 is a structural diagram of a specific circuit implementation of the linearization correction proposed by the present invention.

Fig. 6 is a schematic block diagram of the linearization correction proposed by the present invention.

Fig. 7 is a structure diagram of a phase compensation network and a diagram of transfer amplitude and phase characteristics.

Fig. 8 is a comparison diagram of the change of the noise figure of the receiver before and after using the correction branch.

Fig. 9 is a comparison diagram of changes in receiver linearity IP3 before and after using the correction branch.

Fig. 10 is a comparison diagram of changes in receiver linearity IP2 before and after using the correction branch.

Detailed ways

In order to make the technical means, features and functions realized by the present invention easier to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in combination with specific embodiments and drawings in the embodiments of the present invention.

In conjunction with Fig. 1-shown in Fig. 10, in order to allow those skilled in the art to better understand the principle of the present invention, the working principle of the radio frequency receiver linearization circuit proposed by the present invention is described as follows:

Figure 6 shows a simplified block diagram of the linearization correction technical solution. It can be seen that the linearization scheme is implemented by adding an auxiliary path in parallel with the original receiver. Along the main path of signal transmission, it is the main channel of the receiver. Specifically, for two-tone RF input signals, frf1 (ie, flo+f1) and frf2 (ie, flo+f2), due to the nonlinear factors of the channel, there will be a large amount of nonlinear spectrum generated on the output side of the receiver . As shown in the figure, it can be seen that the spectrum falling within the band has third-order intermodulation distortion components and second-order intermodulation distortion components. The second-order intermodulation distortion component f1+f2 falling outside the band is usually contributed by the baseband circuit after the mixer; the 2flo+f1+f2 distortion component is contributed by the RF low-noise amplifier. Regardless of the influence of the out-of-band distortion components, we need to compensate and eliminate the second-order and third-order distortion components in the band to improve the linearity of the receiver.

Note that in the auxiliary path, for the two-tone RF input signal, frf1 and frf2. We can obtain intermodulation products f1-f2 and 2flo+f1-f2 through the second-order intermodulation product intermodulation generation circuit. Due to the low-pass filtering characteristics of the baseband channel, the sum frequency term 2flo+f1-f2 is effectively suppressed and ignored. The difference frequency items f1-f2 are multiplied by the amplitude and phase adjustment of the subsequent stage and the multiplier unit circuit, and another set of input signals of the multiplier comes from the fundamental frequency items f1 and f2 of the receiver. As a result, at the output of the multiplier we can get the output spectrum shown in Figure 5. In principle, this fIM3, L fIM3, H component and the fIM3, L fIM3, H component output by the receiver are phase-reversed, and the amplitude is equal, thus passing through the output of the final stage combiner (using an operational amplifier), fIM3, L fIM3, The H component is eliminated. It is also noted that the output frequency of the multiplier also has by-products f1 and f2, so it can be foreseen that the addition of the auxiliary path can also increase the gain of the circuit appropriately. The function of the amplifier A2 is to adjust the amplitude, so that the baseband signal of the main path participates in the multiplier operation with a constant amplitude, so as to avoid additional nonlinear products.

Similar to the nonlinear compensation principle of the third-order intermodulation, the nonlinear compensation of the second-order intermodulation can also be realized accordingly. Looking at the auxiliary path again, unlike the compensation channel of the third-order intermodulation, the second-order intermodulation no longer needs the participation of the multiplier. Only through the adjustment of the amplitude and phase, the second-order intermodulation components can be adjusted and controlled, so that the final-stage combination The superposition of the circuit breaker eliminates the in-band intermodulation components f1-f2 of the main path.

The following takes IP3 calibration as an example. Figure 1 shows the basic steps of the calibration circuit. Similarly, IP2 calibration can also be obtained by reference, and will not be repeated here.

First input the two-tone signals frf1 and frf2, and set its amplitude correction range Prf[1...N] and two-tone spacing range to Δf(f1-f2)[1...M]. And the initial parameter is [Prf _i ,Δf _j ].

Disconnect the correction branch switches sw1~3, and only measure the fundamental frequency amplitude P1st at the output terminal when the main path is working, and the third-order intermodulation distortion amplitude P3rd,

Close the correction branch switch sw1~3, and adjust the amplitude and phase of the linear feedforward branch.

Measure the amplitudes P1st and P3rd of the final stage output of the receiver again,

Combined with the previous results without correction, compare the effect of IP3 before and after correction. If the comparison result fails to meet expectations, continue to adjust the linear feedforward branch until the correction effect reaches the expected value. And record that when [Prf _i ,Δf _j ] is input, the corrected cell information obtained is [A _ij ,φ _ij ], which includes the amplitude and phase circuit control mapping relationship: A01&φ01, A02&φ02, resistance and capacitance in the A2 unit Tuning controls.

Carry out a new round of calibration adjustments with different signal powers Prf _i and signal spacing Δf _j until all ranges are covered. Then the calibration process ends, and the obtained storage value matrix is [A _ij ] _M,N ,

以查找表的形式存放于接收机的dsp中供调用。在某个小区具体位置处的接收机的实际接收过程中，当基站为终端分配导频信息时，终端同时获得了基站发出信号到自己天线口的输入功率电平prf_i信息，结合分配的信道情况，确定实际的本振频率和基带带宽Δf_j。其后，终端DSP通过读取查收表中的校正数据A_ij和φ_ij，对应于特定的输入功率prf_i，和频率间距Δf_j，从而映射为实际的幅度、相位电路控制信息：图6中的模块电路A01和φ01，以及模块电路A02和φ02,A2单元中的电阻、电容调谐控制。这样，受控的辅助路径可以在主路径接收通信数据的时候实时地补偿消除失真分量，保证高动态范围的通信接收质量。As shown in Figure 6, the correction numerical matrix [A _ij ] _M,N ,

It is stored in the dsp of the receiver in the form of a look-up table for calling. In the actual receiving process of the receiver at a specific location in a cell, when the base station assigns pilot information to the terminal, the terminal simultaneously obtains the input power level prf _i information of the signal sent by the base station to its own antenna port, combined with the allocated channel case, determine the actual local oscillator frequency and baseband bandwidth Δf _j . Afterwards, the terminal DSP reads the correction data A _ij and φ _ij in the look-up table, corresponding to the specific input power prf _i , and the frequency spacing Δf _j , so as to map it into the actual amplitude and phase circuit control information: in Figure 6 The module circuit A01 and φ01, and the module circuit A02 and φ02, the resistance and capacitance tuning control in the A2 unit. In this way, the controlled auxiliary path can compensate and eliminate the distortion component in real time when the main path receives communication data, so as to ensure high dynamic range communication reception quality.

It can be seen from the above technical steps that the present invention regards the receiver of the main path as a black box, does not care about the nonlinear relationship between the internal circuits of the receiver, but only obtains the sub-linear components of its output quantitatively, and uses the auxiliary path is eliminated. Therefore, the present invention does not depend on the internal topology of the radio frequency receiver and the radio frequency coverage, and has wide applicability. In the above operation practice, according to the actually acquired nonlinear characteristics of the receiver, the correction parameters can be correspondingly simplified or refined. For example, for a sub-6GHz receiver, the typical baseband frequency is within 20MHz. In such a scenario, the nonlinear behavior is not so sensitive to the change of the frequency spacing Δf, so the sample points of Δf(f1-f2)[1...M] can be significantly reduced. The value of the amplitude correction range Prf[1…N] is also particular. In the small signal range, the growth of P3rd is quite linear, which can reduce the number of sampling points. After Prf>-30dBm, the nonlinear changes are complicated, and high-order products P5rd will also be superimposed. At this time, the range of sampling points around this power level of Prf can be increased to obtain a good overall correction effect.

Referring again to FIG. 5, the second-order intermodulation product generation circuit is generated using the transistor pair M23. For such a structure, after the differential signal is input, the odd-order term including the fundamental frequency is canceled, and the even-order term is retained. Due to the low-pass filtering effect of R3C3 at the load, f1-f2 in the even term is retained and passed to the subsequent stage processing, other higher-order even items are filtered out.

Due to the nonlinear complexity of the main path and the auxiliary path, and the delay difference of the signal transmission, it is difficult to determine the phase of the fIM3, L fIM3, H components obtained by the compensation path and the fIM3, L fIM3, H components output by the main path receiver To the precise 180 reverse, the amplitude matching will inevitably degrade the effect of this method. Therefore, it is necessary to introduce amplitude and phase adjustment units.

The amplitude adjustment circuit shown in Fig. 5 is a differential structure amplifier, and a switch array is designed at the load and the source to adjust the gain amplitude of the amplifier. The gain expression can be abbreviated as

g _m56 R _{8～11,16～17} /(1+g _m56 R _13～15 );

Among them, gm56 is the transconductance of transistor M56, R8-11, R16-17 are load equivalent resistances, R13-15 are source equivalent degeneration resistances. K5-k9 is realized by using mos tubes working in the three-stage tube area. Through the tuning of the gate bias voltage, the size control of the equivalent resistance of the mos tubes can be realized. Combined with the R8-11 R13-15 switch array segment control method, a wide range of gain control tuning can be obtained.

Here, through the regulation of the passive phase shifting network shown in Figure 7, the R16-18C9 network, we can obtain the φ _ij offset (usually less than 90 degrees) we need. For different prf _i , Δf _j , only need to tune R18C9 to get the required φ _ij offset at the position of ω _ij . The amplitude of this network is constant, and the amplitude will not be affected during the phase adjustment process. It allows us to realize the independent tuning of the two parameters of amplitude and phase.

Figure 5 shows the multiplier described, based on the active mixer structure but with modifications. The main path receiver signal is connected to one signal through M7/M12 as a source follower, and the gate of the M8-11 transistor pair is connected to another auxiliary path signal. Here, the M8-11 transistor pair works in the state of small signal amplification, and does not perform periodic switching of current. The advantage is that the high strength of the auxiliary path signal is not required, which reduces the power consumption demand of the front-end circuit; more importantly, the small-signal operation of the multiplier reduces the nonlinear behavior caused by the hard switching of the current in the traditional structure, which effectively guarantees Offset effect for auxiliary paths.

The final stage combiner is a multi-input operational amplifier structure, which requires the operational amplifier unit to provide sufficient gain-bandwidth product to ensure that the combiner performs linear superposition and summation within the receiver bandwidth. The implementation of the analog switch K1-6 in Figure 5 is realized by MOS working in the triode area, and the control of the high and low levels of the gate realizes the switching of the switch. The structure of the variable gain amplifier A2 is similar to the structure of the differential pair for amplitude adjustment, and no separate illustration is given here. Although the correction characteristics of the auxiliary path channel do not depend on the structural characteristics of the radio frequency receiver and the radio frequency range. However, it should be noted that the baseband frequency range constitutes a limitation of use of the present invention. In other words, the circuits of the auxiliary path all work at the baseband frequency, and there must be a compromise between gain and bandwidth. On the premise of matching the baseband bandwidth of the RF receiver, the power consumption and gain of the auxiliary path should be optimized. In addition, for another branch structure used to correct IP2 in the auxiliary path shown in FIG. 6 , the structure of the amplitude adjuster and the phase adjuster used are the same as those shown in FIG. 5 . However, because the magnitude and phase information of the second-order distortion component and the third-order distortion component in the main path are usually significantly different, it is necessary to design an additional amplitude and phase adjustment branch in the auxiliary path to compensate for the second-order distortion.

In this embodiment, a linearization correction circuit of a radio frequency receiver is designed and realized by using a 65nm standard CMOS process, and a dual voltage supply of 1.2/1.8V is used. The radio frequency receiver to be corrected adopts LNA+MIXER+TIA current mode structure, its baseband bandwidth is 20MHz, and the radio frequency bandwidth is 0.5-4GHz. Except for the radio frequency receiver, the remaining power consumption of other circuits in Figure 5 is 18.6mW. The simulated electrical performance is as follows. The noise figure results at the local oscillator frequency of 0.5-4GHz are shown in Figure 8. It can be seen that the introduction of the auxiliary path can generally control the noise figure deterioration within 0.3dB on average. Figure 9 shows the IP3 output results of the circuit at a frequency of 0.5-4GHz. At this time, the input signal power prf=-30dBm, where the intermediate frequency is at 10MHz, and the dual-tone frequency spacing Δf is selected as 2MHz. It can be seen that the use After the auxiliary path, IP3 has been significantly improved in the whole wide frequency range, with an improvement of about 13.5dB. Similarly, in the whole wide-band range, the IP2 improvement effect is shown in Figure 10, and the IP2 has been improved by nearly 20dB. In addition, by adjusting Δf within the baseband bandwidth, and performing the correction steps of the auxiliary path in the figure, it is possible to obtain a high robustness result of IP3 with the change of Δf, on the other hand, increasing the input signal power prf to -15dBm, can also Correspondingly, a similar linearity correction to improve performance is obtained, and no separate graphic display is given here. On the whole, the present invention provides a linearization correction technology for radio frequency receiver circuits. It has the characteristics of good applicability and flexible use, and can be widely used in 5G wireless communication equipment.

It will be apparent to those skilled in the art that the invention is not limited to the details of the above-described exemplary embodiments, but that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Accordingly, the embodiments should be regarded in all points of view as exemplary and not restrictive, the scope of the invention being defined by the appended claims rather than the foregoing description, and it is therefore intended that the scope of the invention be defined by the appended claims rather than by the foregoing description. All changes within the meaning and range of equivalents of the elements are embraced in the present invention. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (8)

1. a linearization calibration method of radio frequency receiver, it is characterized in that: comprise the following steps: Step 1: Input the dual-tone signals frf1 and frf2, set the amplitude correction range of the dual-tone signal as Prf[1, 2, 3...N], and set the phase correction range of the dual-tone signal as Δf[1, 2, 3...M]; Where Δf=f1-f2, and the initial parameter is [Prf _i ,Δf _j ]; Step 2: Disconnect the correction branch switches sw1, sw2, and sw3, and only measure the fundamental frequency amplitude P1st and the third-order intermodulation distortion amplitude P3rd at the output end when the main path is working; and calculate the initial value of IP3; Step 3: Close the correction branch switches sw1, sw2, sw3, the auxiliary path can be connected, at this time, through the control switches K5, K6, K7, K8, K9, resistors R8, R9, R10, R11 and resistors R13, R14, R15 , to adjust the amplitude of the linear feedforward branch; by controlling the variable resistor R18 and the variable capacitor C9, to perform a correction trial of the phase adjustment; When the correction branch is enabled, re-measure the amplitude P1st and P3rd of the output terminal of the final stage of the receiver, and obtain the result after IP3 correction; Step 4: Combining the initial IP3 results without correction, compare the results after IP3 correction, and obtain the effect of IP3 before and after correction improvement ΔIP3; Repeat step 3 until the correction effect reaches the expected value; and record that when [Prf _i ,Δf _j ] is input, the obtained correction cell information is [A _ij ,φ _ij ]; Step 5: Carry out a new round of calibration and adjustment of different signal powers Prf _i and signal spacing Δf _j until all input powers and baseband bandwidth ranges are covered, then the calibration process ends; The obtained storage value matrix is [A _ij ] _{M, N} and The correction data is stored in the look-up table of the DSP at the back end of the receiver for calling. 2. The linearization correction method of a radio frequency receiver according to claim 1, characterized in that: the correction branch includes an intermodulation distortion correction branch for correcting third-order intermodulation distortion and a correction branch for correcting second-order intermodulation distortion. an intermodulation distortion correction branch for intermodulation distortion; The intermodulation distortion correction branch includes: a second-order intermodulation component generator, an amplitude regulator, a phase regulator, an amplifier A2 and a baseband multiplier; The intermodulation distortion correction branch includes: a second-order intermodulation component generator, an amplitude regulator, and a phase regulator. 3. A linearization correction device for a radio frequency receiver, characterized in that: the device for realizing any one of the methods in claim 1 or 2, including a main path for receiving and amplifying signals and a signal for correcting The intermodulation distortion correction branch; The main path consists of sequentially coupled input, RF receiver, active combiner and output; The intermodulation distortion correction branch includes sequentially coupled second-order intermodulation product generators, amplitude regulators, phase regulators, amplifier A2 and baseband multipliers; The input terminal includes ports Vin+ and Vin-; the output terminal includes ports Vout+ and Vout-; The first input terminal of the radio frequency receiver is coupled to the port Vin+, and the second input terminal of the radio frequency receiver is coupled to the port Vin-; The first input end of the active combiner is coupled to the first output end Vout1 of the radio frequency receiver, and the second input end of the active combiner is coupled to the second output end Vout2 of the radio frequency receiver; One output port constitutes port Vout+, and the second output port of the active combiner constitutes port Vout-; The first input terminal of the second-order intermodulation component generator is coupled to the port Vin+ through the switch K1; the second input terminal of the second-order intermodulation component generator is coupled to the port Vin- through the switch K2; The first output terminal of the second-order intermodulation component generator is coupled to the first input terminal of the amplitude regulator, and the second output terminal of the second-order intermodulation component generator is coupled to the second input terminal of the amplitude regulator; The first output terminal of the amplitude regulator is coupled to the first input terminal of the phase regulator, and the second output terminal of the amplitude regulator is coupled to the second input terminal of the phase regulator; The first output end of the phase adjuster is coupled to the first input end of the baseband multiplier, and the second output end of the phase adjuster is coupled to the second input end of the baseband multiplier; The positive input terminal Vin1 of the amplifier A2 is coupled to the first output terminal Vout1 of the radio frequency receiver, the reverse input terminal Vin2 of the amplifier A2 is coupled to the second output terminal Vout2 of the radio frequency receiver, and the positive phase output terminal Vout3 of the amplifier A2 is coupled to the baseband multiplier The third input terminal, the inverting output terminal Vout4 of the amplifier A2 is coupled to the fourth input terminal of the baseband multiplier; The first output terminal of the baseband multiplier is coupled to the third input terminal of the active combiner through the switch K3, and the second output terminal of the baseband multiplier is coupled to the fourth input terminal of the active combiner through the switch K4; The input differential radio frequency signal is input by the port Vin+ and Vin-, and is respectively amplified by the main path and the correction branch, and the differential linear baseband signal is output at the Vout+ and Vout-ports; Input the differential RF signal, in the correction branch, the input RF signal is converted into a second-order intermodulation product by the second-order intermodulation component generator, and the amplitude is regulated by the amplitude regulator, and the phase is regulated by the phase regulator , the conditioned signal is multiplied with the differential linear baseband signal output by the main path RF receiver through the amplifier A2, and then superimposed with the differential linear baseband signal output by the RF receiver through an active combiner to obtain an output signal, which is passed through After the source combiner, the third-order distortion components are canceled, and finally the output signal only contains the linear fundamental frequency term. 4. The linearization correction device of a kind of radio frequency receiver according to claim 3, it is characterized in that: described active combiner comprises resistance R23, resistance R24, resistance R25, resistance R26, resistance R27, resistance R28, amplifier A1; One end of the resistor R23 is connected to the positive input terminal Vin3 of the amplifier A1, and the other end forms the first input terminal of the active combiner; one end of the resistor R25 is connected to the negative input terminal Vin4 of the amplifier A1, and the other end forms an active combiner The second input terminal of the device; One end of the resistor R26 is connected to the negative input terminal Vin4 of the amplifier A1, and the other end forms the third input terminal of the active combiner; one end of the resistor R24 is connected to the positive input terminal Vin3 of the amplifier A1, and the other end forms an active combiner The fourth input terminal of the device; One end of the resistor R27 is connected to the positive input terminal Vin3 of the amplifier A1, the other end is connected to the negative output terminal Vout5 of the amplifier A1, one end of the resistor R28 is connected to the negative input terminal Vin4 of the amplifier A1, and the other end is connected to the positive output of the amplifier A1 Terminal Vout6 is connected; The negative output terminal Vout5 of the amplifier A1 forms the first output terminal of the active combiner, and the positive output terminal Vout6 of the amplifier A1 forms the second output terminal of the active combiner. 5. A linearization correction device for a radio frequency receiver according to claim 3, wherein the second-order intermodulation component generator comprises: NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, NMOS transistor M4, Capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5 and resistor R6; The first input terminal of the second-order intermodulation component generator is connected to the gate terminal of the NMOS transistor M3 of the second-order intermodulation component generator and one end of the resistor R1 through the capacitor C1, and the second input terminal of the second-order intermodulation component generator is connected through The capacitor C2 is connected to the gate terminal of the NMOS transistor M2 of the second-order intermodulation component generator and one terminal of the resistor R2; The source terminal of the NMOS transistor M1 is connected to the drain terminal of the NMOS transistor M2 and the drain terminal of the NMOS transistor M3, the drain terminal of the NMOS transistor M1 is connected to the gate terminal of the NMOS transistor M4 through a capacitor C5, and the drain terminal of the NMOS transistor M1 is connected through a parallel connection. The resistor R3 and the capacitor C3 are connected to the power supply voltage Vdd, the gate terminal of the NMOS transistor is connected to the bias voltage Vb2, and the source terminal of the NMOS transistor M2 and the source terminal of the NMOS transistor M3 are grounded; The drain end of the NMOS transistor M4 is connected to the power supply voltage Vdd through the parallel resistor R5 and capacitor C4, and the drain end of the NMOS transistor M4 forms the first output end of the second-order intermodulation component generator through the capacitor C7; the source end of the NMOS transistor M4 The resistor R6 and the capacitor C6 connected in parallel are grounded, and the source end of the NMOS transistor M4 constitutes the second output end of the second-order intermodulation component generator; the gate end of the NMOS transistor M4 is connected to one end of the capacitor C5 and one end of the resistor R4, and the resistor The other end of R4 is connected to the bias voltage Vb3; The other ends of the resistors R1 and R2 are connected to the bias voltage Vb1. 6. A linearization correction device for a radio frequency receiver according to claim 3, wherein the amplitude adjuster comprises: NMOS transistor M5, NMOS transistor M6, NMOS transistor M13, NMOS transistor M14, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14, resistor R15, resistor R9a, resistor R11a, capacitor C8, switch K5, switch K6, switch K7, switch K8, switch K9; The first input terminal of the amplitude regulator is connected to the gate terminal of the NMOS transistor M5, and the second input terminal of the amplitude regulator is connected to the gate terminal of the NMOS transistor M6 through a capacitor C8; The gate end of the NMOS transistor M5 is connected to one end of the capacitor C7 and one end of the resistor R7, and the other end of the resistor R7 is connected to the bias voltage Vb4; The drain end of the NMOS transistor M5 is connected to the power supply voltage Vdd through the resistor R9a, the resistor R9 and the resistor R8 in sequence, the source end of the NMOS transistor M5 is connected to the drain end of the NMOS transistor M13, and the source end of the NMOS transistor M13 is grounded; The switch K7 and the resistor R13 connected in series are connected in parallel with the switch K8 and the resistor R14 connected in series, and the switch K9 and the resistor R15 connected in series; The drain end of NMOS transistor M13 is connected to one end of switch K7, switch K8 and switch K9, the drain end of NMOS transistor M14 is connected to one end of resistor R13, resistor R14 and resistor R15, the source end of NMOS transistor M14 is grounded, and the end of NMOS transistor M6 The source terminal is connected to the drain terminal of the NMOS transistor M14, and the gate terminal of the NMOS transistor M13 and the gate terminal of the NMOS transistor M14 are connected to the bias voltage Vb0; The gate end of the NMOS transistor M6 is connected to one end of the capacitor C8 and one end of the resistor R12, and the other end of the resistor R12 is connected to the bias voltage Vb5; The drain end of the NMOS transistor M6 is connected to the power supply voltage Vbb through the resistor R11a, the resistor R11 and the resistor R10 in turn, one end of the switch K5 is connected to one end of the resistor R8 and the resistor R9, and the other end of the switch K5 is connected to one end of the resistor R10 and the resistor R11 ; One end of switch K6 is connected with resistor R9 and one end of resistor R9a, and the other end of switch K6 is connected with resistor R11 and one end of resistor R11a; One end of the resistor R11 and the resistor R11a forms the first output end of the amplitude regulator, and one end of the resistor R9 and the resistor R9a forms the second output end of the amplitude adjuster. 7. A linearization correction device for a radio frequency receiver according to claim 3, wherein the phase adjuster comprises: a resistor R16, a resistor R17, a resistor R18, and a capacitor C9; The resistor R16 and the resistor R17 connected in series are connected in parallel with the resistor R18 connected in series and the capacitor C9; One end of the resistor R16 and the resistor R18 constitutes the first input end of the phase regulator, and one end of the resistor R17 and the capacitor C9 constitutes the second input end of the phase regulator; One end of the resistor R18 and the capacitor C9 is connected to one end of the resistor R20 through the capacitor C11 to form the first output end of the phase regulator; One end of the resistor R16 and the resistor R17 is connected to one end of the resistor R19 through the capacitor C10 to form the second output end of the phase regulator; The other end of the resistor R19 and the other end of the resistor R20 are connected to the bias voltage Vb6. 8. A linearization correction device for a radio frequency receiver according to claim 3, wherein the baseband multiplier comprises: NMOS transistor M7, NMOS transistor M8, NMOS transistor M9, NMOS transistor M10, NMOS transistor M11, NMOS tube M12, NMOS tube M15, NMOS tube M16, resistor R19, resistor R20, resistor R21, resistor R22; The gate end of the NMOS transistor M9 is connected to the gate end of the NMOS transistor M10 to form the first input end of the baseband multiplier; The gate terminal of the NMOS transistor M8 is connected to the gate terminal of the NMOS transistor M11 to form a second input terminal of the baseband multiplier; The drain end of the NMOS transistor M9 is connected to the drain end of the NMOS transistor M11 and connected to the power supply voltage Vbb through the resistor R22, the drain end of the NMOS transistor M8 is connected to the drain end of the NMOS transistor M10 and connected to the power supply voltage Vbb through the resistor R21, and the NMOS transistor M7 The drain terminal is connected to the power supply voltage Vbb; The drain end of the NMOS transistor M9 is connected to the drain end of the NMOS transistor M11 to form the first output end of the baseband multiplier; The drain end of the NMOS transistor M8 is connected to the drain end of the NMOS transistor M10 to form a second output end of the baseband multiplier; The gate terminal of the NMOS transistor M7 is connected to the non-inverting output terminal Vout3 of the amplifier A2, the drain terminal of the NMOS transistor M12 is connected to the power supply voltage Vbb, and the gate terminal of the NMOS transistor M12 is connected to the inverting output terminal Vout4 of the amplifier A2; The source end of the NMOS transistor M7, the source end of the NMOS transistor M8, and the source end of the NMOS transistor M9 are connected to the drain end of the NMOS transistor M15; The source end of the NMOS transistor M10, the source end of the NMOS transistor M11 and the source end of the NMOS transistor M12 are connected to the drain end of the NMOS transistor M16; The source terminal of the NMOS transistor M15 is grounded, the source terminal of the NMOS transistor M16 is grounded, and the gate terminals of the NMOS transistor M15 and the gate terminals of the NMOS transistor M16 are connected to the bias voltage Vb0.

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