CN114649017A - How to write a magnetic memory - Google Patents

Abstract

The present application provides a method for writing a magnetic memory. The magnetic memory includes a memory cell array composed of a plurality of memory cells. The memory cell array is connected to the external circuit through word lines, source lines and bit lines. Each of the memory cells is composed of a magnetic tunnel junction and an NMOS transistor. Wherein, for the selected memory cell, the write operation method includes: when the write operation needs to energize from the source line to the bit line direction, setting the source line voltage to the working voltage of the circuit through the write drive circuit, and changing the bit line voltage Set as a negative voltage; when the write operation needs to energize from the bit line to the source line, the source line voltage is set to zero potential through the write drive circuit, and the bit line voltage is set to be equal to or less than all the operating voltage. The present application reduces the work load on the MOS transistor and increases the write drive current, and at the same time safely avoids the short-circuit problem caused by the excessive forward bias of the PN junction.

Description

How to write a magnetic memory

technical field

The present invention relates to the technical field of memory, in particular to a write operation method of a magnetic memory.

Background technique

The principle of magnetic memory (MRAM) is based on a structure called MTJ (magnetic tunnel junction). It consists of two layers of ferromagnetic material sandwiched by a very thin layer of non-ferromagnetic insulating material. When writing the P-state to the selected memory cells in the array (that is, placing the magnetization direction of the memory layer of the MTJ parallel to the reference layer), the write circuit needs to provide a top-down current to the MTJ. At this time, the potential of the bit line BL is high, and the NMOS access transistor is in the normal working mode, providing a large drive current on the write path. When the AP state is to be written to the selected memory cell in the array (that is, the memory layer of the MTJ is magnetized The direction is set to be anti-parallel to the reference layer), and the write circuit needs to provide a bottom-up current to the MTJ. The saturation current of the MOS tube is very sensitive to V _GS . At this time, due to the resistance divider of the MTJ device on the write path, V _GS is greatly reduced, and the MOS tube often cannot provide a large enough drive current to complete the write operation. On a nanometer-scale high process node (eg, 28 nm), the voltage dividing effect of the parasitic resistance connected to the upper line of the write path is not negligible, which weakens the drive capability of the access MOS transistor.

Some manufacturers will optimize the design, as shown in Chinese Patent Publication No. CN 101859599A, increase the gate voltage of the access transistor to offset the loss of V _GS when writing the AP state, but the MOS transistor is usually at 1.2-1.0 Working under the VDD of V will affect its long-term service life. In addition to the influence of the body effect, if V _G is raised, V _SB is also increased accordingly, and the saturation current of the NMOS transistor will be lost.

In another example, US Patent No. US8634232 B2 proposes a design solution for sharing source lines between adjacent memory cells in the same column and different rows. In this scheme, when the AP state is written to the selected memory cell (that is, the write operation needs to be powered from the source line to the bit line), the write driver circuit will bias the voltage of the bit line BL to negative VDD, while the shared The potential of the source line SL is grounded. At this time, the body potential of the access MOS transistor is biased to a large negative bias voltage (such as -VDD) by default, so as to avoid those cells in the same column as the written memory cell, whose access MOS transistor is close to one end of the BL bit line. The forward bias of the PN junction is too large, resulting in a short circuit. However, such a voltage bias will make the voltage drop from the gate of the MOS tube to the substrate too large, causing stress to the MOS tube, thereby affecting the service life of the chip. In addition, the body effect will further reduce the saturation current of the MOS transistor.

Another example is Chinese Patent Publication No. CN 109817253 A, which proposes an MRAM chip array layout that can control the body potential. It makes it possible to change the body potential of this region individually by arranging a deep N well in the MRAM chip array part. During the write operation, the body potential is appropriately increased by Δ, thereby reducing the voltage drop from the gate of the access MOS transistor to the substrate, reducing the body effect, and increasing the write drive saturation current of the access MOS transistor. However, this improvement has limited effect on improving the drive current, especially at advanced semiconductor process nodes (28nm or smaller), and the operating voltage is lower (below 0.9V), this method cannot meet the material requirements.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, the purpose of the present application is to provide a writing operation method of a magnetic memory, a design scheme of applying a negative bias voltage in the direction of the write channel bit line to improve the write driving capability, which is superior to the traditional scheme.

The purpose of this application and the solution to its technical problems are achieved by adopting the following technical solutions.

According to a method for writing a magnetic memory proposed in the present application, the magnetic memory includes a memory cell array composed of a plurality of memory cells, and the memory cell array is connected to the external circuit through word lines, bit lines, and source lines , each of the memory cells is composed of a magnetic tunnel junction and an NMOS transistor. For the selected memory cells, the write operation method includes: when the write operation needs to energize from the source line to the bit line direction, setting the source line voltage to the working voltage of the circuit through the write drive circuit; When the line is energized in the direction of the source line, the source line voltage is set to zero potential by the write driving circuit, and the bit line voltage is set to be equal to or less than the working voltage.

The technical problems of the present application can be further realized by adopting the following technical measures.

Optionally, the body potential of the NMOS transistor of the selected memory cell is grounded.

Optionally, the forward bias voltage of the substrate-to-bit line of the memory cell needs to be lower than the forward conduction voltage of the PN junction formed by the substrate of the NMOS transistor and the active region.

Optionally, the negative voltage is between -0.3V and -0.6V.

Optionally, the memory cell array includes a row address decoder and a column address decoder, which respectively convert the received external address information into selection information of word lines, bit lines and source lines, and obtain the Select the storage unit.

Optionally, the memory cell array includes a write driver and a sense amplifier, and under the control of an external read and write enable signal, read or write operations are performed on the selected memory cells.

Optionally, the write drive and sense amplifiers include a write drive circuit and a sense amplifier; the write drive and sense amplifiers obtain a high-level read operation signal, and when a low-level write operation signal is used, The memory cell performs a read operation, the write driver circuit is disconnected from the bit line and source line of the selected memory cell, and the sense amplifier is connected to the bit line and source line of the selected memory cell. is connected; the write driver and the sense amplifier obtain a low-level read operation signal, and when a high-level write operation signal is used, a write operation is performed on the selected memory cell, and the write driver circuit and the selected memory cell are connected. The bit lines and source lines of the memory cells are connected, and the sense amplifiers are disconnected from the bit lines and source lines of the selected memory cells.

Optionally, when the write operation to the selected memory cell needs to be energized from the bit line to the source line, the write drive circuit sets the voltage of the source line to zero potential, and sets the voltage of the bit line to Operating Voltage. When the write operation to the selected memory cell needs to energize from the source line to the bit line, the write driving circuit sets the voltage of the source line to the working voltage and the voltage of the bit line to the negative voltage.

Optionally, it also includes that the data bus provides m+1-bit data for writing or reading, where m is a natural number greater than 1; the column decoder includes a plurality of multiplexing switches, which are opened according to external address information. A pair of multiplexing switches are respectively connected to the bit line and the source line of the same memory cell, and the same memory cell is the selected memory cell.

In this application, the design scheme of improving the write driving capability by applying a negative bias voltage in the direction of the write channel bit line, while increasing the driving current, significantly reduces the requirements for the gate voltage VG on the access MOS transistor, and reduces the NMOS workload. stress. Extends the service life of the NMOS tube, that is, the MRAM chip. Secondly, the solution of the present invention sets the voltage of the source line SL to VDD when the write operation needs to be energized from the source line to the bit line, and the voltage of the bit line BL is biased in a small negative bias range of -0.3～ -0.6V (the body potential of the access MOS tube is always grounded), which reduces the workload stress on the MOS tube and increases its write drive current, while safely avoiding the above-mentioned problems caused by the excessive forward bias of the PN junction short circuit problem. Third, the present application provides a margin for the design selection of the size of the NMOS and PMOS devices on the write path while improving the write driving capability. That is to say, an NMOS transistor with a smaller area can be used in the MRAM array, or a smaller-sized MUX multiplexing switch can be selected in the column decoder on the write path. The manufacturing cost of the chip is reduced. Fourth, compared with the write operation method of increasing the bulk potential, the read and write operation method of the MRAM chip array layout of the present application can bring about a greater increase in driving current, especially in advanced process nodes where the material flipping voltage is slightly higher. under high conditions.

Description of drawings

In order to explain the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. , for those skilled in the art, other drawings can also be obtained from these drawings without any creative effort.

FIG. 1 is a schematic diagram of a memory structure principle according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an exemplary memory structure;

FIG. 3 is a functional schematic diagram of a write driver and a sense amplifier according to an embodiment of the present application.

Detailed ways

Please refer to the drawings in the accompanying drawings, wherein the same reference numerals represent the same components. The following description is based on illustrated specific embodiments of the present application and should not be construed as limiting other specific embodiments of the present application not detailed herein.

The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the application may be practiced. The directional terms mentioned in this application, such as "up", "down", "front", "rear", "left", "right", "inside", "outside", "side", etc., are for reference only Additional schema orientation. Therefore, the directional terms used are used to describe and understand the present application, rather than to limit the present application.

The terms "first", "second", "third", etc. (if present) in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having", as well as variations thereof, are intended to cover non-exclusive inclusions.

The terms used in the specification of the present application are only used to describe specific embodiments, and are not intended to represent the concepts of the present application. Expressions used in the singular cover expressions in the plural unless the context clearly indicates a different meaning. In the specification of this application, it should be understood that terms such as "including", "having" and "containing" are intended to indicate the existence of the possibility of the features, numbers, steps, actions or combinations thereof disclosed in the specification of the present application, and are not intended to be The possibility that one or more other features, numbers, steps, actions, or combinations thereof may be present or may be added is excluded. The same reference numbers in the drawings refer to the same parts.

The drawings and descriptions are to be regarded as illustrative in nature and not restrictive. In the figures, structurally similar elements are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for understanding and convenience of description, but the present application is not limited thereto.

In the drawings, the configuration ranges of devices, systems, components, and circuits are exaggerated for clarity, understanding, and ease of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

Additionally, in the specification, unless explicitly described to the contrary, the word "comprising" will be understood to mean the inclusion of stated components, but not the exclusion of any other components. Further, in the specification, "on" means above or below the target component, and does not mean necessarily on top based on the direction of gravity.

In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following describes a method for writing a magnetic memory according to the present invention, its specific implementation, structure, Features and their effects are described in detail below.

FIG. 1 is a schematic diagram of a memory structure principle according to an embodiment of the present application. An embodiment of the present application discloses a method for writing a magnetic memory. The magnetic memory includes a memory cell array composed of a plurality of memory cells, and the memory cell array is connected to the external circuit through word lines, source lines and bit lines. , each of the memory cells is composed of a magnetic tunnel junction and an NMOS transistor. For the selected storage unit, the write operation method includes:

On the left side of Figure 1, when the write operation needs to energize from the source line to the bit line direction (P to AP, that is, write AP state), the source line voltage V _SL1 is set to the circuit's voltage through the write driver circuit (Write Driver). The operating voltage V _W1 =VDD sets the bit line voltage to a negative voltage -Δ , where the negative voltage -Δ is lower than the voltage VSS. Such a bias configuration brings two advantages to increase the write driving capability: 1) First, since V _BL1 is a negative bias, the voltage drop of V _GS on the access MOS transistor will be greatly improved; 2) In addition, this Under the voltage bias, the _VSB on the access MOS tube will also be greatly reduced (the body potential of the tube is grounded, and _VSB is a negative bias voltage at this time), and the body effect further increases the saturation current of the tube. Among them, the enhancement of the write drive current reduces the requirements for the gate voltage of the access transistor. Depending on the actual write circuit parasitic effects, when a reasonable negative bias voltage -Δ is selected, the voltage requirement for V _G can be reduced to VDD.

On the right side of FIG. 1 , when the write operation needs to energize from the bit line to the source line (AP to P, that is, write P state), the source line voltage V _SL2 is set to zero potential by the write drive circuit , the bit line voltage V _BL2 is set to V _W2 , since the drive current of the write drive circuit is larger than that of the write AP state, the value of V _W2 may be equal to or less than VDD.

Optionally, the body potential of the NMOS transistor of the selected memory cell is grounded.

Optionally, when the write operation to the selected memory cell needs to be energized from the source line to the bit line direction, for the memory cell in the same column but in a different row, there is a forward bias at the end of the NMOS transistor close to the bit line BL, The forward bias voltage is varied by the potential of the negative voltage.

Optionally, the forward bias voltage of the substrate-to-bit line of the memory cell needs to be lower than the forward conduction voltage of the PN junction formed by the substrate of the NMOS transistor and the active region. Because when the forward bias voltage value is the forward conduction voltage between the NMOS transistor substrate and the PN junction of the active region, a short circuit will occur, and the leakage will increase even when the voltage value is close. Therefore, the value of the negative bias voltage -Δ applied on the bit line cannot be too high, and is preferably around -0.3 to -0.6.

FIG. 2 is a schematic structural diagram of a magnetic memory chip according to an embodiment of the present application. A magnetic memory MRAM chip consists of one or more arrays (101) of MRAM memory cells (100). Each array is equipped with several external circuits. The row address decoder (102) and the column address decoder (103) respectively convert the received external address information into word line (WLi), bit line (BLj) and source line (SLj) selection information. The write drive and sense amplifier (104) respectively perform read or write operations on the selected memory cells under the control of an external read and write enable signal.

Optionally, the column decoder is composed of multiple multiplexing switches, which are implemented by CMOS transmission gates in this embodiment.

Optionally, the data bus of the MRAM chip provides writing or reading of m+1-bit data. For each data bit, according to the external input address, the column decoder will select to open one of the n multiplexers connected to the bit line BL in the array. Also in the direction of the source line SL, according to the external input address, the column decoder will select to open one of the n multiplexing switches that communicate with the source line SL in the array. Thereby, a certain storage unit in the storage array is selected. m+1 data bits, corresponding to m+1 selected storage units specified by the external address. These memory cells exist on the same word line, but on different bit lines/source lines. In addition, the chip is equipped with m+1 groups of write driver and sense amplifier modules with the same function, which are used to perform read and write operations on the selected m+1 memory cells.

FIG. 3 is a functional schematic diagram of a write driver and a sense amplifier according to an embodiment of the present application. In an embodiment of the present application, the write driver and sense amplifier include a write driver circuit and a sense amplifier; the write driver and sense amplifier obtain a read operation signal RD_EN of a logic high level, and a logic low level of the read operation signal RD_EN. When the write operation signal is WR_EN, a read operation is performed on the selected memory cell, and the switch m1 and the switch m2 between the write driver circuit and the bit line and the source line of the selected memory cell are disconnected, and the read operation is performed. The switch m3 and the switch m4 between the output amplifier and the bit line and source line of the selected memory cell are connected; the write drive and sense amplifier obtain the read operation signal RD_EN of a logic low level, and a logic high level When the write operation signal WR_EN is received, write operation is performed on the selected memory cell, and the switch m1 and the switch m2 between the write driver circuit and the bit line and source line of the selected memory cell are connected, and the read The switch m3 and the switch m4 between the output amplifier and the bit line and source line of the selected memory cell are disconnected.

Optionally, when the write operation to the selected memory cell needs to be energized from the bit line to the source line (P state, defined as write data "1" in this embodiment), the write drive circuit will The voltage of the source line SLi is set to VSS zero potential, and the voltage of the bit line BLi is set to the working voltage VDD. When the write operation to the selected memory cell needs to energize from the source line to the bit line direction (AP state, defined as write data "0" in this embodiment), the write drive circuit sets the voltage of the source line SLi For the operating voltage VDD, the voltage of the bit line BLi is set to a negative voltage -Δ.

In this application, the design scheme of improving the write driving capability by applying a negative bias voltage in the direction of the write channel bit line, while increasing the driving current, significantly reduces the requirements for the gate voltage VG on the access MOS transistor, and reduces the NMOS workload. stress. Extends the service life of the NMOS tube, that is, the MRAM chip. Secondly, the solution of the present invention sets the voltage of the source line SL to VDD when the write operation needs to be energized from the source line to the bit line, and the voltage of the bit line BL is biased in a small negative bias range of -0.3～ -0.6V (the body potential of the access MOS tube is always grounded), which reduces the workload stress on the MOS tube and increases its write drive current, while safely avoiding the above-mentioned problems caused by the excessive forward bias of the PN junction short circuit problem. Third, the present application provides a margin for the design selection of the size of the NMOS and PMOS devices on the write path while improving the write driving capability. That is to say, an NMOS transistor with a smaller area can be used in the MRAM array, or a smaller-sized MUX multiplexing switch can be selected in the column decoder on the write path. The manufacturing cost of the chip is reduced. Fourth, compared with the write operation method of increasing the bulk potential, the read and write operation method of the MRAM chip array layout of the present application can bring about a greater increase in driving current, especially in advanced process nodes where the material flipping voltage is slightly higher. under high conditions.

The terms "in one embodiment of the present application" and "in various embodiments" are used repeatedly. This term does not generally refer to the same embodiment; however, it can also refer to the same embodiment. The terms "comprising", "having" and "including" are synonymous unless the context of the text indicates otherwise.

The above are only specific embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed above with specific embodiments, it is not intended to limit the present application. , within the scope of the technical solution of the present application, when the technical content disclosed above can be used to make some changes or modifications to equivalent embodiments of equivalent changes, provided that any content that does not depart from the technical solution of the present application, according to the technical content of the present application Substantially any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solutions of the present application.

Claims (9)

1. A write operation method of a magnetic memory, the magnetic memory comprises a memory cell array composed of a plurality of memory cells, the memory cell array is connected with an external circuit through a word line, a source line and a bit line, each memory cell is composed of a magnetic tunnel junction and an NMOS tube, and the write operation method comprises the following steps for the selected memory cell:

when the writing operation needs to be electrified from the source line to the bit line direction, the source line voltage is set to be the working voltage of the circuit through the writing driving circuit, and the bit line voltage is set to be negative voltage;

when the writing operation needs to be powered on from the bit line to the source line direction, the source line voltage is set to be zero potential through the writing driving circuit, and the bit line voltage is set to be equal to or smaller than the working voltage.

2. The method of claim 1 wherein the body potential of the NMOS transistor of the selected memory cell is grounded.

3. The method of claim 1 wherein a forward bias voltage from the substrate to the bit line of the memory cell is less than a forward turn-on voltage of a PN junction formed between the substrate and the active region of the NMOS transistor.

4. The method of claim 1 wherein said negative voltage is between-0.3V and-0.6V.

5. The method of claim 1 wherein the memory cell array includes a row address decoder and a column address decoder that translate received external address information into selections of word lines, bit lines and source lines, respectively, to obtain the selected memory cells.

6. A method of writing to a magnetic memory as in claim 5 wherein the array of memory cells includes write driver and sense amplifiers, the read or write operations being performed on the selected memory cells under the control of external read and write enable signals.

7. The method of claim 6 wherein said write driver and sense amplifier comprises a write driver circuit and a sense amplifier; the write driving and sense amplifier obtains a high-level read operation signal, and when the low-level write operation signal is received, the read operation is carried out on the selected memory cell, the write driving circuit is disconnected with a bit line and a source line of the selected memory cell, and the sense amplifier is connected with the bit line and the source line of the selected memory cell; the write driving and sense amplifier obtains a low-level read operation signal, and performs write operation on the selected memory cell when the high-level write operation signal is received, the write driving circuit is connected with the bit line and the source line of the selected memory cell, and the sense amplifier is disconnected with the bit line and the source line of the selected memory cell.

8. The method of claim 7, wherein the write driver circuit sets the source line voltage to zero and the bit line voltage to the operating voltage when a write operation to the selected memory cell requires power to be applied from the bit line to the source line. When a write operation to a selected memory cell requires energization from the source line in the direction of the bit line, the write driver circuit sets the voltage of the source line to an operating voltage and sets the voltage of the bit line to a negative voltage.

9. The method of claim 5 further comprising the step of providing a data bus for writing or reading m +1 bits of data, m being a natural number greater than 1; the column decoder comprises a plurality of multi-path selection switches, wherein a proper pair of multi-path selection switches are switched on according to external address information and are respectively connected with bit lines and source lines of the same memory unit, and the same memory unit is the selected memory unit.

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