CN114639653A - Package and method for manufacturing the same - Google Patents
Package and method for manufacturing the same Download PDFInfo
- Publication number
- CN114639653A CN114639653A CN202011492956.XA CN202011492956A CN114639653A CN 114639653 A CN114639653 A CN 114639653A CN 202011492956 A CN202011492956 A CN 202011492956A CN 114639653 A CN114639653 A CN 114639653A
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- Prior art keywords
- chip
- package
- insulating layer
- resin
- carrier substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/411—Chip-supporting parts, e.g. die pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/04—Manufacture or treatment of leadframes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/421—Shapes or dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/019—Manufacture or treatment using temporary auxiliary substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W95/00—Packaging processes not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
A packaging body comprises a chip and a plurality of pins, wherein the chip and each pin are encapsulated in a plastic packaging layer and are electrically connected through a bonding wire, an insulating layer is arranged on one surface of the chip, and one surface of the insulating layer and one surface of each pin are exposed by the plastic packaging layer; and the material of the insulating layer is thermosetting resin.
Description
Technical Field
The present disclosure relates to semiconductor packages, and particularly to a package and a method for manufacturing the package.
Background
QFN packages are commonly used package structures. Fig. 1 shows a conventional QFN package structure. As shown in fig. 1. The conventional QFN package 1 includes: the die 4 is attached to a support pad (base island) 3 by an adhesive 2. The chip 4 is in turn supported on the support pad 3 for fixation during packaging, to facilitate the process of forming the bonding wires 5. Finally, the package body is obtained after the package body is packaged by the plastic package layer 6.
At present, aiming at the requirements of light weight, thinness, small size and the like of electronic products, further requirements are put forward on the size of a packaging body, and particularly, thinner requirements are put forward on the thickness aspect of the packaging body.
However, in the package 1 shown in fig. 1, due to the existence of the supporting pad 3, the thickness of the supporting pad itself increases the overall thickness of the package 1, and also raises the wire loop of the bonding wire 5, so that the thickness of the package 1 cannot be further reduced.
In addition, since the supporting pad 3 is used to support and fix the chip 4 during the packaging process of the package, the thickness of the package 1 shown in fig. 1 cannot be further reduced by the conventional package structure and packaging method.
Therefore, a new package is needed to overcome the above-mentioned drawbacks.
Disclosure of Invention
The present application provides a package and a method for manufacturing the package, in which a metal core pad (or called a "base island") of a chip in the package is removed to obtain an ultra-thin package.
In order to achieve the above object, according to an aspect of the present application, a package is provided, which includes a chip encapsulated in a molding layer and a plurality of leads, wherein the chip is electrically connected to each of the leads through a bonding wire; an insulating layer is arranged on one surface of the chip, and the plastic packaging layer exposes one surface of the insulating layer and one surface of each pin; wherein the insulating layer is made of thermosetting resin.
In some embodiments, the thermosetting resin is one or more of epoxy resin, unsaturated polyester resin, phenolic resin, melamine formaldehyde resin or furan resin.
In some embodiments, the insulating layer has a thickness of 15 μm to 50 μm.
In some embodiments, the plurality of leads are disposed around the chip, and at least one lead extends toward the chip toward an end of the chip to form a terminal; the terminals are encapsulated within the encapsulation layer.
According to another aspect of the present application, there is also provided a manufacturing method of a package, the manufacturing method including:
providing a bearing substrate;
forming a patterned metal layer on the bearing substrate to form a plurality of pins;
providing a wafer with a functional surface and a back surface opposite to the functional surface, forming an insulating layer on the back surface of the wafer, and cutting to form a plurality of chips provided with the insulating layers;
attaching the chip provided with the insulating layer to the bearing substrate;
forming a plurality of bonding wires so that the chip is electrically connected with each pin through one bonding wire; and the number of the first and second groups,
and forming a plastic package layer to encapsulate the chip, the bonding wires and the pins, and removing the bearing substrate to expose a surface of the insulating layer and a surface of each pin.
In some embodiments, after the step of removing the carrier substrate, the manufacturing method further comprises: and cutting to form a single packaging body.
In some embodiments, in the step of forming a patterned metal layer on the carrier substrate, the patterned metal layer is formed by electroplating.
In some embodiments, in the step of forming the patterned metal layer on the carrier substrate, the patterned metal layer is formed by two-step electroplating to form a plurality of pins, so that a projected area of a surface of at least one pin away from the carrier substrate on the carrier substrate is larger than a projected area of a surface of the pin contacting the carrier substrate on the carrier substrate.
In some embodiments, in the step of forming an insulating layer on the back surface of the wafer, the insulating layer is formed by coating a thermosetting resin on the back surface of the wafer and thermally curing; the thickness of the insulating layer is 15-50 μm.
In some embodiments, the thermosetting resin is one or more of epoxy resin, unsaturated polyester resin, phenolic resin, melamine formaldehyde resin or furan resin.
In the application, through setting the insulating layer and the thermosetting characteristic thereof, the chip is supported by the base island of the lead frame in the packaging process of the packaging body without the packaging step like a conventional packaging body, so that the base island in the finally obtained packaging body structure is eliminated, the thickness of the packaging body is greatly reduced, the radian of a bonding wire is reduced, and the ultrathin packaging body can be obtained. In addition, in the preparation method of the package body, the plurality of pins are formed in an electroplating mode, the thickness of the formed pins can be accurately controlled according to requirements, and the forming of the ultrathin package body is facilitated.
Drawings
In order to more clearly illustrate the features of particular embodiments of the present invention, reference will now be made in brief to the accompanying drawings of embodiments. It is to be understood that the drawings described below are merely exemplary of the invention and that other similar drawings may be obtained by those of ordinary skill in the art without the exercise of inventive faculty.
FIG. 1 is a schematic diagram of a conventional package product;
fig. 2 is a schematic structural diagram of a package according to an embodiment of the application;
fig. 3 is a flow chart of a method of fabricating a package according to an embodiment of the present application;
fig. 4A to 4E are schematic structural diagrams corresponding to fig. 3.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It is to be understood that the described embodiments are merely a few, but not all, applications of the invention. It should be understood that these examples are only for illustrating the characteristics of the present invention and are not intended to limit the scope of the present invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
As shown in fig. 2, in the present embodiment, a package 100 is provided, which includes: the chip package comprises a chip 110, a plurality of pins 120, and a molding layer 130 encapsulating the chip 110 and the plurality of pins 120.
Specifically, as shown in fig. 2, in the package 100, the plurality of leads 120 are disposed around the chip 110, and each of the leads 120 is electrically connected to the chip 110 through a bonding wire 140. As shown in fig. 2, in order to achieve the mode-locking effect, each pin 120 extends toward the chip 110 towards one end of the chip 110 to form a terminal 121, and the terminal 121 is also encapsulated in the encapsulation layer 130.
In this embodiment, the package 100 may be a QFN package. In order to obtain an ultra-thin package, as shown in fig. 1 and 2, the package body 100 of the present application eliminates a substrate for mounting the chip 110, and an insulating layer 150 is disposed on one surface 110a of the chip 110. The insulating layer 150 is arranged to satisfy: the molding compound layer 130 exposes a surface 150a of the insulating layer 150 and a surface 120a of each lead 120. That is, a surface 100a of the package body 100 exposes the surface 150a of the insulating layer 150 and the surface 120a of each lead 120. As shown in fig. 2, the lower surface of the package 100 (i.e., the mounting surface of the package) exposes the surface 150a of the insulating layer 150 and the surface 120a of each lead 120.
In consideration of the thickness of the package 100, the thickness of the insulating layer 150 is 15 μm to 50 μm.
The insulating layer is made of thermosetting resin, and can be one or a mixture of epoxy resin, unsaturated polyester resin, phenolic resin, melamine formaldehyde resin or furan resin. It will be appreciated by those skilled in the art that in the present application, the material of the insulating layer may be a material known in the art that is heat curable, particularly a double sided adhesive material that is heat curable, such as, but not limited to, LOCTITE ablestak 8006NS epoxy. When selecting the material of the insulating layer, the cured insulating layer may have characteristics similar to those of a conventional ABF carrier (Ajinomot Build-up Film).
Therefore, in the package 100 of the present application, by providing the insulating layer and the thermal curing property thereof, it is not required to support the chip 120 by using the base island of the lead frame in the packaging process of the package 100 like in the packaging step of the conventional package, so that the base island in the finally obtained package 100 structure is eliminated, the thickness of the package is greatly reduced, and the ultra-thin package is obtained.
Hereinafter, the method for manufacturing the package 100 will be described in detail with reference to fig. 3 and 4A to 4E.
As shown in fig. 3 and 4A, the method for manufacturing the package 100 includes step S1: a carrier substrate SP is provided, and a patterned metal layer M is formed on the carrier substrate SP to form a plurality of leads 120. It will be appreciated by a person skilled in the art that in this step the metal layer M may be patterned on the carrier plate SP by methods known in the art, such as electroplating, deposition, etc. The carrier substrate SP may be a conventional carrier substrate used in the art for package packaging. As an exemplary example and not limiting the application, in this step, a carbon steel plate is used as the carrier substrate SP. Meanwhile, considering that the metal frame (lead frame) of the ultra-thin QFN product is rather thin, it is difficult to make the molding by the conventional direct copper plate etching, and therefore, in this step, the patterned metal layer M is formed by copper plating on the carbon steel plate as the carrier substrate SP. In this step, the thickness of the copper plating is approximately < ═ 0.1 mm.
Further, in this step, in order to realize the formation of a terminal 121 at one end of each lead 120 as shown in fig. 1, the terminal 121 is formed by two-step copper plating in this step.
As shown in fig. 3 and 4B, the method for manufacturing the package 100 includes step S2: a chip 110 with an insulating layer 150 attached thereto is provided. It will be appreciated by those skilled in the art that the chip 110 enriched with the insulating layer 150 can be obtained by any method known in the art. As an exemplary example and not limiting to the present application, in the present step, a wafer W having a functional surface S and a back surface opposite to the functional surface S is first provided, an insulating layer 150 is formed on the back surface of the wafer W, and a plurality of chips 110 provided with the insulating layer 150 are formed after dicing.
As shown in fig. 3 and 4C, the method for manufacturing the package 100 includes step S3: the chip 110 provided with the insulating layer 150 is attached to the carrier substrate SP. It will be understood by those skilled in the art that the chip 110 provided with the insulating layer 150 may be attached to the carrier substrate SP by any method known in the art. For example, in this step, the chip 110 is attached to the carrier substrate SP by using a conventional die bonder.
As shown in fig. 3 and 4D, the method for manufacturing the package 100 includes step S4: a plurality of bonding wires 140 are formed such that the chip 110 and each of the leads 120 are electrically connected by a bonding wire 140. It will be appreciated by those skilled in the art that the plurality of bond wires 140 can be formed by any method known in the art.
As shown in fig. 3 and 4E, the method for manufacturing the package 100 includes step S4: a molding compound layer 130 is formed to encapsulate the chip 110, the bonding wires 140 and the leads 120, and the carrier substrate SP is removed, so that the molding compound layer 130 exposes a surface 150a of the insulating layer 150 and a surface 120a of each lead 120. After dicing in a conventional dicing step, a single package 100 as shown in fig. 2 can be obtained.
The present application has been described in relation to the above embodiments, which are only examples for implementing the present application. It must be noted that the disclosed embodiments do not limit the scope of the application. Rather, modifications and equivalent arrangements included within the spirit and scope of the claims are included within the scope of the present application.
Claims (10)
1. A packaging body comprises a chip and a plurality of pins, wherein the chip and each pin are encapsulated in a plastic packaging layer and are electrically connected through a bonding wire; wherein the insulating layer is made of thermosetting resin.
2. The package of claim 1, wherein the thermosetting resin is one or more of epoxy resin, unsaturated polyester resin, phenolic resin, melamine formaldehyde resin or furan resin.
3. The package of claim 1, wherein the insulating layer has a thickness of 15 μ ι η to 50 μ ι η.
4. The package of claim 1, wherein the plurality of leads are disposed around the chip, and wherein at least one lead extends toward the chip toward an end of the chip to form a terminal; the terminals are encapsulated within the encapsulation layer.
5. A method of manufacturing a package, the method comprising:
providing a bearing substrate;
forming a patterned metal layer on the bearing substrate to form a plurality of pins;
providing a wafer with a functional surface and a back surface opposite to the functional surface, forming an insulating layer on the back surface of the wafer, and cutting to form a plurality of chips provided with the insulating layers;
attaching the chip provided with the insulating layer to the bearing substrate;
forming a plurality of bonding wires so that the chip is electrically connected with each pin through one bonding wire; and the number of the first and second groups,
and forming a plastic packaging layer to encapsulate the chip, the bonding wires and the pins, and removing the bearing substrate to expose a surface of the insulating layer and a surface of each pin.
6. The manufacturing method of claim 5, wherein after the step of removing the carrier substrate, the manufacturing method further comprises: and cutting to form a single packaging body.
7. The manufacturing method according to claim 5, wherein in the step of forming a patterned metal layer on the carrier substrate, the patterned metal layer is formed by electroplating.
8. The method according to claim 5, wherein in the step of forming the patterned metal layer on the carrier substrate, the patterned metal layer is formed by two-step electroplating to form a plurality of leads, such that a projected area of a surface of at least one lead away from the carrier substrate on the carrier substrate is larger than a projected area of a surface of the lead contacting the carrier substrate on the carrier substrate.
9. The manufacturing method according to claim 5, wherein in the step of forming an insulating layer on the back surface of the wafer, the insulating layer is formed by applying a thermosetting resin to the back surface of the wafer and thermally curing; the thickness of the insulating layer is 15-50 μm.
10. The method according to claim 9, wherein the thermosetting resin is one or more of epoxy resin, unsaturated polyester resin, phenolic resin, melamine formaldehyde resin and furan resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011492956.XA CN114639653A (en) | 2020-12-16 | 2020-12-16 | Package and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011492956.XA CN114639653A (en) | 2020-12-16 | 2020-12-16 | Package and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114639653A true CN114639653A (en) | 2022-06-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011492956.XA Pending CN114639653A (en) | 2020-12-16 | 2020-12-16 | Package and method for manufacturing the same |
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| CN (1) | CN114639653A (en) |
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| CN108198804A (en) * | 2017-12-29 | 2018-06-22 | 江苏长电科技股份有限公司 | There is stack package structure and its manufacturing process that pin side wall climbs tin |
| CN108198761A (en) * | 2017-12-29 | 2018-06-22 | 江苏长电科技股份有限公司 | There is semiconductor package and its manufacturing process that pin side wall climbs tin |
| CN108206170A (en) * | 2017-12-29 | 2018-06-26 | 江苏长电科技股份有限公司 | There is semiconductor package and its manufacturing process that pin side wall climbs tin |
| CN111785696A (en) * | 2020-08-04 | 2020-10-16 | 苏州日月新半导体有限公司 | Integrated circuit package and method of making the same |
| CN214043650U (en) * | 2020-12-16 | 2021-08-24 | 上海凯虹科技电子有限公司 | Package body |
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2020
- 2020-12-16 CN CN202011492956.XA patent/CN114639653A/en active Pending
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| US20020057553A1 (en) * | 2000-11-10 | 2002-05-16 | Fairchild Korea Semiconductor Ltd. | Stacked intelligent power module package |
| DE10134979A1 (en) * | 2001-07-24 | 2002-10-17 | Infineon Technologies Ag | Integrated semiconductor chip having an active front side with semiconductor structures and contact connections and a passive/active rear side with/without semiconductor structures |
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| US20120208324A1 (en) * | 2011-02-14 | 2012-08-16 | Renesas Electronics Corporation | Manufacturing method of semiconductor device |
| CN108198790A (en) * | 2017-12-29 | 2018-06-22 | 江苏长电科技股份有限公司 | There is stack package structure and its manufacturing process that pin side wall climbs tin |
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| CN108198804A (en) * | 2017-12-29 | 2018-06-22 | 江苏长电科技股份有限公司 | There is stack package structure and its manufacturing process that pin side wall climbs tin |
| CN108198761A (en) * | 2017-12-29 | 2018-06-22 | 江苏长电科技股份有限公司 | There is semiconductor package and its manufacturing process that pin side wall climbs tin |
| CN108206170A (en) * | 2017-12-29 | 2018-06-26 | 江苏长电科技股份有限公司 | There is semiconductor package and its manufacturing process that pin side wall climbs tin |
| CN111785696A (en) * | 2020-08-04 | 2020-10-16 | 苏州日月新半导体有限公司 | Integrated circuit package and method of making the same |
| CN214043650U (en) * | 2020-12-16 | 2021-08-24 | 上海凯虹科技电子有限公司 | Package body |
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