CN114626330A - Simulation method and device for digital-analog hybrid circuit - Google Patents

Abstract

The embodiments of the present application provide a method and device for simulating a digital-analog hybrid circuit, obtaining circuit information of a black-box circuit including a black-box analog circuit and a black-box digital circuit, determining simulation configuration information for the black-box circuit, and simulating the black-box circuit The circuit is replaced by the analog circuit to be tested, and the black box digital circuit is replaced by the digital circuit to be tested, and the simulation configuration information is used to simulate the circuit to be tested including the analog circuit to be tested and the digital circuit to be tested, wherein the analog circuit to be tested has the same characteristics as the analog circuit to be tested. The black box analog circuit has the same input pin information and output pin information, and the digital circuit to be tested has the same input interface information and output interface information as the black box digital circuit. That is to say, in the embodiment of the present application, the construction of the simulation system can be set in the design stage of the analog circuit to be tested and the digital circuit to be tested, which reduces the time period before the design completion node of the circuit and the simulation operation node of the circuit, shortening the Chip development cycle.

Description

A digital-analog hybrid circuit simulation method and device

technical field

The present application relates to the field of integrated circuits, and in particular, to a method and device for simulating a digital-analog hybrid circuit.

Background technique

In the field of chip design, with the increasing integration of chips and the diversification of market demands, the design of integrating digital circuits and analog circuits in one chip has gradually occupied more positions in the chip market. This situation brings greater difficulties to chip verification and simulation. Although the mainstream electronic design automation (EDA) tools and domestic EDA tools on the market all have the function of providing digital-analog hybrid circuit simulation, but These functions are carried out on the basis of completing the digital circuit and the analog circuit, so that the initial stage of simulation verification needs to be carried out after the design stage of the digital circuit and the analog circuit are all completed, thus greatly prolonging the development cycle of the chip.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, the embodiments of the present application provide a digital-analog hybrid circuit simulation method and device, which can realize the establishment of a simulation system in the design stage of digital circuits and analog circuits, save simulation time, and shorten the development cycle of chips.

The embodiment of the present application provides a digital-analog hybrid circuit simulation method, including:

Obtain circuit information of a black-box circuit including a black-box analog circuit and a black-box digital circuit; the circuit information of the black-box circuit includes input pin information and output pin information of the black-box analog circuit, and the black-box analog circuit The circuit includes a test resistor connected in series between the input pin and the output pin; the circuit information also includes input interface information and output interface information of the black-box digital circuit;

determining simulation configuration information for the black box circuit;

Replace the black-box analog circuit with an analog circuit to be tested, replace the black-box digital circuit with a digital circuit to be tested, and update the data based on the storage location of the analog circuit to be tested and the storage location of the black-box digital circuit. The simulation configuration information; the analog circuit under test has the same input pin information and output pin information as the black box analog circuit, and the digital circuit under test has the same input interface information as the black box digital circuit and output interface information;

Using the updated simulation configuration information, the circuit under test including the analog circuit under test and the digital circuit under test is simulated.

Optionally, replacing the black-box analog circuit with an analog circuit to be tested, and replacing the black-box digital circuit with a digital circuit to be tested, is based on the storage location of the analog circuit to be tested and the black-box digital circuit. The storage location of the circuit updates the simulation configuration information, including:

Replace the verilog netlist of the black-box digital circuit with the verilog netlist of the digital circuit to be tested at the storage location of the verilog netlist of the black-box digital circuit;

Replace the netlist of the black-box analog circuit with the netlist of the analog circuit to be tested at the storage location of the netlist of the black-box analog circuit;

Update the storage location of the verilog netlist of the black-box digital circuit in the simulation configuration information to the storage location of the netlist of the black-box analog circuit, and update the verilog netlist of the digital circuit to be tested in the simulation configuration information The storage location of is replaced with the storage location of the netlist of the analog circuit under test.

Optionally, the simulation configuration information determined for the black-box circuit and the updated simulation configuration information also include: the storage location of the top-level netlist of the simulation system, the storage location of the verilog code of the outsourced test item layer of the black-box digital circuit. Storage location and the storage location of the netlist of the excitation circuit, the excitation circuit is used to provide an excitation signal; the storage location of the verilog code of the outsourced test item layer of the black box digital circuit and the outsourced test item layer of the digital circuit to be tested The verilog code is stored in the same location.

Optionally, the method further includes:

According to the simulation configuration information and the storage location of the verilog netlist of the digital circuit to be tested, and the netlist of the analog circuit to be tested, a simulation configuration script is obtained;

Then, using the simulation configuration information to simulate the circuit to be tested including the analog circuit to be tested and the digital circuit to be tested includes:

The simulation configuration script is run to invoke the simulation EDA tool to perform a simulation operation on the circuit under test including the analog circuit under test and the digital circuit under test.

Optionally, the acquiring the input interface information and the output interface information of the black box digital circuit includes: acquiring the declaration information of the input interface and the output interface of the black box digital circuit based on the verilog grammar; The verilog netlist of the black box digital circuit;

The acquiring the input pin information and output pin information of the black-box analog circuit includes: acquiring circuit information of the black-box analog circuit, and generating a netlist of the black-box analog circuit according to the circuit information.

The embodiment of the present application provides a digital-analog hybrid circuit simulation device, including:

A circuit information acquisition unit for acquiring circuit information of a black-box circuit including a black-box analog circuit and a black-box digital circuit; the circuit information of the black-box circuit includes input pin information and output pin information of the black-box analog circuit information, the black box analog circuit includes a test resistor connected in series between the input pin and the output pin; the circuit information also includes input interface information and output interface information of the black box digital circuit;

a configuration information determining unit, configured to determine simulation configuration information for the black box circuit;

A circuit replacement unit for replacing the black-box analog circuit with an analog circuit to be tested, and replacing the black-box digital circuit with a digital circuit to be tested, based on the storage location of the analog circuit to be tested and the black-box digital circuit The storage location of the circuit updates the simulation configuration information; the analog circuit under test has the same input pin information and output pin information as the black box analog circuit, and the digital circuit under test has the same input pin information and output pin information as the black box analog circuit. The same input interface information and output interface information of the circuit;

The simulation unit is used for simulating the circuit under test including the analog circuit under test and the digital circuit under test by using the updated simulation configuration information.

Optionally, the circuit replacement unit includes:

The first circuit replacement subunit is used to replace the verilog netlist of the black-box digital circuit with the verilog netlist of the digital circuit to be tested at the storage location of the verilog netlist of the black-box digital circuit;

a second circuit replacement subunit, configured to replace the netlist of the black-box analog circuit with the netlist of the analog circuit to be tested at the storage location of the netlist of the black-box analog circuit;

The configuration information replacement subunit is used to update the storage location of the verilog netlist of the black-box digital circuit in the simulation configuration information to the storage location of the netlist of the black-box analog circuit, and replace the The storage location of the verilog netlist of the digital circuit to be tested is replaced with the storage location of the netlist of the analog circuit to be tested.

Optionally, the simulation configuration information determined for the black-box circuit and the updated simulation configuration information also include: the storage location of the top-level netlist of the simulation system, the storage location of the verilog code of the outsourced test item layer of the black-box digital circuit. Storage location and the storage location of the netlist of the excitation circuit, the excitation circuit is used to provide an excitation signal; the storage location of the verilog code of the outsourced test item layer of the black box digital circuit and the outsourced test item layer of the digital circuit to be tested The verilog code is stored in the same location.

Optionally, the device further includes:

a script determination unit, configured to obtain a simulation configuration script according to the simulation configuration information and the storage location of the verilog netlist of the digital circuit to be tested, and the netlist of the analog circuit to be tested;

Then, the simulation unit is specifically used for:

The simulation configuration script is run to invoke the simulation EDA tool to perform a simulation operation on the circuit under test including the analog circuit under test and the digital circuit under test.

Optionally, the circuit information acquisition unit includes:

The digital circuit acquisition subunit is used to acquire the declaration information of the input interface and the output interface of the black-box digital circuit based on the verilog syntax; the verilog netlist of the black-box digital circuit is generated according to the declaration information;

The analog circuit acquisition subunit is configured to acquire circuit information of the black-box analog circuit, and generate a netlist of the black-box analog circuit according to the circuit information.

Embodiments of the present application provide a method and device for simulating a digital-analog hybrid circuit, for obtaining circuit information of a black-box circuit including a black-box analog circuit and a black-box digital circuit, and the circuit information of the black-box circuit includes an input tube of the black-box analog circuit pin information and output pin information, the black box analog circuit includes the test resistor connected in series between the input pin and the output pin, and the circuit information also includes the input interface information and output interface information of the black box digital circuit, to determine the simulation for the black box circuit Configuration information, after replacing the black-box analog circuit with the analog circuit to be tested, and replacing the black-box digital circuit with the digital circuit to be tested, update the simulation configuration information based on the storage location of the analog circuit to be tested and the storage location of the black-box digital circuit, The circuit to be tested including the analog circuit to be tested and the digital circuit to be tested can be simulated using the updated simulation configuration information, wherein the analog circuit to be tested has the same input pin information and output pin information as the black box analog circuit. The test digital circuit has the same input interface information and output interface information as the black box digital circuit. That is to say, in the embodiment of the present application, a black-box analog circuit can be established in advance according to the input pin information and output pin information of the analog circuit to be tested, and a black-box digital circuit can be established according to the input interface information and output interface information of the digital circuit to be tested. circuit, and determine the simulation configuration information for the black box circuit, so that the construction of the simulation system is set in the design stage of the analog circuit to be tested and the digital circuit to be tested. The built test system performs simulation operation, which reduces the time before the design completion node of the analog circuit to be tested and the digital circuit to be tested and the simulation operation node of the analog circuit to be tested and the digital circuit to be tested, and shortens the development cycle of the chip.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some implementations described in the present application. For example, for those skilled in the art, other drawings can also be obtained from these drawings.

1 is a flowchart of a method for simulating a digital-analog hybrid circuit provided by an embodiment of the present application;

2 is a schematic diagram of an interface declaration of a black-box digital circuit provided by an embodiment of the present application;

3 is a schematic diagram of a black box analog circuit provided by an embodiment of the present application;

4 is a schematic diagram of a simulation system provided by an embodiment of the present application;

5 is a schematic structural diagram of a simulation environment provided by an embodiment of the present application;

FIG. 6 is a structural block diagram of a digital-analog hybrid circuit simulation apparatus provided by an embodiment of the present application.

Detailed ways

In order to make those skilled in the art better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only It is a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

At present, the digital-analog hybrid circuit simulation process is to use the graphical interface of the corresponding EDA tool to read in the analog circuit schematic diagram and the digital circuit design file, then create the test environment and set the excitation, and finally run the simulation and view the simulation results. Although the EDA tool provides a way of simulating the digital-analog hybrid circuit, since the digital circuit and the analog circuit are required to be complete designs from the start of reading the design using the EDA tool, it limits the need for the simulation verification at the beginning stage. The digital circuit and analog circuit design stages are all completed, and the simulation engineer can only start after the digital circuit and analog circuit design are all completed, which will increase the development cycle of the chip.

Based on the above technical problems, embodiments of the present application provide a digital-analog hybrid circuit simulation method and device, which acquire circuit information of a black-box circuit including a black-box analog circuit and a black-box digital circuit, and the circuit information of the black-box circuit includes a black-box circuit. The input pin information and output pin information of the analog circuit, the black box analog circuit includes the test resistor connected in series between the input pin and the output pin, and the circuit information also includes the input interface information and output interface information of the black box digital circuit, which is The black-box circuit determines the simulation configuration information. After replacing the black-box analog circuit with the analog circuit to be tested, and replacing the black-box digital circuit with the digital circuit to be tested, based on the storage location of the analog circuit to be tested and the storage location of the black-box digital circuit Update the simulation configuration information, you can use the updated simulation configuration information to simulate the circuit to be tested including the analog circuit to be tested and the digital circuit to be tested, wherein the analog circuit to be tested has the same input pin information and output as the black box analog circuit Pin information, the digital circuit to be tested has the same input interface information and output interface information as the black box digital circuit. That is to say, in the embodiment of the present application, a black-box analog circuit can be established in advance according to the input pin information and output pin information of the analog circuit to be tested, and a black-box digital circuit can be established according to the input interface information and output interface information of the digital circuit to be tested. circuit, and determine the simulation configuration information for the black box circuit, so that the construction of the simulation system is set in the design stage of the analog circuit to be tested and the digital circuit to be tested. The built test system performs simulation operation, which reduces the time before the design completion node of the analog circuit to be tested and the digital circuit to be tested and the simulation operation node of the analog circuit to be tested and the digital circuit to be tested, and shortens the development cycle of the chip.

The specific implementation of the digital-analog hybrid circuit simulation method and device in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 1, which is a flowchart of a method for simulating a digital-analog hybrid circuit provided in an embodiment of the present application, the method may include the following steps:

S101. Acquire circuit information of a black-box circuit including a black-box analog circuit and a black-box digital circuit.

In the embodiment of the present application, a black-box analog circuit and a black-box digital circuit can be constructed first, the black-box analog circuit is an analog circuit that only includes pin information, and other information is unknown, and the black-box digital circuit is a digital circuit that only includes interface information, Other information is unknown. After constructing the black-box analog circuit and the black-box digital circuit, the circuit information including the black-box analog circuit and the black-box digital circuit can be obtained, and then a simulation system platform can be built based on the black-box circuit including the black-box analog circuit and the black-box digital circuit. . The circuit information of the black box circuit includes input pin information and output pin information of the black box analog circuit, and input interface information and output interface information of the black box digital circuit.

Specifically, the black-box digital circuit is generated according to the digital circuit to be tested. The black-box digital circuit has the same input interface information and output interface information as the digital circuit to be tested. Since the input interface information and output interface information of the digital circuit to be tested are in The design phase of the digital circuit under test is determined before the end of the design phase, so the generation of the black-box digital circuit can be performed in parallel with the design of the digital circuit under test.

The input interface information of the black box digital circuit is used to indicate the function of each input interface of the black box digital circuit, and the output interface information of the black box digital circuit is used to indicate the function of each output interface of the black box digital circuit. For example, the first input interface is used to input reset signal (RESET), the second input interface is used to input (PD), etc.; for example, the first output interface is used to output PDB signal, and the second output interface is used to output PDB signal. Output PDBB signal, etc.

Since the front end of the digital circuit to be tested is designed using the hardware description language verilog, the EDA tool is used to create a black-box digital circuit, and a verilog type view can be created in the EDA tool, and the verilog syntax can be used in the open editable window. The interface information of the black-box digital circuit is declared. The interface information includes the input interface information and the output interface information. Since different interfaces are distinguished by the declaration order, the declaration order of the interface information of the black-box digital circuit and the interface information of the digital circuit under test are different. The declaration sequence is consistent, so as to ensure that the interface information of the black box digital circuit and the interface information of the digital circuit under test are the same.

Referring to FIG. 2 , a schematic diagram of an interface declaration of a black-box digital circuit provided by an embodiment of the present application, wherein the input interface is represented by input, and the input signals of each input interface are in sequence: RESET, PD, FIN, [8:0 ]M, [4:0]N, [1:0]OD, OE, BP, SOUT, [1:0]TST, the output signals of each output interface are: PDB, PDBB, DN, DNB, UP, UPB , FOUT, TST_OUT.

In the embodiment of the present application, after obtaining the declaration information of the input interface and the output interface of the black-box digital circuit based on the verilog syntax, the EDA tool can generate the corresponding circuit symbols (symbols) of the interface elements of each black-box digital circuit according to the declaration information In this way, the creation of the black-box digital circuit is completed, and the acquisition of the input interface information and output interface information of the black-box digital circuit is completed. In this embodiment of the present application, a verilog netlist (netlist) of the black-box digital circuit may also be generated according to the declaration information.

Specifically, the black-box analog circuit is generated according to the analog circuit to be tested, and the black-box analog circuit has the same input pin information and output pin information as the analog circuit to be tested. Pin information is determined before the end of the design phase of the analog circuit under test, so the generation of the black box analog circuit can be performed in parallel with the design of the analog circuit under test.

For black-box analog circuits, you can create a schematic diagram that only includes the pins of the analog circuit to be tested, including input pins and output pins, and connect all pins reasonably, such as input pins A test resistor is connected in series between the pin and the output pin. The number of test resistors can be determined according to the number of input pins and output pins. Each input pin is connected to at least one test resistor, and different input pins can be connected to the same test resistor. , you can also connect different test resistors, each output pin is connected to at least one test resistor, and different output pins can be connected to the same test resistor or different test resistors. Test resistors for input pins and output pins in series can prevent input pins and output pins from being optimized and removed by EDA tools during subsequent netlist generation.

Referring to FIG. 3 , which is a schematic diagram of a black box analog circuit provided by an embodiment of the present application, the input pins include M<8:3>, IN1, IN2, DN, DNB, UP, and UPB, and the output pins include M<8:3>, IN1, IN2, DN, DNB, UP, and UPB. Including SOUT, where input pins M<8>, M<7>, M<6>, M<5>, M<4>, M<3>, IN1, IN2, DN, DNB, UP, and UPB pass through The test resistors R6, R7, R8, R9, R10, R11, R0, R1, R2, R3, R4, R5 are connected to the output pin SOUT.

In the embodiment of the present application, acquiring the input pin information and output pin information of the black box analog circuit may specifically be: acquiring the black box analog circuit information, and generating circuit symbols of the pin components of each black box analog circuit according to the analog circuit information (symbol) The corresponding view (view). Specifically, the netlist of the black-box analog circuit can also be generated according to the circuit information.

S102, determine simulation configuration information for the black box circuit.

In the embodiment of the present application, after the black box circuit is determined and the circuit information of the black box circuit is obtained, a simulation system can be built based on the black box circuit. Referring to FIG. 4 , a simulation system provided by the embodiment of the present application is shown. The schematic diagram of the simulation system can include an excitation circuit (Driver) and a monitoring circuit (Monitor). The simulation system is used to simulate a test circuit including a digital circuit (Digital) and an analog circuit (Analog), wherein the excitation circuit is used to provide excitation signals. , the monitoring circuit is used to monitor the signal of the test circuit according to the needs of simulation verification.

Specifically, after obtaining the circuit information of the black box circuit, the information of the excitation circuit can also be set. When using the simulation EDA tool to simulate the black box circuit, the excitation circuit is used to provide excitation signals for the black box circuit. The simulation operation of the box circuit is to simulate the response signal generated by the black box circuit under the action of the excitation signal. Through the analysis of the response signal, the simulation operation result of the black box circuit can be obtained. The simulation operation result of the black box circuit reflects the black box circuit. performance parameters.

The information of the excitation circuit may include circuit elements in the excitation circuit and the connection relationship between the excitation circuit and the black-box circuit. The information of the excitation circuit is determined according to the detection requirements of the circuit to be tested, for example, according to the simulation type, simulation analysis point, etc. Using the excitation circuit and the black-box circuit, the circuit schematic of the simulated circuit is obtained. The information of the monitoring circuit can include the circuit elements in the monitoring circuit, and the connection relationship between the monitoring circuit and the black-box circuit. The information of the monitoring circuit is determined according to the detection requirements of the circuit to be tested, for example, according to the simulation type, simulation detection point, etc. The circuit schematic can also include monitoring circuits.

After establishing the circuit schematic diagram of the simulation circuit, you can build a digital-analog hybrid simulation environment. Specifically, you can create a view (view) of the configuration information (config) type, and select the hybrid simulation type of the simulation schematic diagram as needed. After correct setting , the simulation system schematic diagram is designed.

Specifically, after obtaining the circuit information of the black box circuit, configuration information of the simulation operation can also be set, so that the simulation EDA tool can perform circuit simulation according to the configuration information. Configuration information may include, for example, model files that may be required for simulation, scripts used in the simulation process, where the simulation is run and where the simulation results are generated, information on black-box digital circuits used in the simulation and information on black-box analog circuits, user-defined The storage location of files such as configuration files, so that the simulation EDA tool can call the required files according to the configuration information to simulate the black box circuit.

Referring to FIG. 5, a schematic diagram of the structure of a simulation environment provided by an embodiment of the present application, the simulation environment structure includes a database (Database), and the database includes a model (Models) folder, a script (Script) folder, a simulation (Simulation) ) folder, circuit information (Src) folder, custom model (User_define Models) folder, etc., where the model folder is used to store all model files required for simulation, and the script folder is used to store all scripts used in the simulation process , the simulation folder is the location where the simulation runs and the simulation results are generated, the circuit information folder is used to store the information of the black-box digital circuit and the information of the black-box analog circuit used in the simulation, and the custom model folder is used to store the information in the simulation process. A user-defined configuration file is required. The information of the black-box digital circuit includes an RTL code file or an RTL netlist of the black-box digital circuit, and the information of the black-box analog circuit includes a simulation netlist file of the black-box analog circuit.

During specific implementation, you can open the simulation tool window corresponding to the schematic diagram of the simulation system, set the simulation model, simulation analysis points, and simulation monitoring points as required, then select the simulator type, set the digital-analog hybrid simulation type, and digital-analog conversion parameters and other information. After the simulation options are set, run the simulation, and the simulation tool will generate the simulation netlist and simulation settings of the entire simulation system circuit. The corresponding digital circuit under test in the netlist and file is the aforementioned black box digital circuit. The circuit is the aforementioned black box analog circuit.

After completing the construction of the simulation system, the simulation configuration information can be obtained. The simulation configuration information can include the storage location of the verilog netlist of the black box digital circuit, the storage location of the netlist of the black box analog circuit, and the storage location of the top-level netlist of the simulation system. The location, the storage location of the verilog netlist of the outsourced test item layer of the black box digital circuit and the storage location of the netlist of the excitation circuit. The simulation configuration information may further include the storage location of the simulation model file, simulation analysis points, simulation monitoring points, simulator type, digital-analog hybrid simulation type, digital-analog conversion parameters, and the like.

S103, replace the black box analog circuit with the analog circuit to be tested, replace the black box digital circuit with the digital circuit to be tested, and update the simulation configuration information based on the storage location of the analog circuit to be tested and the storage location of the black box digital circuit.

In the embodiment of the present application, the construction of the digital-analog hybrid circuit simulation system platform can be carried out after the black box circuit is established, so that the construction time of the digital-analog hybrid circuit simulation system platform is advanced to the stage of digital circuit and analog circuit design, or even in advance To the initial stage of digital circuit and analog circuit design, circuit design and simulation platform construction can be carried out simultaneously, which solves the problem that the construction of the digital-analog hybrid circuit simulation system platform is overly dependent on the circuit design speed, effectively reduces the development cycle of the chip, reduces the Development costs.

After the digital circuit to be tested and the analog circuit to be tested are designed, the analog black-box analog circuit to be tested can be replaced with the analog circuit to be tested, the black-box digital circuit can be replaced with the digital circuit to be tested, and the input pins of the analog circuit to be tested can be replaced The information and output pin information are respectively the same as the input pin information and output pin information of the black box analog circuit, and the input interface information and output interface information of the digital circuit to be tested are respectively the same as the input interface information and output information of the black box digital circuit. The interface information is the same, so that even if the black box circuit is replaced by the circuit under test, the connection between the black box circuit and the excitation circuit, and the connection between the circuit under test and the excitation circuit will not change, so the required simulation configuration The information has not been changed, and the digital-analog hybrid circuit simulation system platform built in the early stage can be used for the simulation of the circuit to be tested.

Specifically, replacing the black-box analog circuit with the analog circuit to be tested can be specifically: replacing the netlist of the black-box analog circuit with the netlist of the analog circuit to be tested at the storage location of the black-box analog circuit; replacing the black-box digital circuit with the netlist of the analog circuit to be tested Replacing with the digital circuit to be tested may specifically include replacing the verilog netlist of the black-box digital circuit with the verilog netlist of the digital circuit to be tested in the storage location of the verilog netlist of the black-box digital circuit. Of course, the storage location of the verilog netlist of the black-box digital circuit in the simulation configuration information is also updated to the storage location of the verilog netlist of the digital circuit to be tested, and the storage location of the netlist of the black-box analog circuit is also updated to the storage location of the netlist to be tested. The storage location for the netlist of the analog circuit.

S104, use the simulation configuration information to simulate the circuit to be tested including the analog circuit to be tested and the digital circuit to be tested.

After replacing the black-box digital circuit with the digital circuit to be tested and the black-box analog circuit with the analog circuit to be tested, the connection between the black-box circuit and the excitation circuit will not be the same as the connection between the circuit under test and the excitation circuit. Therefore, the required simulation configuration information has not changed, and the digital-analog hybrid circuit simulation system platform built in the early stage can be used for the simulation of the circuit to be tested.

In the embodiment of the present application, the updated simulation configuration information can be used to simulate the circuit to be tested including the analog circuit to be tested and the digital circuit to be tested to obtain a simulation result of the circuit to be tested, and the simulation result of the circuit to be tested is The performance parameters of the circuit under test can be optimized, so that the circuit under test can be optimized according to the simulation results of the circuit under test. The updated simulation configuration information also includes the storage location of the top-level netlist of the simulation system, the storage location of the verilog code of the outsourced test item layer of the digital circuit to be tested, and the storage location of the netlist of the excitation circuit, which is used to provide excitation signals. The storage location of the verilog code of the outsourced test item layer of the black-box digital circuit in the simulation configuration information is unmodified, and the storage location of the verilog code of the outsourced test item layer of the digital circuit to be tested is the same.

Since the construction time of the digital-analog hybrid circuit simulation system platform is advanced to the stage of digital circuit and analog circuit design, it can even be advanced to the initial stage of digital circuit and analog circuit design. The construction of the modular hybrid circuit simulation system platform is overly dependent on the circuit design speed, which effectively reduces the development cycle of the chip and reduces the development cost.

In this embodiment of the present application, a simulation configuration script may also be obtained according to the simulation configuration information, the storage location of the verilog netlist of the digital circuit to be tested, and the storage location of the netlist of the analog circuit to be tested, and the simulation configuration script may include the first configuration information, the first configuration information includes the storage position of the verilog netlist of the digital circuit to be tested, and the storage position of the netlist of the analog circuit to be tested. The simulation of the circuit under test may specifically be: running a simulation configuration script to perform a simulation operation on the circuit under test including the analog circuit under test and the digital circuit under test by using a simulation EDA tool. The first configuration information may further include the storage location of the top-level netlist of the simulation system, the storage location of the verilog code of the outsourced test item layer of the digital circuit to be tested, and the storage location of the netlist of the excitation circuit.

In the embodiment of the present application, a simulation configuration script can also be obtained according to the simulation configuration information, the storage location of the verilog code file of the digital circuit to be tested, and the storage location of the netlist of the analog circuit to be tested, and the simulation configuration script can include the second configuration information, the second configuration information includes the storage location of the verilog code file of the digital circuit to be tested, and the storage location of the netlist of the analog circuit to be The simulation of the circuit under test may specifically be: running a simulation configuration script to perform a simulation operation on the circuit under test including the analog circuit under test and the digital circuit under test by using a simulation EDA tool. The verilog code file of the digital circuit to be tested is designed by the design engineer, so there is no need for the simulation engineer to enter the information of the relevant circuit units, reducing the possibility of errors. The second configuration information may further include the storage location of the top-level netlist of the simulation system, the storage location of the verilog code of the outsourced test item layer of the digital circuit to be tested, and the storage location of the netlist of the excitation circuit.

An embodiment of the present application provides a digital-analog hybrid circuit simulation method, which acquires circuit information of a black-box circuit including a black-box analog circuit and a black-box digital circuit, and the circuit information of the black-box circuit includes input pin information of the black-box analog circuit and output pin information, the black box analog circuit includes the test resistor connected in series between the input pin and the output pin, the circuit information also includes the input interface information and output interface information of the black box digital circuit, and determines the simulation configuration information for the black box circuit , after replacing the black-box analog circuit with the analog circuit to be tested, and replacing the black-box digital circuit with the digital circuit to be tested, update the simulation configuration information based on the storage location of the analog circuit to be tested and the storage location of the black-box digital circuit, you can use The updated simulation configuration information simulates the circuit to be tested including the analog circuit to be tested and the digital circuit to be tested, wherein the analog circuit to be tested has the same input pin information and output pin information as the black box analog circuit, and the digital circuit to be tested has the same input pin information and output pin information as the black box analog circuit. The circuit has the same input interface information and output interface information as the black box digital circuit. That is to say, in the embodiment of the present application, a black-box analog circuit can be established in advance according to the input pin information and output pin information of the analog circuit to be tested, and a black-box digital circuit can be established according to the input interface information and output interface information of the digital circuit to be tested. circuit, and determine the simulation configuration information for the black box circuit, so that the construction of the simulation system is set in the design stage of the analog circuit to be tested and the digital circuit to be tested. The built test system performs simulation operation, which reduces the time before the design completion node of the analog circuit to be tested and the digital circuit to be tested and the simulation operation node of the analog circuit to be tested and the digital circuit to be tested, and shortens the development cycle of the chip.

Based on the above digital-analog hybrid circuit simulation method, an embodiment of the present application further provides a digital-analog hybrid circuit simulation device. Referring to FIG. 6, a structural block diagram of a digital-analog hybrid circuit simulation device provided by an embodiment of the present application is shown, The apparatus may include:

The circuit information acquisition unit 110 is configured to acquire circuit information of a black-box circuit including a black-box analog circuit and a black-box digital circuit; the circuit information of the black-box circuit includes input pin information and output tube information of the black-box analog circuit pin information, the black box analog circuit includes a test resistor connected in series between the input pin and the output pin; the circuit information also includes input interface information and output interface information of the black box digital circuit;

a configuration information determining unit 120, configured to determine simulation configuration information for the black box circuit;

A circuit replacement unit 130, configured to replace the black box analog circuit with an analog circuit to be tested, and replace the black box digital circuit with a digital circuit to be tested, based on the storage location of the analog circuit to be tested and the black box The storage location of the digital circuit updates the simulation configuration information; the analog circuit under test has the same input pin information and output pin information as the black box analog circuit, and the digital circuit under test has the same input pin information and output pin information as the black box analog circuit. The same input interface information and output interface information of the digital circuit;

The simulation unit 140 is configured to use the updated simulation configuration information to simulate the circuit to be tested including the analog circuit to be tested and the digital circuit to be tested.

Optionally, the circuit replacement unit includes:

The first circuit replacement subunit is used to replace the verilog netlist of the black-box digital circuit with the verilog netlist of the digital circuit to be tested at the storage location of the verilog netlist of the black-box digital circuit;

a second circuit replacement subunit, configured to replace the netlist of the black-box analog circuit with the netlist of the analog circuit to be tested at the storage location of the netlist of the black-box analog circuit;

The configuration information replacement subunit is used to update the storage location of the verilog netlist of the black-box digital circuit in the simulation configuration information to the storage location of the netlist of the black-box analog circuit, and replace the The storage location of the verilog netlist of the digital circuit to be tested is replaced with the storage location of the netlist of the analog circuit to be tested.

Optionally, the simulation configuration information determined for the black-box circuit and the updated simulation configuration information also include: the storage location of the top-level netlist of the simulation system, the storage location of the verilog code of the outsourced test item layer of the black-box digital circuit. Storage location and the storage location of the netlist of the excitation circuit, the excitation circuit is used to provide an excitation signal; the storage location of the verilog code of the outsourced test item layer of the black box digital circuit and the outsourced test item layer of the digital circuit to be tested The verilog code is stored in the same location.

Optionally, the device further includes:

a script determination unit, configured to obtain a simulation configuration script according to the simulation configuration information and the storage location of the verilog netlist of the digital circuit to be tested, and the netlist of the analog circuit to be tested;

Then, the simulation unit is specifically used for:

The simulation configuration script is run to invoke the simulation EDA tool to perform a simulation operation on the circuit under test including the analog circuit under test and the digital circuit under test.

Optionally, the circuit information acquisition unit includes:

The digital circuit acquisition subunit is used to acquire the declaration information of the input interface and the output interface of the black-box digital circuit based on the verilog syntax; the verilog netlist of the black-box digital circuit is generated according to the declaration information;

The analog circuit acquisition subunit is configured to acquire circuit information of the black-box analog circuit, and generate a netlist of the black-box analog circuit according to the circuit information.

An embodiment of the present application provides a digital-analog hybrid circuit simulation device, which acquires circuit information of a black-box circuit including a black-box analog circuit and a black-box digital circuit, and the circuit information of the black-box circuit includes input pin information of the black-box analog circuit and output pin information, the black box analog circuit includes the test resistor connected in series between the input pin and the output pin, the circuit information also includes the input interface information and output interface information of the black box digital circuit, and determines the simulation configuration information for the black box circuit , after replacing the black-box analog circuit with the analog circuit to be tested, and replacing the black-box digital circuit with the digital circuit to be tested, update the simulation configuration information based on the storage location of the analog circuit to be tested and the storage location of the black-box digital circuit, you can use The updated simulation configuration information simulates the circuit to be tested including the analog circuit to be tested and the digital circuit to be tested, wherein the analog circuit to be tested has the same input pin information and output pin information as the black box analog circuit, and the digital circuit to be tested has the same input pin information and output pin information as the black box analog circuit. The circuit has the same input interface information and output interface information as the black box digital circuit. That is to say, in the embodiment of the present application, a black-box analog circuit can be established in advance according to the input pin information and output pin information of the analog circuit to be tested, and a black-box digital circuit can be established according to the input interface information and output interface information of the digital circuit to be tested. circuit, and determine the simulation configuration information for the black box circuit, so that the construction of the simulation system is set in the design stage of the analog circuit to be tested and the digital circuit to be tested. The built test system performs simulation operation, which reduces the time before the design completion node of the analog circuit to be tested and the digital circuit to be tested and the simulation operation node of the analog circuit to be tested and the digital circuit to be tested, and shortens the development cycle of the chip.

From the description of the above embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general hardware platform. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, and the computer software product can be stored in a storage medium, such as read-only memory (English: read-only memory, ROM)/RAM, magnetic disk, An optical disc, etc., includes several instructions for causing a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of the present application.

Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the apparatus embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for related parts. The device and system embodiments described above are only illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in One place, or it can be distributed over multiple network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment. Those of ordinary skill in the art can understand and implement it without creative effort.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the present application, several improvements and modifications can also be made, and these improvements and modifications should also be regarded as the protection scope of the present application.

Claims (10)

1. a digital-analog hybrid circuit simulation method, is characterized in that, comprises: Obtain circuit information of a black-box circuit including a black-box analog circuit and a black-box digital circuit; the circuit information of the black-box circuit includes input pin information and output pin information of the black-box analog circuit, and the black-box analog circuit The circuit includes a test resistor connected in series between the input pin and the output pin; the circuit information also includes input interface information and output interface information of the black-box digital circuit; determining simulation configuration information for the black box circuit; Replace the black-box analog circuit with an analog circuit to be tested, replace the black-box digital circuit with a digital circuit to be tested, and update the data based on the storage location of the analog circuit to be tested and the storage location of the black-box digital circuit. The simulation configuration information; the analog circuit under test has the same input pin information and output pin information as the black box analog circuit, and the digital circuit under test has the same input interface information as the black box digital circuit and output interface information; Using the updated simulation configuration information, the circuit under test including the analog circuit under test and the digital circuit under test is simulated. 2. The method according to claim 1, characterized in that, replacing the black box analog circuit with an analog circuit to be tested, replacing the black box digital circuit with a digital circuit to be tested, based on the The storage location of the analog circuit and the storage location of the black-box digital circuit update the simulation configuration information, including: Replace the verilog netlist of the black-box digital circuit with the verilog netlist of the digital circuit to be tested at the storage location of the verilog netlist of the black-box digital circuit; Replace the netlist of the black-box analog circuit with the netlist of the analog circuit to be tested at the storage location of the netlist of the black-box analog circuit; Update the storage location of the verilog netlist of the black-box digital circuit in the simulation configuration information to the storage location of the netlist of the black-box analog circuit, and update the verilog netlist of the digital circuit to be tested in the simulation configuration information The storage location of is replaced with the storage location of the netlist of the analog circuit under test. 3. The method according to claim 2, wherein the simulation configuration information determined for the black box circuit and the updated simulation configuration information further comprise: the storage location of the top-level netlist of the simulation system, the black box circuit The storage position of the verilog code of the outsourcing test item layer of the box digital circuit and the storage position of the netlist of the excitation circuit, the excitation circuit is used to provide the excitation signal; the storage position of the verilog code of the outsourcing test item layer of the black box digital circuit and The storage locations of the verilog codes of the outsourced test item layer of the digital circuit to be tested are the same. 4. The method according to claim 2, wherein the method further comprises: According to the simulation configuration information and the storage location of the verilog netlist of the digital circuit to be tested, and the netlist of the analog circuit to be tested, a simulation configuration script is obtained; Then, the simulation of the circuit under test including the analog circuit under test and the digital circuit under test by using the simulation configuration information includes: The simulation configuration script is run to invoke the simulation EDA tool to perform a simulation operation on the circuit under test including the analog circuit under test and the digital circuit under test. 5. The method according to any one of claims 1-4, wherein, The acquiring the input interface information and output interface information of the black-box digital circuit includes: acquiring declaration information of the input interface and output interface of the black-box digital circuit based on verilog syntax; generating the black-box digital circuit according to the declaration information The verilog netlist of the circuit; The acquiring the input pin information and output pin information of the black-box analog circuit includes: acquiring circuit information of the black-box analog circuit, and generating a netlist of the black-box analog circuit according to the circuit information. 6. A digital-analog hybrid circuit emulation device is characterized in that, comprising: A circuit information acquisition unit for acquiring circuit information of a black-box circuit including a black-box analog circuit and a black-box digital circuit; the circuit information of the black-box circuit includes input pin information and output pin information of the black-box analog circuit information, the black box analog circuit includes a test resistor connected in series between the input pin and the output pin; the circuit information also includes input interface information and output interface information of the black box digital circuit; a configuration information determining unit, configured to determine simulation configuration information for the black box circuit; A circuit replacement unit for replacing the black-box analog circuit with an analog circuit to be tested, and replacing the black-box digital circuit with a digital circuit to be tested, based on the storage location of the analog circuit to be tested and the black-box digital circuit The storage location of the circuit updates the simulation configuration information; the analog circuit under test has the same input pin information and output pin information as the black box analog circuit, and the digital circuit under test has the same input pin information and output pin information as the black box analog circuit. The same input interface information and output interface information of the circuit; The simulation unit is used for simulating the circuit under test including the analog circuit under test and the digital circuit under test by using the updated simulation configuration information. 7. The device according to claim 6, wherein the circuit replacement unit comprises: The first circuit replacement subunit is used to replace the verilog netlist of the black-box digital circuit with the verilog netlist of the digital circuit to be tested at the storage location of the verilog netlist of the black-box digital circuit; a second circuit replacement subunit, configured to replace the netlist of the black-box analog circuit with the netlist of the analog circuit to be tested at the storage location of the netlist of the black-box analog circuit; The configuration information replacement subunit is used to update the storage location of the verilog netlist of the black-box digital circuit in the simulation configuration information to the storage location of the netlist of the black-box analog circuit, and replace the The storage location of the verilog netlist of the digital circuit to be tested is replaced with the storage location of the netlist of the analog circuit to be tested. 8. The apparatus according to claim 7, wherein the simulation configuration information determined for the black box circuit and the updated simulation configuration information further comprise: a storage location of a top-level netlist of the simulation system, the black box circuit The storage position of the verilog code of the outsourcing test item layer of the box digital circuit and the storage position of the netlist of the excitation circuit, the excitation circuit is used to provide the excitation signal; the storage position of the verilog code of the outsourcing test item layer of the black box digital circuit and The storage locations of the verilog codes of the outsourced test item layer of the digital circuit to be tested are the same. 9. The apparatus of claim 7, wherein the apparatus further comprises: a script determination unit, configured to obtain a simulation configuration script according to the simulation configuration information and the storage location of the verilog netlist of the digital circuit to be tested, and the netlist of the analog circuit to be tested; Then, the simulation unit is specifically used for: The simulation configuration script is run to invoke the simulation EDA tool to perform a simulation operation on the circuit under test including the analog circuit under test and the digital circuit under test. 10. The device according to any one of claims 6-9, wherein the circuit information acquisition unit comprises: The digital circuit acquisition subunit is used to acquire the declaration information of the input interface and the output interface of the black box digital circuit based on the verilog grammar; according to the declaration information, the verilog netlist of the black box digital circuit is generated; The analog circuit acquisition subunit is configured to acquire circuit information of the black-box analog circuit, and generate a netlist of the black-box analog circuit according to the circuit information.

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