CN114610324B

CN114610324B - Binary translation method, processor and electronic device

Info

Publication number: CN114610324B
Application number: CN202210192731.5A
Authority: CN
Inventors: 兰彦志; 曾露
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2022-02-28
Filing date: 2022-02-28
Publication date: 2025-09-23
Anticipated expiration: 2042-02-28
Also published as: CN114610324A

Abstract

The embodiment of the invention provides a binary translation method, a processor and electronic equipment, which are applied to a binary translation system, wherein the method comprises the steps of obtaining a first jump instruction, wherein the first jump instruction is an instruction of a target program in a host, the first jump instruction corresponds to a first jump address and a second jump address, the first jump address is a target jump address to be jumped under the condition that the first jump instruction meets the jump condition, and the second jump address is a target jump address to be jumped under the condition that the first jump instruction does not meet the jump condition; counting the number of times of jumping from the first jump instruction to the second jump address in the process of executing the first jump instruction, and if the number of times of jumping is larger than a first preset threshold value, carrying out instruction rearrangement on the first jump address and the second jump address. The embodiment of the invention can reduce the overall hardware overhead of the binary translation system and improve the operation efficiency of the binary translation system.

Description

Binary translation method, processor and electronic equipment

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a binary translation method, a processor, and an electronic device.

Background

The CPU (Central Processing Unit ) instruction set is divided from the instruction complexity perspective, and can be divided into complex instruction set computer (Complex Instruction Set Computer, CISC) instructions and reduced instruction set computer (Reduced Instruction Set Computer RISC, RISC) instructions. The CISC has the advantages of large instruction number, large difference of applicable frequencies, different instruction lengths, small instruction number of RISC, similar applicable frequencies and fixed instruction lengths. The more simplified RISC instruction set makes it easier to design a multi-stage pipeline and multi-stage processor caches, thereby improving microprocessor performance.

With the continuous development of microprocessor technology, the performance of microprocessors has become stronger, so that a computer can process different CPU instruction sets simultaneously, and the processing efficiency is improved, and a binary translation technology has been developed. The technology can enable a source program to be translated of one CPU architecture to run on another CPU architecture, for example, the software ecology of the mature CPU architecture can be quickly migrated to a new CPU architecture. However, the technology still has the technical problems of low translation efficiency, excessive redundant operation and the like at present, and in order to solve the problem of low efficiency of a binary translator, some microprocessors provide an additional two-level translator in a processor core to support optimization of translated codes. However, the existing two-level system translator has large hardware overhead and low operation efficiency, and the performance of the two-level system translator needs to be improved.

Disclosure of Invention

The embodiment of the invention provides a binary translation method, a processor and electronic equipment, which can solve the problems of high hardware overhead and low operation efficiency of a binary translator in the prior art.

In order to solve the above problems, an embodiment of the present invention discloses a binary translation method applied to a binary translation system for translating a source program in a client into a target program in a host, the method comprising:

Acquiring a first jump instruction, wherein the first jump instruction is an instruction of a target program in the host, the first jump instruction corresponds to a first jump address and a second jump address, the first jump address is a target jump address to which the first jump instruction is to jump under the condition that the first jump instruction meets the jump condition, and the second jump address is a target jump address to which the first jump instruction is to jump under the condition that the first jump instruction does not meet the jump condition;

Counting the number of times of jumping from the first jump instruction to the second jump address in the process of executing the first jump instruction;

And if the jump times are greater than a first preset threshold value, carrying out instruction rearrangement on the first jump address and the second jump address.

In another aspect, an embodiment of the present invention discloses a processor applied to a binary translation system for translating a source program in a client into a target program in a host, the microprocessor comprising:

The instruction fetching unit is used for acquiring a first jump instruction, wherein the first jump instruction is an instruction of a target program in the host, the first jump instruction corresponds to a first jump address and a second jump address, the first jump address is a target jump address to which the first jump instruction is to jump under the condition that the first jump instruction meets the jump condition, and the second jump address is a target jump address to which the first jump instruction is to jump under the condition that the first jump instruction does not meet the jump condition;

And the processing unit is used for counting the jump times of the first jump instruction to the second jump address in the process of executing the first jump instruction, and carrying out instruction rearrangement on the first jump address and the second jump address if the jump times are larger than a first preset threshold value.

In yet another aspect, an embodiment of the present invention further discloses an electronic device, where the electronic device includes a memory, and one or more programs, where the one or more programs are stored in the memory and configured to execute the binary translation method described above by the one or more processors.

The embodiment of the invention also discloses a readable storage medium, which enables the electronic device to execute the binary translation method when the instructions in the storage medium are executed by the processor of the electronic device.

The embodiment of the invention has the following advantages:

In the embodiment of the invention, in the process of executing the first jump instruction in the host, the number of times that the first jump instruction jumps to the second jump address is counted, wherein the number of times that the first jump instruction jumps to the second jump address can also be called as the number of times that the first jump instruction does not meet the jump condition or the number of times that the first jump instruction misses. Then, under the condition that the number of times of jumping to the second jumping address is larger than a first preset threshold value, the first jumping address and the second jumping address are subjected to instruction rearrangement, so that the addresses with more jumping times are positioned on a jumping path with smaller expenditure, the overall hardware expenditure of the binary translation system is reduced, and the running efficiency of the binary translation system is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of steps of an embodiment of a binary translation method of the present invention;

FIG. 2 is a schematic diagram of an execution flow of a target program according to the present invention;

FIG. 3 is a schematic diagram illustrating a reorder flow of a jump instruction according to the present invention;

FIG. 4 is a schematic diagram of another object execution flow of the present invention;

FIG. 5 is a schematic diagram of an execution flow of another object program according to the present invention;

FIG. 6 is a schematic diagram of a skip refill table of the present invention;

FIG. 7 is a flow chart of the steps of a binary translation process of the present invention;

FIG. 8 is a block diagram of a processor of the present invention;

FIG. 9 is a block diagram of another processor of the present invention;

FIG. 10 is a block diagram of an electronic device for binary translation of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Method embodiment

Referring to fig. 1, a flowchart illustrating steps of an embodiment of a binary translation method of the present invention is shown, and is applied to a binary translation system, where the method may specifically include the steps of:

Step 101, a first jump instruction is acquired, wherein the first jump instruction is an instruction of a target program in a host, and the first jump instruction corresponds to a first jump address and a second jump address.

Step 102, counting the number of hops from the first jump instruction to the second jump address in the process of executing the first jump instruction.

And 103, if the number of times of the jump is greater than a first preset threshold, carrying out instruction rearrangement on the first jump address and the second jump address.

The binary translation method provided by the embodiment of the invention can be applied to a binary translation system. The binary translation system is used for translating a source program in a client into a target program in a host. The first jump instruction is a host corresponding instruction, the first jump instruction corresponds to a first jump address and a second jump address, the first jump address is a target jump address to which the first jump instruction is to jump under the condition that the first jump instruction meets the jump condition, and the second jump address is a target jump address to which the first jump instruction is to jump under the condition that the first jump instruction does not meet the jump condition.

It should be noted that, the source program is a binary code. In the translation process, the binary translation system can only take the binary code (namely the source program) subjected to compiling processing, and the binary code is disassembled to obtain the code of the assembly level, and at the moment, the code cannot be segmented by taking the function in the source program as a basic unit. Typically, binary translation systems split the resulting source program into one and the next translation units, with the last instruction of each translation unit typically being a jump instruction in the source program. The binary translation system works with the translation unit as a basic unit.

In the embodiment of the invention, the first jump instruction is an instruction of a target program in a host, and a client jump instruction corresponding to the first jump instruction exists in a source program of a client. In the source program, the jump instruction corresponds to two jump directions, one is the jump direction when the jump condition is satisfied, and the other is the jump direction when the jump condition is not satisfied, and each jump direction corresponds to one jump address. Assume that, for a jump instruction A1 in the source program, the offset address when the jump condition is satisfied is offset0, and the offset address when the jump condition is not satisfied is offset1. In the source program, after judging the jump instruction, the processor can jump to the target jump address directly according to the jump condition, the offset address and the address of the jump instruction. In other words, in the source procedure, the overhead to offset0 and offset1 is the same. However, after the translation processing is performed on the source program by the two-level translation system, the original instruction sequence is disturbed, and the next instruction of the currently executed jump instruction and the jump instruction do not necessarily belong to the same instruction sequence in the target program of the host. In addition, a large number of B instructions are inserted into the translated target program, when the target program in the host machine goes to the target jump address corresponding to the offset1, one or more B offset1 instructions need to be executed first, and the B instructions are also jump instructions, so when the target program goes to the target jump address corresponding to the offset1, continuous jump is often needed, cavitation is generated in continuous jump, and errors are easily caused when the host machine prefetches instructions, thereby influencing the operation efficiency of the binary translation system.

For example, assume that the jump condition of the first jump instruction A1 is a=b, the offset address corresponding to the first jump address is offset0, the offset address corresponding to the second jump address is offset1, the instruction stored in the first jump address is instruction A2, and the instruction stored in the second jump address is instruction A3. Referring to fig. 2, a schematic diagram of an execution flow of a target program according to an embodiment of the present invention is shown. As shown in fig. 2, when executing the first jump instruction A1, the processor determines whether the first jump instruction A1 satisfies a jump condition, if the jump condition (a=b) is satisfied, directly jumps to the first jump address, acquires the instruction A2 from the first jump address and executes the instruction A2, and if the jump condition (a+.b) is not satisfied, before going to the second jump address, one or more "b offset1" instructions need to be executed first, then the instruction A3 can be acquired from the second jump address and executed, which increases the hardware overhead of the binary translation system and affects the operation efficiency of the binary translation system.

In order to solve the problem, in the process of executing the first jump instruction in the target program, firstly, counting the number of times the first jump instruction jumps to the second jump address, wherein the number of times the first jump instruction jumps to the second jump address can also be called as the number of times the first jump instruction does not meet the jump condition or the number of times the first jump instruction misses, and then, under the condition that the number of times the first jump instruction jumps to the second jump address (the number of times the first jump instruction misses) is larger than a first preset threshold value, carrying out instruction rearrangement on the first jump address and the second jump address, so that the target program reduces the number of times of the jump address corresponding to the forward offset1 as far as possible, so as to reduce the number of times of operation of the 'b offset 1' instruction, reduce the hardware overhead of a binary translation system and improve the operation efficiency of the binary translation system.

As an example, the instruction reordering of the first jump address and the second jump address in step 103 includes setting an exception to execute a custom exception service program to modify a jump direction of the first jump instruction in the memory pool when the number of jumps is greater than a first preset threshold, and exchanging instructions stored in the first jump address and the second jump address, so that the first jump instruction jumps to the second jump address when a jump condition is satisfied, and jumps to the first jump address when the jump condition is not satisfied.

During the running process of the program, the exception mechanism is generally used to handle the exception events that occur, for example, exception events such as overflow except 0, crossing of the array, file failing to find, etc. During program execution, if an exception occurs, an object representing the exception may be generated, the object containing details of the exception, and then submitted to the runtime system, which looks for the corresponding code to handle the exception.

In the embodiment of the invention, the first jump address and the second jump address of the first jump instruction can be rearranged by executing the custom exception service program. Referring to fig. 3, a schematic rearrangement flow of a jump instruction according to an embodiment of the present invention is shown. As shown in fig. 3, a first preset threshold of the skip refill table may be set before the target program in the host is executed. The jump refill table is used for recording the running times and the miss times of the first jump instruction (namely, the times that the first jump instruction does not meet the jump condition). The PC is an address of the first jump instruction, and the address of the first jump instruction may be used as an instruction identifier of the first jump instruction. And updating the running times and the miss times corresponding to the first jump instruction in the jump refill table according to the PC of the first jump instruction when the first jump instruction is executed once. In the embodiment of the invention, the number of times of the missed hits of the first jump instruction is larger than the first preset threshold value as an abnormal event, and if the number of times of the missed hits of the first jump instruction is larger than the first preset threshold value, an exception is triggered, and the instruction rearrangement of the first jump address and the second jump address of the first jump instruction is realized by executing the self-defined exception service program. Specifically, as shown in fig. 3, the first jump address and the second jump address recorded in the memory pool may be exchanged by executing the custom exception service program to change the jump direction of the first jump instruction, so that the first jump instruction goes to the second jump address when the jump condition is satisfied and goes to the first jump address when the jump condition is not satisfied, and the instructions stored in the first jump address and the second jump address are exchanged. Illustratively, prior to instruction reordering, instruction A2 is stored in the first jump address and instruction A3 is stored in the second jump address. Through instruction reordering, the instruction stored in the first jump address becomes instruction A3 and the instruction stored in the second jump address becomes instruction A2.

Referring to fig. 4, a schematic diagram of an execution flow of another object program according to an embodiment of the present invention is shown. As shown in fig. 4, the processor proceeds to fetch the instruction A2 from the second jump address and execute it if it is determined that the first jump instruction satisfies the jump condition (a=b), and proceeds to fetch the instruction A3 from the first jump address and execute it if it is determined that the first jump instruction does not satisfy the jump condition (a+.b). Compared with the execution flow of the target program before the instruction rearrangement shown in fig. 2, after the first jump address and the second jump address are rearranged, the next instruction to be executed is still the instruction A2 under the condition of a=b, the next instruction to be executed is still the instruction A3 under the condition of a+.b, and the execution logic of the target program is not changed, but after the instruction rearrangement, the target program does not need to go to the second jump address corresponding to the offset1 again under the condition that the first jump instruction does not meet the jump condition, and the instruction A3 can be directly obtained from the first jump address corresponding to the offset0 and executed. Although the target jump program still executes the "b offset1" instruction to the second jump address when the first jump instruction satisfies the jump condition, the number of times of the first jump instruction satisfying the jump condition is smaller than the number of times of the first jump instruction not satisfying the jump condition in the same time because the number of times of the first jump instruction missing is larger than the first preset threshold, compared with the execution flow shown in fig. 2, in the execution flow shown in fig. 4, the number of times of the operation of the "b offset1" instruction is effectively reduced, thereby reducing the hardware overhead of the binary translation system and improving the operation efficiency of the binary translation system.

As another example, rearranging the first jump address and the second jump address in step 103 includes reversing a jump condition of the first jump instruction and swapping instructions stored in the first jump address and the second jump address.

In the embodiment of the invention, the instruction rearrangement of the first jump address and the second jump address can be realized by inverting the jump condition of the first jump instruction and exchanging the instructions stored in the first jump address and the second jump address.

Assuming that the original jump condition of the first jump instruction A1 is a=b, the jump condition of the first jump instruction A1 is a+.b after the jump condition is inverted. Before instruction rearrangement, the first jump address stores instruction A2, and the second jump address stores instruction A3. Through instruction reordering, the instruction stored in the first jump address becomes instruction A3 and the instruction stored in the second jump address becomes instruction A2.

Referring to fig. 5, a schematic diagram of an execution flow of another object program according to an embodiment of the present invention is shown. As shown in fig. 5, the processor proceeds to fetch instruction A3 into the first jump address and execute it if it is determined that the first jump instruction satisfies the jump condition (a+.b), and proceeds to fetch instruction A2 into the second jump address and execute it if it is determined that the first jump instruction does not satisfy the jump condition (a=b). Compared with the execution flow of the target program before the instruction rearrangement shown in fig. 2, after the first jump address and the second jump address are rearranged, the next instruction to be executed is still the instruction A2 under the condition of a=b, the next instruction to be executed is still the instruction A3 under the condition of a not equal b, and the execution logic of the target program is not changed, but through the instruction rearrangement, the target program can directly acquire the instruction A3 from the first jump address corresponding to the offset0 and execute the instruction A3 without going to the second jump address corresponding to the offset1 under the condition of a not equal b. Although the target jump procedure still executes the "b offset1" instruction to the second jump address under the condition of a=b, the number of times of the first jump instruction meeting a condition that a=b is smaller than the number of times of meeting a=b in the same time as the first jump instruction is larger than the first preset threshold before the instruction rearrangement, so that compared with the execution flow shown in fig. 2, the running number of times of the "b offset1" instruction is effectively reduced, the hardware overhead of the binary translation system is reduced, and the running efficiency of the binary translation system is improved.

In an alternative embodiment of the invention, the method further comprises:

Step S11, if the number of times of jump is smaller than or equal to a first preset threshold value and the currently executed instruction is the first jump instruction, judging whether the first jump instruction meets a jump condition or not;

step S12, if the first jump instruction meets the jump condition, jumping to the first jump address, and acquiring a target instruction from the first jump address and executing the target instruction;

And step S13, if the first jump instruction does not meet the jump condition, executing an expansion instruction, then jumping to the second jump address, and acquiring and executing a target instruction from the second jump address, wherein the expansion instruction is generated in the process of translating the source program to be translated by the binary translation system.

In the embodiment of the present invention, if the number of hops from the first jump instruction to the second jump address, that is, the number of misses of the first jump instruction, is smaller than the first preset threshold, the first jump address and the second jump address of the first jump instruction are not rearranged, and the first jump instruction is still executed according to the processing procedure in the existing binary translator. Specifically, whether the first jump instruction meets the jump condition is judged, if yes, the first jump instruction is directly jumped to a first jump address, a target instruction is obtained from the first jump address and executed, and if not, the second jump address is jumped to after the expansion instruction is executed, and the target instruction is obtained from the second jump address and executed.

As an example, assume that a first offset address corresponding to a first jump address is offset0 and a second offset address corresponding to a second jump address is offset1 in the target program. If the number of times of the missed hits of the first jump instruction is smaller than or equal to a first preset threshold value, the first jump instruction is directly sent to the first jump address to acquire the target instruction when the first jump instruction meets the jump condition, and when the first jump instruction does not meet the jump condition, a b offset1 instruction is firstly operated, and then the second jump instruction is sent to the second jump address to acquire the target instruction. Because the number of times of the first jump instruction jumping to the second jump address is smaller than or equal to a first preset threshold, that is, a b offset1 instruction needs to be executed before each time going to the second jump address, the number of times of executing the boffset instruction is also smaller than the first preset threshold, the hardware cost is limited, and the influence on the operation efficiency of the binary translation system is small. Therefore, by setting the first preset threshold, the embodiment of the invention adopts the corresponding instruction execution strategy according to the relationship between the number of times of missed jump instructions and the first preset threshold, thereby effectively controlling the hardware overhead of the binary translation system.

In an optional embodiment of the present invention, step 102, counting the number of hops of the first jump instruction to the second jump address during the process of executing the first jump instruction includes:

step S21, counting the running times of the first jump instruction and the jump times to the second jump address in the process of executing the first jump instruction;

step S22, recording the operation times and the jump times in a preset jump refill table.

In the embodiment of the present invention, the running number of the first jump instruction and the number of jumps to the second jump address (hereinafter referred to as "miss number") may be recorded through a preset jump refill table. Referring to fig. 6, a schematic diagram of a skip refill table according to an embodiment of the present invention is shown. As shown in fig. 6, an address (PC) of the first jump instruction in the target program may be used as an instruction identification of the first jump instruction in order to distinguish each first jump instruction according to the address, and record the number of misses (Not TAKEN TIMES) and the number of runs (run times) of each first jump instruction.

As an example, the first jump instruction that needs to count the number of misses in the target program may be marked according to actual requirements, and in the process of executing the target program, only the number of misses of the marked first jump instruction, that is, the number of jumps to the second jump address, and the number of runs of the first jump instruction are counted, and the counted result is recorded in the jump refill table. The binary translation system can determine whether the first jump address and the second jump address of the first jump instruction need to be rearranged by inquiring the jump refill table, so that the information inquiry efficiency of the binary translation system is improved.

In an alternative embodiment of the present invention, after the instruction rearrangement of the first jump address and the second jump address, the method further includes converting the first jump instruction into a second jump instruction, and continuing to sequentially execute a next instruction, where the binary translation system does not count the running number and the jump number of the second jump instruction.

It should be noted that, in the embodiment of the present invention, only the running times and the jumping times of the marked first jumping instruction are counted and recorded in the jumping refill table, and the running times and the jumping times of other jumping instructions in the target program, that is, the second jumping instruction, are not counted. Compared with the first jump instruction, the second jump instruction is a first jump instruction subjected to instruction rearrangement, and when the second jump instruction is executed, no matter whether the second jump instruction meets the jump condition or not, the number of times of executing the B instruction by the processor is effectively reduced, so that any processing on the second jump instruction is not needed, namely, the running number and the jump number of the second jump instruction are not needed to be recorded in the jump refill table, so that excessive occupation of table items in the jump refill table is avoided, and the utilization rate of the jump refill table is improved.

After the first jump instruction is converted into the second jump instruction, the next instruction is continuously executed according to the sequence of each instruction in the target program.

In an alternative embodiment of the invention, the method further comprises:

And if the running times of the first jump instruction are larger than a second preset threshold value, resetting the running times and the jump times of the first jump instruction in the jump refill table.

In the embodiment of the invention, the running times and the jumping times of the first jumping instructions in the jumping refill table can be cleared under the condition that the running times of the first jumping instructions are larger than the second preset threshold value, so that timeliness of the running times and the jumping times recorded in the jumping refill table is ensured, and data redundancy is avoided. The first preset threshold and the second preset threshold may be set according to actual requirements, which is not specifically limited in the embodiment of the present invention, and in general, the first preset threshold is smaller than the second preset threshold.

In addition, in the embodiment of the invention, when the skip refill table is full, that is, when no idle table item exists, the information corresponding to the first skip instruction recorded earliest can be covered according to the recorded time of each first skip instruction, or the information corresponding to the first skip instruction with the lowest information update frequency can be covered according to the information update frequency of each first skip instruction within the preset time, so as to ensure that the information, such as the running times and the skip times, of the first skip instruction currently executed is recorded in the skip refill table in real time.

In an alternative embodiment of the present invention, before the step 101 of obtaining the first jump instruction, the method further includes:

Step S31, acquiring a source program to be translated, wherein the source program comprises at least one jump instruction;

step S32, cutting the source program based on the jump instruction to obtain at least one translation unit;

step S33, performing disassembly processing on the at least one translation unit to obtain an assembler corresponding to each translation unit;

step S34, a translation function is called to translate the assembler corresponding to each translation unit, and the target program corresponding to each translation unit is obtained.

The target program in the host is obtained by translating the source program in the client by a binary translation system. Referring to fig. 7, a flowchart of steps of a binary translation process according to an embodiment of the present invention is shown. As shown in fig. 7, specifically, after the binary translation system obtains the source program to be translated, the source program is firstly segmented based on the jump instruction in the source program, so as to obtain a translation unit, that is, a basic working unit of the binary translation system. And then, the binary translation system performs disassembly processing on the translation units to obtain assembler programs corresponding to each translation unit. Wherein each translation unit corresponds to an assembler. And finally, the binary translation system calls a corresponding translation function to translate the obtained assembler, so that the target program corresponding to the translation unit can be obtained. The translation function may be any function that is good at translating instructions in the field, which is not specifically limited in this embodiment of the present invention.

When the binary translation system processes the source program to be translated, the binary translation system processes the source program to be translated according to the sequence of the segmented translation units and the sequence among the translation units. Specifically, the binary translation system sequentially executes the target programs corresponding to the translation units according to the order of the translation units after obtaining the target programs corresponding to the translation units. In an alternative embodiment of the invention, the method further comprises:

Step S41, judging whether the assembler corresponding to the current translation unit is translated;

step S42, if the assembler corresponding to the current translation unit finishes translation, the next translation unit is translated according to a preset sequence.

For an assembler corresponding to the current translation unit, the binary translation system firstly judges whether the assembler is translated. And if the assembler finishes translation, carrying out translation processing on the next translation unit according to the sequence of the translation units, namely the preset sequence. The preset termination condition may be that the translation program of the binary translation system exits logic, or that no other translation unit exists after the current translation unit according to a preset sequence, and so on.

In an optional embodiment of the present invention, in step S32, the splitting the source program to be translated based on the jump instruction obtains at least one translation unit, including:

step S321, searching and marking a jump instruction in a source program to be translated;

sub-step S322, determining whether a fourth jump instruction exists before the third jump instruction in the source program;

Sub-step S323, extracting the third jump instruction from the source program and extracting an instruction between the third jump instruction and the fourth jump instruction if the fourth jump instruction exists before the third jump instruction, so as to obtain a translation unit;

In sub-step S324, if the fourth jump instruction does not exist before the third jump instruction, the first jump instruction and the previous instructions are extracted from the source program, and a translation unit is obtained.

The third jump instruction and the fourth jump instruction are any jump instruction in the source program, and the fourth jump instruction is located before the third jump instruction.

In the embodiment of the invention, the jump instruction in the source program to be translated can be used as a segmentation point to segment the source program. Specifically, the jump instruction in the source program is searched first, and the found jump instruction is marked, so that the identification is convenient. Then, for each of the marked jump instructions, i.e., the third jump instruction, it is determined whether there is a fourth jump instruction located before it. And if the fourth jump instruction does not exist before the third jump instruction, the third jump instruction is the first jump instruction in the source program, and the third jump instruction and the instructions before the third jump instruction are extracted from the source program, so that a translation unit can be obtained.

In summary, the embodiment of the present invention provides a binary translation method, which can count the number of times the first jump instruction jumps to the second jump address in the process of executing the first jump instruction in the host, where the number of times the first jump instruction jumps to the second jump address may also be referred to as the number of times the first jump instruction does not meet the jump condition, or the number of times the first jump instruction misses. Then, under the condition that the number of times of jumping to the second jumping address is larger than a first preset threshold value, the first jumping address and the second jumping address are subjected to instruction rearrangement, so that the addresses with more jumping times are positioned on a jumping path with smaller expenditure, the overall hardware expenditure of the binary translation system is reduced, and the running efficiency of the binary translation system is improved.

It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.

Device embodiment

Referring to FIG. 8, which shows a block diagram of a processor of the present invention, applied to a binary translation system for translating a source program in a client into a target program in a host, the processor 80 may specifically include:

A fetching unit 801, configured to obtain a first jump instruction, where the first jump instruction is a target program instruction in the host, the first jump instruction corresponds to a first jump address and a second jump address, the first jump address is a target jump address to be jumped when the first jump instruction meets a jump condition, and the second jump address is a target jump address to be jumped when the first jump instruction does not meet the jump condition;

And a processing unit 802, configured to count a number of hops from the first jump instruction to the second jump address in a process of executing the first jump instruction, and if the number of hops is greater than a first preset threshold, reorder the first jump address and the second jump address.

In an alternative embodiment of the invention, the processing unit is specifically configured to:

Executing a custom exception service program to modify the jump direction of the first jump instruction in the memory pool, and exchanging instructions stored in the first jump address and the second jump address, so that the first jump instruction jumps to the second jump address when the jump condition is met, and jumps to the first jump address when the jump condition is not met.

And inverting the jump condition of the first jump instruction, and exchanging instructions stored in the first jump address and the second jump address.

Counting the running times of the first jump instruction and the jump times to the second jump address in the process of executing the first jump instruction;

and recording the running times and the jump times in a preset jump refill table.

In an alternative embodiment of the invention, the processing unit is further adapted to:

And converting the first jump instruction into a second jump instruction, and continuing to sequentially execute the next instruction, wherein the binary translation system does not count the running times and the jump times of the second jump instruction.

If the number of times of jump is smaller than or equal to a first preset threshold value and the currently executed instruction is the first jump instruction, judging whether the first jump instruction meets a jump condition or not;

If the first jump instruction meets the jump condition, jumping to the first jump address, acquiring a target instruction from the first jump address and executing the target instruction;

if the first jump instruction does not meet the jump condition, executing an expansion instruction, then jumping to the second jump address, and acquiring a target instruction from the second jump address and executing the target instruction, wherein the expansion instruction is generated in the process of translating the source program to be translated by the binary translation system.

In an alternative embodiment of the present invention, the finger taking unit is further configured to:

Acquiring a source program to be translated, wherein the source program comprises at least one jump instruction;

the processing unit is further configured to:

Dividing the source program based on the jump instruction to obtain at least one translation unit;

performing disassembly processing on the at least one translation unit to obtain an assembler corresponding to each translation unit;

And calling a translation function to translate the assembler corresponding to each translation unit to obtain the target program corresponding to each translation unit.

searching and marking a jump instruction in a source program to be translated;

Judging whether a fourth jump instruction exists before a third jump instruction in the source program, wherein the third jump instruction and the fourth jump instruction are any jump instruction in the source program, and the fourth jump instruction is positioned before the third jump instruction;

If the fourth jump instruction exists before the third jump instruction, extracting the third jump instruction from the source program to be translated, and extracting an instruction between the third jump instruction and the fourth jump instruction to obtain a translation unit;

And if the fourth jump instruction does not exist before the third jump instruction, extracting the first jump instruction and the previous instructions from the source program to obtain a translation unit.

judging whether the assembler corresponding to the current translation unit is translated;

and if the translation of the assembler corresponding to the current translation unit is finished, carrying out translation processing on the next translation unit according to a preset sequence.

It should be noted that the processor 80 may further include a decoding unit 803. The decoding unit 803 is configured to decode an instruction to be executed.

The processing unit 802 may include an execution unit 8021. The execution unit 8021 is used to perform arithmetic operations.

Optionally, the processing unit 802 may also include a physical register file 8022. During execution of an instruction, source operands may be included in the instruction, which need to be read from physical register file 8022. Other data related to instruction execution may also be stored in the physical register file. For example, the execution results of the execution unit 8021 are written back into the physical register file 8022.

Alternatively, the execution unit 8021 may include at least one operation unit. The at least one arithmetic unit may be of different types, e.g., fixed point arithmetic units, floating point arithmetic units, etc.

Alternatively, the processor provided in the embodiment of the present invention may be a single-emission processor. A single-issue processor refers to fetching only one instruction from memory in one clock cycle, decoding only one instruction, executing only one instruction, and writing only one operation result.

It should be noted that, the embodiment of the present invention does not limit the type and implementation of the processor, and for example, the processor may be a microprocessor, a chip, or the like.

Fig. 9 is a block diagram of another structure of a processor according to an embodiment of the present invention. The processor shown in fig. 9 may be a multi-processor, as compared to the processor shown in fig. 8. A multi-issue processor refers to a processor that can fetch multiple instructions from memory simultaneously in one clock cycle while decoding the multiple instructions. As shown in fig. 9, the processor provided in the embodiment of the present invention may further include a renaming unit 8023, a transmitting unit 8024, and a reordering unit 8025 on the basis of the processor shown in fig. 8.

Wherein the renaming unit 8023 is used to rename addresses of the write-back physical register file 8022 of instructions.

The issue unit 8024 is used to determine which unit to issue instructions for execution, e.g., to an execution unit for execution, or to a fixed point arithmetic unit in an execution unit for execution, or to a floating point arithmetic unit in an execution unit for execution, etc.

The reorder unit 8025 is configured to mark data of write-back addresses of instructions in the physical register file 8022 as committed, in the order of the instructions.

In summary, the embodiments of the present invention provide a processor, where the microprocessor can count the number of times the first jump instruction jumps to the second jump address in the process of executing the first jump instruction in the host, where the number of times the first jump instruction jumps to the second jump address may also be referred to as the number of times the first jump instruction does not satisfy the jump condition, or the number of times the first jump instruction misses. Then, under the condition that the number of times of jumping to the second jumping address is larger than a first preset threshold value, the first jumping address and the second jumping address are subjected to instruction rearrangement, so that the addresses with more jumping times are positioned on a jumping path with smaller expenditure, the overall hardware expenditure of the binary translation system is reduced, and the running efficiency of the binary translation system is improved.

For processor embodiments, the description is relatively simple as it is substantially similar to method embodiments, as relevant points are found in the partial description of method embodiments.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

The embodiment of the invention provides electronic equipment for binary translation, which is applied to a binary translation system and is used for translating a source program in a client into a target program in a host, wherein the electronic equipment comprises a memory and one or more programs, one or more programs are stored in the memory and are configured to be executed by one or more processors, the one or more programs comprise instructions for acquiring a first jump instruction, the first jump instruction is an instruction of the target program in the host, the first jump instruction corresponds to a first jump address and a second jump address, the first jump address is a target jump address to which the first jump instruction is to be jumped under the condition that the first jump instruction meets the jump, the second jump address is a target jump address to which the first jump instruction is to be jumped under the condition that the first jump instruction does not meet the jump, the first jump instruction is statistically set to the first jump address and the second jump address in the first jump instruction, and the first jump address is greater than the first jump threshold number is set.

Fig. 10 is a block diagram illustrating a configuration of an electronic device 300 for binary translation, according to an example embodiment. For example, electronic device 300 may be a mobile phone, computer, digital broadcast terminal, messaging device, game console, tablet device, medical device, exercise device, personal digital assistant, or the like.

Referring to FIG. 10, the electronic device 300 may include one or more of a processing component 302, a memory 304, a power supply component 306, a multimedia component 308, an audio component 310, an input/output (I/O) interface 312, a sensor component 314, and a communication component 316.

The processing component 302 generally controls overall operation of the electronic device 300, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing element 302 may include one or more processors 80 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 302 can include one or more modules that facilitate interactions between the processing component 302 and other components. For example, the processing component 302 may include a multimedia module to facilitate interaction between the multimedia component 308 and the processing component 302.

The memory 304 is configured to store various types of data to support operations at the electronic device 300. Examples of such data include instructions for any application or method operating on the electronic device 300, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 304 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

The power supply component 306 provides power to the various components of the electronic device 300. The power supply components 306 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 300.

The multimedia component 308 includes a screen between the electronic device 300 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may sense not only the boundary of a touch or slide action, but also the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 308 includes a front-facing camera and/or a rear-facing camera. When the electronic device 300 is in an operational mode, such as a shooting mode or a video mode, the front camera and/or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

The audio component 310 is configured to output and/or input audio signals. For example, the audio component 310 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 300 is in an operational mode, such as a call mode, a recording mode, and a voice information processing mode. The received audio signals may be further stored in the memory 304 or transmitted via the communication component 316. In some embodiments, audio component 310 further comprises a speaker for outputting audio signals.

The I/O interface 312 provides an interface between the processing component 302 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to, a home button, a volume button, an activate button, and a lock button.

The sensor assembly 314 includes one or more sensors for providing status assessment of various aspects of the electronic device 300. For example, the sensor assembly 314 may detect an on/off state of the electronic device 300, a relative positioning of the components, such as a display and keypad of the apparatus 300, the sensor assembly 314 may also detect a change in position of the electronic device 300 or a component of the electronic device 300, the presence or absence of a user's contact with the electronic device 300, an orientation or acceleration/deceleration of the electronic device 300, and a change in temperature of the electronic device 300. The sensor assembly 314 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. The sensor assembly 314 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 314 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 316 is configured to facilitate communication between the electronic device 300 and other devices, either wired or wireless. The electronic device 300 may access a wireless network based on a communication standard, such as WiFi,2G, or 3G, or a combination thereof. In one exemplary embodiment, the communication component 316 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 316 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on radio frequency information processing (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the electronic device 300 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for executing the methods described above.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 304, including instructions executable by processor 320 of electronic device 300 to perform the above-described method. For example, the non-transitory computer readable storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

A non-transitory computer readable storage medium, which when executed by a processor of an electronic device (server or terminal), enables the processor to perform the binary translation method shown in fig. 1.

It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.

The above detailed description of the binary translation method, the binary translation device and the electronic device provided by the present invention has been provided, and specific examples are used herein to illustrate the principles and the implementation of the present invention, and the above examples are only used to help understand the method and the core idea of the present invention, and meanwhile, to those skilled in the art, according to the idea of the present invention, there are changes in the specific implementation and the application scope, so the disclosure should not be construed as limiting the present invention.

Claims

1. A binary translation method applied to a binary translation system for translating a source program in a client into a target program in a host, the method comprising:

If the number of times of the jump is larger than a first preset threshold value, carrying out instruction rearrangement on the first jump address and the second jump address;

Wherein said instruction reordering of said first and second jump addresses comprises:

2. The method of claim 1, wherein the instruction reordering of the first and second jump addresses further comprises:

3. The method of claim 1, wherein counting the number of hops the first jump instruction jumps to the second jump address during execution of the first jump instruction comprises:

4. A method according to claim 3, characterized in that the method further comprises:

5. The method of claim 3, wherein after said instruction reordering of said first jump address and said second jump address, said method further comprises:

6. The method according to any one of claims 1 to 5, further comprising:

7. The method of any of claims 1 to 5, wherein prior to the fetching of the first jump instruction, the method further comprises:

8. The method of claim 7, wherein the splitting the source program based on the jump instruction results in at least one translation unit comprising:

searching and marking a jump instruction in a source program to be translated;

If the fourth jump instruction exists before the third jump instruction, extracting the third jump instruction from the source program, and extracting an instruction between the third jump instruction and the fourth jump instruction to obtain a translation unit;

9. The method of claim 7, wherein the method further comprises:

10. A processor for use in a binary translation system for translating a source program in a client to a target program in a host, the processor comprising:

The processing unit is used for counting the jump times of the first jump instruction to the second jump address in the process of executing the first jump instruction, and carrying out instruction rearrangement on the first jump address and the second jump address if the jump times are larger than a first preset threshold value;

Wherein, the processing unit is specifically configured to:

11. The processor of claim 10, wherein the processing unit is further specifically configured to:

12. An electronic device comprising a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to perform the binary translation method of any of claims 1-9 by one or more processors.

13. A readable storage medium, characterized in that instructions in the storage medium, when executed by a processor of an electronic device, enable the processor to perform the binary translation method of any one of claims 1 to 9.