CN114614816A - A phase-locked loop capable of fast locking - Google Patents

Abstract

The invention discloses a phase-locked loop capable of realizing quick locking, which comprises a waveform broadening phase frequency detector, a digital auxiliary phase detector, a charge pump, a filter, a VCO (voltage controlled oscillator) and a frequency divider, wherein the waveform broadening phase frequency detector is connected with the VCO; the invention realizes larger gain by widening the pulse width of UP or DN, and simultaneously adds new judgment on the basis of the traditional large and small bandwidth because a new locking mode is provided: whether phase error exceeds pi, whether filter structure when phase error exceeds pi is different, need not consider loop stability when increasing the electric current and realizing bigger bandwidth, thereby realize bigger electric current on original basis, the upper limit is higher, the gain is bigger, simultaneously because get into the phase place tracking stage in advance, accelerate the charging speed to the electric capacity, the settling time is accelerated, in addition, switching resistance can realize that the damping coefficient remains unchanged when switching the bandwidth, can not influence loop stability, the robustness is better, guarantee that the bandwidth is little, realize quick locking under the good performance's the condition.

Description

A phase-locked loop capable of fast locking

technical field

The present invention relates to the technical field of phase locked loops, in particular to a phase locked loop capable of realizing fast locking.

Background technique

Frequency synthesizers based on phase-locked loops (PLLs) are an important part in various applications, especially in communication systems, where frequency synthesizers need to have good phase noise, jitter, and spurious performance. This is an important design requirement. A phase-locked loop capable of fast locking is especially important in systems that require frequency hopping operation. A phase-locked loop is a second-order damping system. The settling time is determined by the time constant, which is inversely proportional to the loop bandwidth. As the loop bandwidth increases, the settling time decreases, but when the frequency is higher and the divider ratio is larger, increasing the bandwidth increases the in-band noise.

In the prior art, the locking process of the PLL is divided into two parts, one part is the frequency locking process, and the other part is the phase locking process. If the gain of the charge pump is increased during the frequency locking process, the gain of the charge pump is restored during the phase locking process. It is possible to reduce the time of the frequency locking process without affecting the bandwidth, thereby reducing the locking time. As shown in Figure 1, the circuit structure of a typical dual-loop PFD/CP mainly includes a coarse-tuned PFD/CP (phase frequency discriminator), a fine-tuned PFD/CP, a filter, a voltage-controlled oscillator (VCO), and a frequency divider. Among them, the coarse adjustment PFD/CP is used in the process of frequency locking, compares the phase of the reference signal and the frequency division signal, and converts the phase difference ratio into a current, and the fine adjustment PFD/CP is used in the phase locking process, and compares the reference signal and the division signal. The phase of the frequency signal, the phase difference ratio is converted into a current, the filter converts the current generated by the charge pump into the control voltage of the VCO, and at the same time filters out the high-frequency components on the control voltage to reduce the ripple, the VCO is controlled according to the filter generated. The frequency signal divider corresponding to the voltage generation converts the high frequency signal generated by the VCO into a low frequency signal.

The main idea of the above-mentioned typical dual-loop PFD/CP circuit structure is to use a coarse-tuned PFD/CP in the frequency locking process to increase the gain of the charge pump to increase the bandwidth and speed up the locking time, but this PFD/CP has a blind area. When the phase error is reduced to a certain value, it will not work. At this time, the fine-tuned PFD/CP starts to work until the phase error is reduced to zero. However, the circuit structure of the dual-loop PFD/CP is complex, and there are For two PFD/CPs, it is necessary to set the value of the blind zone reasonably, the design is cumbersome, and the stability during the locking process cannot be guaranteed, and the robustness is poor. The changes in parameters such as phase margin and damping coefficient also need to be considered, and the upper limit is low. , that is, the locking time that can be reduced is limited. Therefore, the present invention proposes a phase-locked loop capable of realizing fast locking to solve the problems existing in the prior art.

SUMMARY OF THE INVENTION

In view of the above problems, the purpose of the present invention is to propose a phase-locked loop capable of realizing fast locking, which solves the problem that the phase-locked loop in the prior art is complex in structure, cumbersome in design, and cannot guarantee the stability in the locking process, resulting in a relatively low robustness. Poor and limited lock time that can be reduced.

In order to achieve the purpose of the present invention, the present invention is realized through the following technical solutions: a phase-locked loop capable of realizing fast locking, comprising a waveform broadening frequency discriminator, a digital auxiliary phase discriminator, a charge pump, a filter, a VCO and a splitter frequency detector, the charge pump is a switchable charge pump, the filter is a switchable filter, the waveform broadening frequency discriminator and the digital auxiliary phase discriminator receive the reference signal and the frequency division signal from the frequency divider , the digital auxiliary phase detector generates a MODE signal to change the current size of the charge pump and the filter to realize bandwidth switching, and the waveform broadening and frequency detector phase detector increases the gain of the charge pump by broadening the waveform of the UP signal or the DN signal, and at the same time The SW1 signal is generated and sent to the filter to realize filter switching. The filter changes the locking process of the loop and makes the loop enter the phase locking process in advance, while ensuring that the damping coefficient remains unchanged when switching the filter. The output end is connected to the input end of the VCO, and the output end of the VCO is connected to the input end of the frequency divider.

A further improvement lies in: the waveform broadening and frequency discriminator phase discriminator consists of four parts, namely: phase discriminating part, judging leading and lagging part, judging whether the phase error exceeds π part and waveform expanding part.

A further improvement is that: the phase detection part uses a three-state gate frequency discriminator to compare the rising edges of the VREF signal and the VDIV signal to generate corresponding QA and QB signals.

A further improvement lies in: the judging leading and trailing parts are used to judge whether VREF is leading or trailing, using QB to sample QA, if it is high, the VREF signal leads, if it is low, the VDIV signal leads, and the MODE signal is enabled. , if the MODE signal is high, it will be turned on, and if the MODE signal is low, it will output a low level.

A further improvement is: the part of judging whether the phase error exceeds π is used to judge whether the difference between the VREF signal and the VDIV signal exceeds π, output the SW1 signal at the same time, and use the QB to sample the VREF signal. If the switch signal is high, it exceeds π, otherwise not exceed π.

A further improvement is: the digital auxiliary phase detector is used to generate a MODE signal for switching the size and bandwidth, specifically: setting a phase threshold τ, if the phase difference between the VREF signal and the VDIV signal exceeds τ, then the MODE signal is a high level. level, otherwise it is low level.

A further improvement lies in: the charge pump adopts a source-level switch op-amp charge pump, and the current switching is realized by a proportional current mirror and the MODEB control signal, wherein the large current is 4 times the small current, and when the MODEB control signal is high, the two Two current mirrors work at the same time, when the MODEB signal is low, only one current mirror works.

A further improvement lies in: the filter adopts a first-order/second-order filter, and uses MODEB as a control signal to switch the size of the filter resistance, when the loop bandwidth is switched from large to small, the damping coefficient remains unchanged, and at the same time The SW1 signal is used to switch between the first-order filter and the second-order filter.

The beneficial effects of the present invention are as follows: the phase-locked loop structure of the present invention is simple and clear, including a waveform broadening frequency discriminator, a digital auxiliary phase discriminator, a charge pump, a filter, a VCO and a frequency divider. The pulse width achieves greater gain. At the same time, a new locking method is proposed, and a new judgment is added on the basis of the traditional size bandwidth: whether the phase error exceeds π, and the filter structure when the phase error exceeds π Different, when increasing the current to achieve a larger bandwidth, the loop stability does not need to be considered, so that a larger current can be achieved on the original basis, the upper limit is higher, and the gain is larger. The charging speed is faster and the settling time is faster. In addition, switching the resistance while switching the bandwidth can keep the damping coefficient unchanged, without affecting the loop stability, and the robustness is better. Compared with the traditional circuit structure, the bandwidth and phase are broken. The trade-off between noise and lock time, so as to achieve fast lock with small bandwidth and good performance.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a schematic diagram of the circuit structure of a dual-loop PFD/CP in the technical background of the present invention;

2 is a schematic structural diagram of a phase-locked loop circuit in an embodiment of the present invention;

3 is a schematic diagram of the circuit principle of a waveform broadening frequency and phase detector circuit in an embodiment of the present invention;

4 is a schematic diagram of an output waveform of a waveform broadening frequency and phase detector circuit in an embodiment of the present invention;

5 is a schematic diagram of the circuit principle of a digital auxiliary phase detector in an embodiment of the present invention;

6 is a schematic diagram of an output waveform of a digital auxiliary phase detector circuit in an embodiment of the present invention;

7 is a schematic structural diagram of a switchable charge pump circuit in an embodiment of the present invention;

8 is a schematic structural diagram of a switchable filter circuit in an embodiment of the present invention;

9 is a schematic diagram of the locking time of the phase-locked loop capable of realizing fast locking in an embodiment of the present invention;

FIG. 10 is a schematic diagram of the locking time of a conventional phase-locked loop in an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Referring to FIG. 2 , this embodiment provides a phase-locked loop capable of realizing fast locking, including a waveform broadening frequency discriminator, a digital auxiliary phase discriminator, a charge pump, a filter, a VCO and a frequency divider. The charge pump is The switchable charge pump, the filter is a switchable filter, the waveform broadening frequency discriminator and the digital auxiliary phase discriminator receive the reference signal and the frequency-divided signal from the frequency divider, and the digital auxiliary phase discriminator generates the MODE signal to change the charge pump The current size and filter can achieve bandwidth switching. When switching the bandwidth, switching the resistance can keep the damping coefficient unchanged, without affecting the loop stability, and the robustness is better. The waveform of the DN signal is broadened to increase the gain of the charge pump. A larger gain is achieved by broadening the pulse width of the UP or DN. At the same time, the SW1 signal is generated and sent to the filter to achieve filter switching. The filter changes the locking process of the loop and makes The loop enters the phase locking process in advance, and at the same time ensures that the damping coefficient remains unchanged when switching the filter. Due to the early entry into the phase locking phase, the charging speed of the capacitor is accelerated, and the settling time is accelerated. The output of the filter is connected to the input of the VCO. The output end of the VCO is connected to the input end of the frequency divider. Compared with the traditional circuit structure, it breaks the trade-off between bandwidth, phase noise and locking time, so as to achieve fast locking while ensuring small bandwidth and good performance. It is simple and clear, can ensure the stability in the locking process, and has high robustness.

Referring to Figure 3, the waveform broadening and frequency discriminator phase discriminator is composed of four parts, namely: phase discriminator, judging leading and lagging parts, judging whether the phase error exceeds π, and waveform expansion part; the phase discriminator uses three-state gate discriminator The frequency phase detector compares the rising edge of the VREF signal and the VDIV signal to generate the corresponding QA and QB signals; the leading and trailing part is used to judge whether the VREF is leading or trailing, using QB to sample QA, if it is high, the VREF signal Leading, if it is low, the VDIV signal is leading. It is enabled for the MODE signal. If the MODE signal is high, it will be turned on. If the MODE signal is low, it will output a low level; the part to judge whether the phase error exceeds π is used to judge the VREF signal and the Whether the VDIV signal exceeds π, output the SW1 signal at the same time, use QB to sample the VREF signal, if the SW1 signal is high, it will exceed π, otherwise it will not exceed π; in the waveform expansion part, when SW1 is high, FORMER is high. Usually, when VREF is ahead and the phase error exceeds π, the XOR operation of VREF and VDIV is performed and then the OR operation is performed with the QA signal. At this time, the QUP signal is always at a high level, thus achieving the purpose of waveform expansion and speeding up. The frequency locking process, and when SW1 is low, it means that the phase error does not exceed π at this time, the QUP signal is the QA signal, and no waveform expansion is performed, which does not affect the phase locking process. The waveform is shown in Figure 4.

On the basis of the traditional size bandwidth, a new judgment is added: whether the phase error exceeds π, the filter structure is different when the phase error exceeds π, and the loop stability does not need to be considered when increasing the current to achieve a larger bandwidth, thus On the basis of the original, a larger current is achieved, the upper limit is higher, and the gain is larger.

As shown in Figure 5 and Figure 6, the digital auxiliary phase detector is used to generate the MODE signal that switches the bandwidth of the large and small, and a phase threshold τ is set. If the phase difference between the VREF signal and the VDIV signal exceeds τ, the MODE signal is high. Level, otherwise it is low level, the specific implementation is: QUP and QDN do the AND operation, after the delay of τ, use the RESET signal to sample and output the MODE signal.

As shown in Figure 7, the charge pump adopts the source-level switch op-amp charge pump, and the current switching is realized by a proportional current mirror and the MODEB control signal. The large current is 4 times the small current. When the MODEB control signal is high, the two Two current mirrors work at the same time, when the MODEB signal is low, only one current mirror works.

The filter uses a first-order/second-order filter, and uses MODEB as a control signal to switch the size of the filter resistance. When the loop bandwidth is switched from large to small, the damping coefficient remains unchanged, and the SW1 signal is used to perform a The switching between the first-order filter and the second-order filter is shown in Figure 8. When SW is low, it means that the phase error between VREF and VDIV exceeds π. At this time, only the capacitor C1 exists, and it is quickly When charging, Vcont increases rapidly, and the frequency increases rapidly. When SW is low, it means that the phase error between VREF and VDIV does not exceed π. At this time, the branch connected in series with R and C2 also starts to work, and the frequency is pulled down for Phase tracking process, which loops several times until the voltages on C1 and C2 are equal.

The invention breaks the locking process of the traditional PLL, and proposes a new locking method to further reduce the locking time on the basis of the bandwidth switching PLL, and achieve greater gain by extending the pulse width of UP or DN. A new locking method adds a new judgment on the basis of the original size and bandwidth: whether the phase error exceeds π, the filter structure is different when the phase error exceeds π, and it is not necessary to increase the current to achieve a larger bandwidth. Considering the loop stability, a larger current, a higher upper limit, and a larger gain can be achieved on the basis of the original. At the same time, due to the early entry into the phase tracking stage, the charging speed of the capacitor C2 is accelerated, and the settling time is accelerated. In addition, the switching bandwidth is At the same time, switching the resistance can keep the damping coefficient unchanged, without affecting the loop stability, and the robustness is better.

Referring to FIG. 9 and FIG. 10 , the simulation time of the phase-locked loop that can realize fast locking provided by this embodiment is compared with the traditional phase-locked loop. time, Fig. 8 shows the locking time of the traditional phase-locked loop, according to the comparison of Fig. 7 and Fig. 8, the phase-locked loop capable of realizing fast locking of this embodiment is compared with the traditional lock time compared with the traditional PLL reduced by two-thirds.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the scope of the present invention. within the scope of protection.

Claims (8)

1. a phase-locked loop capable of realizing fast locking, is characterized in that: comprise waveform broadening frequency discriminator, digital auxiliary phase discriminator, charge pump, filter, VCO and frequency divider, and the charge pump is a The charge pump is switched, the filter is a switchable filter, the waveform broadening frequency discriminator and the digital auxiliary phase discriminator receive the reference signal and the frequency-divided signal from the frequency divider, and the digital auxiliary phase discriminator generates The MODE signal changes the current size of the charge pump and the filter to achieve bandwidth switching. The waveform broadening frequency discriminator increases the gain of the charge pump by expanding the waveform of the UP signal or the DN signal, and generates the SW1 signal and sends it to the filter. Filter switching, the filter changes the locking process of the loop and makes the loop enter the phase locking process in advance, while ensuring that the damping coefficient remains unchanged when switching the filter, the output of the filter is connected to the input of the VCO, The output end of the VCO is connected to the input end of the frequency divider. 2. a kind of phase-locked loop capable of realizing fast locking according to claim 1, it is characterized in that: described waveform broadening frequency discriminator phase detector is made up of four parts, respectively: phase detection part, judge ahead and behind part, judging whether the phase error exceeds the π part and the waveform extension part. 3. a kind of phase-locked loop capable of realizing fast locking according to claim 2, is characterized in that: described phase detection part uses tri-state gate frequency discriminator phase discriminator, compares the rising edge of VREF signal and VDIV signal, produces Corresponding QA and QB signals. 4. a kind of phase-locked loop capable of realizing fast locking according to claim 2, is characterized in that: described judging leading and lagging part is used for judging that VREF leads or lagging behind, utilizes QB to sample QA, if it is high level The VREF signal is advanced, if it is low, the VDIV signal is advanced, and it is enabled for the MODE signal. If the MODE signal is high, it is turned on, and if the MODE signal is low, it outputs a low level. 5. a kind of phase-locked loop capable of realizing fast locking according to claim 2, it is characterized in that: described judging whether the phase error exceeds π part is used for judging whether between VREF signal and VDIV signal exceeds π, output SW1 simultaneously Signal, use QB to sample VREF signal, if the switch signal is high, it will exceed π, otherwise it will not exceed π. 6. a kind of phase-locked loop capable of realizing fast locking according to claim 1, is characterized in that: described digital auxiliary phase detector is used to generate the MODE signal of switching the size bandwidth, specifically: set a phase threshold τ, If the phase difference between the VREF signal and the VDIV signal exceeds τ, the MODE signal is high, otherwise it is low. 7. A phase-locked loop capable of realizing fast locking according to claim 1, wherein the charge pump adopts a source-level switch op-amp charge pump, and the current switching is realized by a proportional current mirror and a MODEB control signal, The large current is 4 times that of the small current. When the MODEB control signal is at a high level, two current mirrors work at the same time. When the MODEB signal is at a low level, only one current mirror works. 8. a kind of phase locked loop capable of realizing fast locking according to claim 1, is characterized in that: described filter adopts first-order/second-order filter, and adopts MODEB as control signal to switch the size of filter resistance , when the loop bandwidth is switched from large to small, the damping coefficient remains unchanged, and the SW1 signal is used to switch between the first-order filter and the second-order filter.

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