CN114584247B - Time synchronization method, detection device and system - Google Patents
Time synchronization method, detection device and system Download PDFInfo
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- CN114584247B CN114584247B CN202210211810.6A CN202210211810A CN114584247B CN 114584247 B CN114584247 B CN 114584247B CN 202210211810 A CN202210211810 A CN 202210211810A CN 114584247 B CN114584247 B CN 114584247B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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Abstract
The application provides a time synchronization method, detection equipment and a system, wherein the method comprises the steps of generating a first time synchronization message, sending the first time synchronization message to a node at the upper level of a current level node, wherein the first time synchronization message comprises the real-time of the current level node, receiving a second time synchronization message sent by the upper level node, wherein the second time synchronization message comprises the real-time of the upper level node, and determining whether the current level node is successfully synchronized according to the difference value between the real-time of the current level node and the real-time of the upper level node.
Description
Technical Field
The present application relates to the field of time synchronization technology, and in particular, to a time synchronization method, a detection device, a system, a computer readable storage medium, a processor, and a vehicle.
Background
In time synchronization of each node in a complex topological network, if one node fails in synchronization, the prior art is difficult to detect the position of the node with failed synchronization, and the time synchronization condition of each node in the time synchronization detection equipment of staff cannot be reminded, so that the problem of low practicability of the time synchronization detection equipment is caused.
Disclosure of Invention
The application mainly aims to provide a time synchronization method, detection equipment, a system, a computer readable storage medium, a processor and a vehicle, so as to solve the problem that the position of a node failing to synchronize in a topological network is difficult to detect in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided a time synchronization method, which includes generating a first time synchronization message and transmitting the first time synchronization message to a previous node of a current node, where the first time synchronization message includes a real time of the current node, receiving a second time synchronization message transmitted by the previous node, where the second time synchronization message includes a real time of the previous node, and determining whether the current node is successfully synchronized according to a difference between the real time of the current node and the real time of the previous node.
Further, determining whether the current level node is successful in synchronization according to the difference between the real-time of the current level node and the real-time of the previous level node includes determining that the current level node is successful in synchronization if the difference between the real-time of the current level node and the real-time of the previous level node is less than a predetermined value, and determining that the current level node is failed in synchronization if the difference between the real-time of the current level node and the real-time of the previous level node is greater than or equal to the predetermined value.
Further, after determining whether the current level node is successful in synchronization according to the difference between the real-time of the current level node and the real-time of the previous level node, the method further comprises generating a completion signal, sending the completion signal to a display module, and controlling the display module to display the synchronization result of the current level node.
According to another aspect of the present application, there is provided a time synchronization detection apparatus, including a control chip for performing the above-described time synchronization method, and an ethernet interface for electrically connecting with a current level node to be detected in a topology network.
Further, the time synchronization detection device further comprises a selection switch, the selection switch is electrically connected with the control chip, the real-time of the current stage node is determined according to a software time stamp when the selection switch is in a first state, and the real-time of the current stage node is determined according to a hardware time stamp when the selection switch is in a second state.
Further, the time synchronization detection device further comprises a display module, and the display module is electrically connected with the control chip and is used for displaying the synchronization result of the current-stage node.
The display module comprises a first display module, a second display module and a third display module, wherein the first display module is electrically connected with the control chip, the current-stage node synchronization failure is represented under the condition that the first display module is in a first state, the second display module is electrically connected with the control chip, the current-stage node synchronization is represented under the condition that the second display module is in the first state, the third display module is electrically connected with the control chip, and the current-stage node synchronization is represented to be successful under the condition that the second display module is in the first state.
Further, the first display module is a first LED, the second display module is a second LED, and the third display module is a third LED.
The time synchronization detection equipment further comprises a power supply module and a voltage converter, wherein the power supply module is electrically connected with the control chip and used for converting alternating current signals into first direct current signals, the voltage converter is electrically connected with the power supply module and the control chip and used for converting the first direct current signals into second direct current signals, and the voltage values of the first direct current signals and the second direct current signals are different.
Further, the time synchronization detection device further comprises a storage chip, wherein the storage chip is electrically connected with the control chip and is used for storing a difference value between the real-time of the current level node and the real-time of the previous level node of the current level node.
Further, the time synchronization detection device further comprises a program programming interface, and the program programming interface is electrically connected with the control chip and is used for being electrically connected with the computer.
According to another aspect of the present application, there is also provided a time synchronization system including any one of the time synchronization detecting apparatuses described above and a computer electrically connected to the time synchronization detecting apparatus.
According to another aspect of the present application, there is also provided a computer readable storage medium, where the computer readable storage medium includes a stored program, where the program when executed controls a device in which the computer readable storage medium is located to perform any one of the above-described methods for time synchronization.
According to another aspect of the present application, there is also provided a processor for running a program, wherein the program runs to perform any one of the above-described time synchronization methods.
According to another aspect of the present application there is also provided a vehicle comprising one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs comprising a method for performing any of the above described time synchronisation.
By applying the technical scheme of the application, the difference value between the real-time of the current level node and the real-time of the previous level node is obtained through the real-time of the current level node and the real-time of the previous level node, so that whether the current level node is successfully synchronized or not is determined, and the time synchronization state of any node in the topology network can be detected, thereby solving the problem that the position of the node which fails to be synchronized in the topology network is difficult to detect in the prior art.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
FIG. 1 shows a flow chart of a method of time synchronization according to an embodiment of the application;
FIG. 2 shows a schematic diagram of an apparatus for time synchronization according to an embodiment of the application;
FIG. 3 shows a schematic diagram of a time synchronization detecting device according to an embodiment of the application;
fig. 4 is a flowchart of a time synchronization detecting apparatus implementing time synchronization according to an embodiment of the present application.
Wherein the above figures include the following reference numerals:
100. The device comprises a control chip, an Ethernet interface, a selection switch, a display module, a power module, a voltage converter, a storage chip and a program programming interface, wherein the control chip is 200, the Ethernet interface is 300, the selection switch is 400, the display module is 500, the power module is 600, the voltage converter is 700, and the storage chip is 800.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described above in the background art, in time synchronization of each node in a complex topology network, if a certain node fails to synchronize, the prior art cannot detect the position of the node that fails to synchronize, and cannot remind the staff of time synchronization of each node in the time synchronization detection device, so that the problem of low practicability of the time synchronization detection device is caused.
According to an embodiment of the present application, a method of time synchronization is provided.
Fig. 1 is a flow chart of a method of time synchronization according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
Step S101, generating a first time synchronization message, and sending the first time synchronization message to a node of a previous stage of a current stage node, wherein the first time synchronization message comprises the real-time of the current stage node;
step S102, receiving a second time synchronization message sent by the previous node, wherein the second time synchronization message comprises the real-time of the previous node;
Step S103, determining whether the current level node is successful in synchronization according to the difference between the real-time of the current level node and the real-time of the previous level node.
In the step, the difference value between the real-time of the current level node and the real-time of the previous level node is obtained through the real-time of the current level node and the real-time of the previous level node, so that whether the current level node is successfully synchronized or not is determined, the time synchronization state of any node in the topology network can be detected, and the problem that the position of the node which fails to be synchronized in the topology network is difficult to detect in the prior art is solved.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order other than that illustrated herein.
In one embodiment of the present application, determining whether the synchronization of the current level node is successful according to a difference between the real time of the current level node and the real time of the previous level node includes determining that the synchronization of the current level node is successful if the difference between the real time of the current level node and the real time of the previous level node is less than a predetermined value, and determining that the synchronization of the current level node is failed if the difference between the real time of the current level node and the real time of the previous level node is greater than or equal to the predetermined value, so that the synchronization of the current level node can be rapidly determined. Specifically, the predetermined value may be set to 2 μs, 5 μs, 10 μs, or the like.
In one embodiment of the present application, after determining whether the synchronization of the current node is successful according to a difference between the real-time of the current node and the real-time of the previous node, the method further includes generating a completion signal, and sending the completion signal to a display module, so as to control the display module to display the synchronization result of the current node, and enable a worker to learn the synchronization result of the current node.
The embodiment of the application also provides a time synchronization device, and the time synchronization device of the embodiment of the application can be used for executing the method for time synchronization provided by the embodiment of the application. The following describes a time synchronization apparatus provided by an embodiment of the present application.
Fig. 2 is a schematic diagram of an apparatus for time synchronization according to an embodiment of the present application. As shown in fig. 2, the device comprises a processing unit 10, a receiving unit 20 and a determining unit 30, wherein the processing unit 10 is configured to generate a first time synchronization message and send the first time synchronization message to a previous node of a current node, the first time synchronization message includes a real-time of the current node, the receiving unit 20 is configured to receive a second time synchronization message sent by the previous node, the second time synchronization message includes a real-time of the previous node, and the determining unit 30 is configured to determine whether the current node is successful or not according to a difference between the real-time of the current node and the real-time of the previous node.
In the device, the difference value between the real-time of the current level node and the real-time of the previous level node is obtained through the determining unit, so that whether the current level node is successfully synchronized or not is determined, the time synchronization state of any node in the topology network can be detected, and the problem that the position of the node which fails to synchronize in the topology network is difficult to detect in the prior art is solved.
In one embodiment of the present application, the determining unit includes a first determining module and a second determining module, where the first determining module is configured to determine that the synchronization of the current level node is successful when a difference between a real time of the current level node and a real time of the previous level node is smaller than a predetermined value, and the second determining module is configured to determine that the synchronization of the current level node is failed when a difference between the real time of the current level node and the real time of the previous level node is greater than or equal to the predetermined value, so as to quickly determine that the synchronization of the current level node is successful.
In an embodiment of the present application, the apparatus further includes a control unit, where the control unit is configured to generate a completion signal, send the completion signal to a display module, and control the display module to display a synchronization result of the current level node, so that a worker can learn the synchronization result of the current level node.
The embodiment of the application also provides a time synchronization detection device, and fig. 3 is a schematic diagram of the time synchronization detection device according to the embodiment of the application. As shown in fig. 3, the time synchronization detection device includes a control chip 100 and an ethernet interface 200, where the control chip 100 is configured to perform the time synchronization method, and the ethernet interface 200 is configured to electrically connect with a current node to be detected in a topology network, so as to solve a problem that it is difficult to detect a location of a node that fails to synchronize in the topology network in the prior art.
Specifically, the ethernet interface may be a 1000M standard ethernet interface or a 1000Base-T1 onboard ethernet interface.
Fig. 4 is a flowchart of implementing time synchronization by a time synchronization detection device according to an embodiment of the present application, where, as shown in fig. 4, the time synchronization detection device is electrically connected to a current node to be detected in a topology network, and sends a first time synchronization packet to a previous node of the current node, where the first time synchronization packet includes a real-time of the current node, and then the previous node sends a second time synchronization packet to the time synchronization detection device, where the second time synchronization packet includes a real-time of the previous node, and the time synchronization detection device determines whether the current node is successful according to a difference between the real-time of the current node and the real-time of the previous node.
In an embodiment of the present application, as shown in fig. 3, the time synchronization detecting apparatus further includes a selection switch 300, where the selection switch 300 is electrically connected to the control chip 100, and when the selection switch 300 is in a first state, the real-time of the current stage node is determined according to a software timestamp, and when the selection switch 300 is in a second state, the real-time of the current stage node is determined according to a hardware timestamp, and preferably, the selection switch 300 is a dial switch, so that flexibility of the time synchronization detecting apparatus is improved. Specifically, the selection switch 300 is in a first state, that is, the active part of the selection switch is located at a first position (for example, left side), the selection switch 300 is in a second state, that is, the active part of the selection switch is located at a second position (for example, right side), specifically, the software timestamp refers to a system time acquired through the clock chip, the hardware timestamp refers to a corresponding time acquired through the bottom physical chip, the hardware timestamp is more accurate than the software timestamp, and the adaptability of the software timestamp is wider, wherein the bottom physical chip is commonly used in life and combined with the crystal head network cable and the crystal head socket to form a physical layer, the physical layer defines a transmission medium, a transmission speed, a data coding mode and a collision detection mechanism used by the ethernet, and the bottom physical chip is an entity realizing the function of the physical layer.
In an embodiment of the present application, as shown in fig. 3, the time synchronization detecting apparatus further includes a display module 400, where the display module 400 is electrically connected to the control chip 100, and is configured to display a synchronization result of the current level node, so that a worker can easily understand the synchronization result of the current level node.
In one embodiment of the present application, the display module includes a first display module, a second display module and a third display module, where the first display module is electrically connected to the control chip, and indicates that synchronization of the current node fails when the first display module is in a first state, the second display module is electrically connected to the control chip, and indicates that synchronization of the current node is being performed when the second display module is in the first state, and the third display module is electrically connected to the control chip, and indicates that synchronization of the current node is successful when the second display module is in the first state, so as to display synchronization of the current node when the first state is in a light-emitting state.
In an embodiment of the present application, the first display module is a first LED, the second display module is a second LED, and the third display module is a third LED, so as to display synchronization of the current level node, for example, the first LED emits red light when in a first state, which is used to indicate that synchronization of the current level node fails, the second LED emits yellow light when in the first state, which is used to indicate that synchronization of the current level node is being performed, and the third LED emits green light when in the first state, which is used to indicate that synchronization of the current level node succeeds.
In one embodiment of the present application, as shown in fig. 3, the time synchronization detecting apparatus further includes a power module 500 and a voltage converter 600, wherein the power module 500 is electrically connected to the control chip 100 and is used for converting an ac electrical signal into a first dc electrical signal, the voltage converter 600 is electrically connected to the power module 500 and the control chip 100 and is used for converting the first dc electrical signal into a second dc electrical signal, and the voltage value of the first dc electrical signal is different from the voltage value of the second dc electrical signal, so that the power requirement of the time synchronization detecting apparatus is met, and the voltage converter 600 can boost or buck the voltage output by the power module 500.
In one embodiment of the present application, as shown in fig. 3, the time synchronization detecting apparatus further includes a memory chip 700, and the memory chip 700 is electrically connected to the control chip 100, for storing a difference between a real time of the current level node and a real time of a previous level node of the current level node, thereby satisfying a storage requirement of the difference between the real time of the current level node and the real time of the previous level node, and the memory chip 700 is further capable of storing the real time of the current level node, the real time of the previous level node, and a program for controlling the control chip.
In an embodiment of the present application, as shown in fig. 3, the time synchronization detecting apparatus further includes a programming interface 800, where the programming interface 800 is electrically connected to the control chip 100 and is used for being electrically connected to a computer, so as to meet a requirement of data transmission of the control chip 100, where the data may be a difference between a real-time of the current level node and a real-time of a previous level node of the current level node. Specifically, the program programming interface may be JTAG, and the program in the computer is programmed into the control chip of the time synchronization detection device through the program programming interface, so that the control chip realizes the corresponding function.
In one embodiment of the present application, the control chip converts the real-time of the current stage node, the real-time of the previous stage node, and the difference between the real-time of the current stage node and the real-time of the previous stage node into a first PPS pulse signal, a second PPS pulse signal, and a third PPS pulse signal, respectively, so that a worker can electrically connect a detection probe of an oscilloscope to the time synchronization detection device and obtain the first PPS pulse signal, the second PPS pulse signal, and the third PPS pulse signal.
The embodiment of the application also provides a time synchronization system, which comprises any one of the time synchronization detection equipment and a computer, wherein the computer is electrically connected with the time synchronization detection equipment.
The embodiment of the application also provides a vehicle, which comprises one or more processors, a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs comprise a method for executing any of the time synchronization.
It should be noted that the above electrical connection may be a direct electrical connection or an indirect electrical connection, where a direct electrical connection refers to a direct connection between two devices, and an indirect electrical connection refers to a connection between a and B, where other devices like capacitors and resistors are connected.
The time synchronization detecting apparatus includes a processor and a memory, the processing unit, the receiving unit, the determining unit, and the like are stored as program units in the memory, and the processor executes the program units stored in the memory to realize the corresponding functions.
The processor includes a kernel, and the kernel fetches the corresponding program unit from the memory. The kernel can be provided with one or more than one kernel, and the problem that the prior art is difficult to detect the position of the node with the synchronization failure in the topological network is solved by adjusting the kernel parameters.
The memory may include volatile memory, random Access Memory (RAM), and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM), among other forms in computer readable media, the memory including at least one memory chip.
The embodiment of the invention provides a computer readable storage medium, which comprises a stored program, wherein the program is used for controlling a device where the computer readable storage medium is located to execute the time synchronization method.
The embodiment of the invention provides a processor, which is used for running a program, wherein the method for time synchronization is executed when the program runs.
The embodiment of the invention provides equipment, which comprises a processor, a memory and a program stored in the memory and capable of running on the processor, wherein the processor at least realizes the following steps when executing the program, namely, a first time synchronization message is generated and sent to a previous-stage node of a current-stage node, the first time synchronization message comprises the real-time of the current-stage node, a second time synchronization message sent by the previous-stage node is received, the second time synchronization message comprises the real-time of the previous-stage node, and whether the current-stage node is successfully synchronized or not is determined according to the difference value between the real-time of the current-stage node and the real-time of the previous-stage node. The device herein may be a server, PC, PAD, cell phone, etc.
The application also provides a computer program product which is suitable for executing a program initialized with at least the following method steps when being executed on data processing equipment, wherein the program is used for generating a first time synchronization message and sending the first time synchronization message to a previous node of a current node, the first time synchronization message comprises the real-time of the current node, receiving a second time synchronization message sent by the previous node, the second time synchronization message comprises the real-time of the previous node, and determining whether the current node is successfully synchronized according to the difference value between the real-time of the current node and the real-time of the previous node.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, etc., such as Read Only Memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) According to the time synchronization method, the difference value between the real-time of the current level node and the real-time of the previous level node is obtained through the real-time of the current level node and the real-time of the previous level node, whether the current level node is successful in synchronization or not is further determined, and the time synchronization state of any node in the topology network can be detected, so that the problem that the position of the node which fails in synchronization in the topology network is difficult to detect in the prior art is solved.
2) According to the time synchronization detection device, the control chip is used for executing the time synchronization method, the Ethernet interface is used for being electrically connected with the current-stage node to be detected in the topology network, and the problem that the position of the node failing to synchronize in the topology network is difficult to detect in the prior art is solved.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (7)
1. A time synchronization detection device is characterized by comprising a control chip and an Ethernet interface,
The control chip is used for generating a first time synchronization message and transmitting the first time synchronization message to a previous stage node of a current stage node, wherein the first time synchronization message comprises real-time of the current stage node, receiving a second time synchronization message transmitted by the previous stage node, and the second time synchronization message comprises real-time of the previous stage node, and determining whether the current stage node is successfully synchronized according to a difference value between the real-time of the current stage node and the real-time of the previous stage node;
Determining whether the current level node is successful in synchronization according to the difference value between the real-time of the current level node and the real-time of the previous level node, wherein the determining that the current level node is successful in synchronization comprises determining that the current level node is successful in synchronization when the difference value between the real-time of the current level node and the real-time of the previous level node is smaller than a preset value, and determining that the current level node is failed in synchronization when the difference value between the real-time of the current level node and the real-time of the previous level node is greater than or equal to the preset value;
The control chip is also used for determining whether the current level node is successful in synchronization or not according to the difference value between the real-time of the current level node and the real-time of the previous level node, generating a completion signal, sending the completion signal to a display module, and controlling the display module to display the synchronization result of the current level node;
The Ethernet interface is used for being electrically connected with the current-stage node to be detected in the topology network;
The time synchronization detecting apparatus further includes:
The selection switch is electrically connected with the control chip, the real-time of the current stage node is determined according to the software time stamp when the selection switch is in a first state, and the real-time of the current stage node is determined according to the hardware time stamp when the selection switch is in a second state;
The time synchronization detecting apparatus further includes:
And the display module is electrically connected with the control chip and used for displaying the synchronization result of the current-stage node.
2. The time synchronization detecting apparatus according to claim 1, wherein the display module includes:
The first display module is electrically connected with the control chip and is used for representing that the synchronization of the current-stage node fails under the condition that the first display module is in a first state;
the second display module is electrically connected with the control chip and is used for representing that the current-stage node is in synchronization under the condition that the second display module is in a first state;
And the third display module is electrically connected with the control chip and is used for representing that the synchronization of the current-stage node is successful under the condition that the second display module is in the first state.
3. The time synchronization detecting apparatus according to claim 2, wherein the first display module is a first LED, the second display module is a second LED, and the third display module is a third LED.
4. A time synchronization detecting apparatus according to any one of claims 1 to 3, characterized in that the time synchronization detecting apparatus further comprises:
The power supply module is electrically connected with the control chip and used for converting the alternating current signal into a first direct current signal;
And the voltage converter is respectively and electrically connected with the power supply module and the control chip and is used for converting the first direct current signal into a second direct current signal, and the voltage value of the first direct current signal is different from the voltage value of the second direct current signal.
5. A time synchronization detecting apparatus according to any one of claims 1 to 3, characterized in that the time synchronization detecting apparatus further comprises:
And the storage chip is electrically connected with the control chip and is used for storing the difference value between the real-time of the current level node and the real-time of the previous level node of the current level node.
6. A time synchronization detecting apparatus according to any one of claims 1 to 3, characterized in that the time synchronization detecting apparatus further comprises:
and the program programming interface is electrically connected with the control chip and is used for being electrically connected with a computer.
7. A time synchronization system, characterized in that it comprises the time synchronization detecting device according to any one of claims 1 to 3 and a computer electrically connected to the time synchronization detecting device.
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| CN112838903A (en) * | 2020-12-31 | 2021-05-25 | 广东大普通信技术有限公司 | Clock synchronization method, equipment and storage medium |
| CN113507337A (en) * | 2021-07-21 | 2021-10-15 | 中国第一汽车股份有限公司 | Method, device, medium and equipment for determining clock synchronization precision |
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| CN108599888A (en) * | 2018-05-09 | 2018-09-28 | 西安电子科技大学 | A kind of distributed network clock synchronizing system |
| CN110620629A (en) * | 2018-06-19 | 2019-12-27 | 佛山市顺德区美的电热电器制造有限公司 | Clock synchronization method, equipment and computer storage medium |
| CN111385048B (en) * | 2018-12-29 | 2023-06-30 | 中兴通讯股份有限公司 | Time synchronization method and system |
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