CN114551631B - A back-illuminated silicon-based single-photon avalanche diode structure and photodetector - Google Patents
A back-illuminated silicon-based single-photon avalanche diode structure and photodetector Download PDFInfo
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Abstract
The invention discloses a back-illuminated silicon-based single photon avalanche diode structure and a photoelectric detector, wherein the diode structure comprises a P-type epitaxial layer and a wiring layer, a plurality of isolation structures, an electrode protection ring, a plurality of light source induction areas and a P-well protection ring, wherein each isolation structure comprises a shallow groove isolation layer, an isolation N well and a deep groove isolation layer which are stacked in the P-type epitaxial layer, the electrode protection ring is arranged in the wiring layer and close to the shallow groove isolation layer, each light source induction area is distributed between the adjacent isolation structures at intervals, each light source induction area comprises an active P+ layer, an active area P well, a deep N well and an N-type buried layer which are stacked, the P-well protection ring is arranged on two sides of the active P+ layer and the active area P well, an anode electrode is arranged in the wiring layer below the active P+ layer, a reflecting metal plate is arranged in the wiring layer opposite to the active P+ layer, the sharing cathode comprises an electrode N well and is arranged in the P-type epitaxial layer and is connected with the deep N well, and the cathode electrode is arranged in the wiring layer close to the electrode N well. The invention can improve the detection efficiency.
Description
Technical Field
The invention belongs to the technical field of microelectronic photoelectric devices, and particularly relates to a back-illuminated silicon-based single photon avalanche diode structure and a photoelectric detector.
Background
Avalanche diodes (Single Photon Avalanche Diode, SPADs for short) are receiving increasing attention due to their high sensitivity at the single photon level and high resolution exceeding 100 ps. More recently, SPADs fabricated using complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) technology have been used in various fields such as fluorescence lifetime imaging microscopy, time-gated raman spectroscopy, radiation thermometry, and photodetectors and range radars. In these applications, high sensitivity, high resolution are necessary, and thus SPADs with high packing efficiency and high detection efficiency are receiving a great deal of attention. The existing SPAD adopts a certain pixel array to realize the detection effect of the SPAD.
However, since the large pixel array is limited by the device performance, the existing SPAD detection efficiency is poor, and a high dark count rate exists.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a back-illuminated silicon-based single photon avalanche diode structure and a photodetector. The technical problems to be solved by the invention are realized by the following technical scheme:
In a first aspect, the present invention provides a back-illuminated silicon-based single photon avalanche diode structure comprising:
Each isolation structure comprises a shallow groove isolation layer, an isolation N well and a deep groove isolation layer which are stacked in the P-type epitaxial layer from bottom to top; an electrode protection ring arranged in the wiring layer and close to the shallow groove isolation layer;
The light source induction areas are distributed between adjacent isolation structures at intervals, each light source induction area comprises an active P+ layer, an active area P well, a deep N well and an N-type buried layer which are stacked from bottom to top, P well protection rings, a reflection metal plate, a light source metal plate and a light source metal plate, wherein the P well protection rings are arranged on two sides of the active P+ layer and the active area P well and are connected with the shallow groove isolation layer and the isolation N well;
the shared cathode comprises an electrode N well and a cathode electrode, wherein the electrode N well is arranged in the P-type epitaxial layer and is connected with the deep N well, and the cathode electrode is arranged in the wiring layer close to the electrode N well.
In one embodiment of the invention, the deep N-well is a retrograde doped well.
In one embodiment of the invention, the doping concentration of the active region P-well is higher than the doping concentration of the P-well guard ring.
In one embodiment of the invention, the junction depth of the active region P-well is less than the junction depth of the P-well guard ring.
In one embodiment of the invention, the width of the active p+ layer is equal to the width of the reflective metal plate.
In one embodiment of the present invention, a plurality of light source sensing areas are distributed in an array, and the shared cathode is disposed in an area surrounded by top angles of every adjacent four light source sensing areas.
In one embodiment of the present invention, each of the light source sensing regions has a rounded structure.
In a second aspect, the present invention provides a photodetector comprising a plurality of back-illuminated silicon-based single photon avalanche diode structures as described in any one of the preceding claims distributed in an array.
The invention has the beneficial effects that:
The back-illuminated silicon-based single photon avalanche diode structure provided by the invention is a novel structure based on a compatible high-voltage CMOS (complementary metal oxide semiconductor) process, can ensure that the diode has a larger filling rate, has high detection efficiency in a wider spectral response range, thereby improving the detection efficiency and having a lower dark count rate, and particularly, an isolated N well in an isolated structure forms a reverse bias PN junction structure with a P well protection ring in a light source induction region to avoid carrier drift or adjacent light source induction region crosstalk formed by tunneling; the electrode protection ring in the isolation structure introduces an electric field peak value at the interface of the shallow groove isolation layer into the shallow groove isolation layer, so that dark count and post pulse caused by trapped charges on the surface of the shallow groove isolation layer under strong field use can be effectively reduced, the N-type buried layer is positioned at the position closest to the surface of the device, electrons are provided for a deep N well, and electric field enhancement at a shared cathode position caused by total depletion of the P-type epitaxial layer is avoided.
The present invention will be described in further detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a schematic cross-sectional view of a back-illuminated silicon-based single photon avalanche diode structure provided in an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a shared cathode in a back-illuminated silicon-based single photon avalanche diode structure provided in an embodiment of the present invention;
FIG. 3 is a top view of a back-illuminated silicon-based single photon avalanche diode structure provided in accordance with an embodiment of the present invention;
Fig. 4 is a schematic diagram of filling rates of pixel regions corresponding to different sizes and pitches according to an embodiment of the present invention;
Fig. 5 (a) -5 (b) are schematic diagrams of electric field distribution and avalanche ionization rate distribution of a back-illuminated silicon-based single photon avalanche diode structure according to an embodiment of the present invention;
Fig. 6 (a) -6 (b) are schematic electric field distribution diagrams of electrode guard rings at different positions in a back-illuminated silicon-based single photon avalanche diode structure according to an embodiment of the present invention.
Reference numerals illustrate:
1-P type epitaxial layer, 2-wiring layer, 3-shallow slot isolation layer, 4-isolation N well, 5-deep slot isolation layer, 6-electrode protection ring, 7-active P+ layer, 8-active region P well, 9-deep N well, 10-N type buried layer, 11-P well protection ring, 12-anode electrode, 13-reflection metal plate, 14-electrode N well and 15-cathode electrode.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Aiming at the problems of low detection efficiency and high dark count of the traditional SPAD, the embodiment of the invention considers the two aspects of improving the detection probability and reducing the dark count rate at the same time, and provides a back-illuminated silicon-based single photon avalanche diode structure and a photoelectric detector.
In a first aspect, referring to fig. 1, an embodiment of the present invention provides a back-illuminated silicon-based single photon avalanche diode structure, including:
A P-type epitaxial layer 1 and a wiring layer 2;
The device comprises a P-type epitaxial layer 1, a wiring layer 2, a plurality of isolation structures, an electrode protection ring 6, a plurality of isolation structures, a plurality of first isolation structures and a plurality of second isolation structures, wherein each isolation structure is arranged in the P-type epitaxial layer 1 and the wiring layer 2 and comprises a shallow groove isolation layer 3, an isolation N well 4 and a deep groove isolation layer 5 which are stacked in the P-type epitaxial layer 1 from bottom to top;
The light source induction areas are arranged in the P-type epitaxial layer 1 and the wiring layer 2 and are distributed between adjacent isolation structures at intervals, wherein each light source induction area comprises an active P+ layer 7, an active area P well 8, a deep N well 9 and an N-type buried layer 10 which are stacked from bottom to top, P well protection rings 11 which are arranged on two sides of the active P+ layer 7 and the active area P well 8 and are connected with the shallow trench isolation layer 3 and the isolation N well 4, a deep N well 9 which is also arranged on the P well protection rings 8 and the partial isolation N well 4 and wraps the shallow trench isolation layer 3 and the isolation N well 4 at the outermost side, an anode electrode 12 which is arranged in the wiring layer 1 below the active P+ layer 7, and a reflection metal plate 13 which is arranged in the wiring layer 2 opposite to the active P+ layer 7;
The shared cathode is arranged in the P-type epitaxial layer 1 and the wiring layer 2, wherein the shared cathode comprises an electrode N well 14 which is arranged in the P-type epitaxial layer 1 and is connected with the deep N well 9, and a cathode electrode 15 which is arranged in the wiring layer 2 close to the electrode N well 14.
The P-type epitaxial layer 1 is a ready-made silicon (Si) base substrate doped with phosphorus, arsenic or antimony, the doping concentration is about 5 multiplied by 10 15cm-3, the ready-made Si base substrate is thinned to form the thickness required by the P-type epitaxial layer 1, the doping concentration of the P-type epitaxial layer 1 is low, the depletion region width is wide, and the device detection probability and the spectral response range are improved.
The wiring layer 2 is a wiring layout layer having electrical characteristics, and is not strictly required here, and only the wiring layout requirement needs to be satisfied.
In the embodiment of the invention, in each isolation structure, a shallow groove isolation layer 3, an isolation N well 4 and a deep groove isolation layer 5 are used for isolating two adjacent light source induction areas, PN junction isolation is formed between the two adjacent light source induction areas, the isolation N well 4 is arranged on the upper surface of the shallow groove isolation layer 3 in the vertical direction, the deep groove isolation layer 5 is arranged on the upper surface of the isolation N well 4 in the vertical direction, in the process implementation, preferably, the shallow groove isolation layer 3 is of a structure with a narrow upper part and a wide lower part, the width of the upper side of the shallow groove isolation layer 3 is equal to the width of the isolation N well 4, the deep groove isolation layer 5 is of a structure with a wide upper part and a narrow lower part, the width of the lower side of the deep groove isolation layer 5 is smaller than the width of the isolation N well 4, and the width of the deep groove isolation layer 5 is smaller than the width of the isolation N well 4, so that the deep groove isolation layer 5 is provided with a sufficient safety distance for the light source induction area, and the trap caused by etching and filling processes can be prevented from negatively affecting the dark counting rate and post pulses;
an electrode protection ring 6 is arranged in the wiring layer 2 below the shallow trench isolation layer 3, and the electrode protection ring can be made of polysilicon, so that an electric field peak value at the interface of the shallow trench isolation layer 3 can be introduced into the shallow trench isolation layer 3, and dark counting and post-pulse caused by trapped charges on the surface of the shallow trench isolation layer 3 under strong field use can be effectively reduced.
In the embodiment of the invention, the active P+ layer 7 is arranged at the center of each light source sensing region, the active region P well 8 coincides with the center of the active P+ layer 7, the outer diameter is equal to the active P+ layer 7, the active region P well 8 is arranged right above the active P+ layer 7 in the vertical direction, the size of the light source sensing regions and the distance between the light source sensing regions are very critical to the whole device structure, and the proper size and distance can ensure higher filling rate. The active p+ layer 7 can be selected to be a rounded square structure, the dimension of the active p+ layer 7 corresponds to the length of the side length of the square structure, the dimension of the active p+ layer 7 is preferably 2-6 μm in the experimental process, and the distance between adjacent light source sensing areas can be designed differently according to actual needs;
The deep N well 9 is arranged above the active region P well 8, is a retrograde doped well, namely, the doping concentration surface is low, the doping depth is continuously increased, and the depletion region width is wider due to the continuously increased concentration, so that the detection probability and the spectral response range of the device are further improved, the deep N well 9 is shared by all light source sensing regions, a whole continuous region is formed, the shallow slot isolation layer 3 and the isolation N well 4 in the isolation structure are wrapped at the outermost side, and a multiplication main junction is formed with the active region P well, so that a strong electric field is formed, and the arrival of photons is perceived;
The N-type buried layer 10 is disposed at a position closest to the surface of the device structure, and the N-type buried layer 10 is shared by all the light source sensing regions to form a whole continuous region, and forms a multiplication main junction with the P-type epitaxial layer 1 to form a strong electric field so as to sense arrival of photons, thereby providing bias voltage for the deep N-well 9. An avalanche multiplication region is formed by the N-type buried layer 10 and the P-type epitaxial layer 1, an electric field is directed to the N-type buried layer 10 from the P-type epitaxial layer 1, electrons are mainly involved in avalanche in a high-field absorption region, the electron avalanche ionization rate is higher, the quantum efficiency can be further improved, the electric field enhancement at a shared cathode 40 caused by the total depletion of the P-type epitaxial layer 1 is avoided, and the doping concentration of the N-type buried layer 10 is higher, for example, the doping concentration is about 5 multiplied by 10 18cm-3, so that a smaller cathode series resistance can be provided for each light source induction region;
the P-well protection ring 11 surrounds the active region P-well 8 and the active P+ layer 7 in the light source induction region to form a physical epitaxial protection ring, and the isolation N-well 4 forms a reverse bias PN junction structure with the P-well protection ring 11 to avoid carrier drift or tunneling to form adjacent pixel crosstalk; under the action of the deep N well 9, the doping concentration required by forming the P well protection ring 11 is reduced, wherein the doping concentration of the P well 8 in the active region is higher than that of the P well protection ring 11, and the junction depth of the P well 8 in the active region is smaller than that of the P well protection ring 11, so that the central electric field of the light source induction region is higher than the side electric field, and the side breakdown is restrained in advance;
the anode electrode 12 is arranged at the center of the active P+ layer 7, is of floating potential and is connected with a subsequent circuit, and the potential change of a re-fixed node of the subsequent circuit is generated by high current generated by avalanche multiplication effect, so that the arrival of photons is reflected;
The reflective metal plate 13 is disposed under the anode electrode 12, and has a width equal to that of the active p+ layer, so as to reflect photons irradiated thereon back into the device, thereby increasing the photon utilization rate and enhancing the device detection probability at a longer wavelength.
Further, referring to fig. 2, in the embodiment of the present invention, a cathode electrode 15 in the shared cathode is electrically contacted with the N-type buried layer 10 through an electrode N-well 14 and a deep N-well 9, so as to provide bias voltages for the deep N-well 9 in each light source sensing region. In order to avoid potential non-uniformity caused by lateral resistance loss of the buried N-well layer 10, the shared cathode is supplied with bias voltages by adjacent four light source sensing regions together.
Referring to fig. 3, in a top view of a back-illuminated silicon-based single photon avalanche diode structure according to an embodiment of the present invention, the diode is an array structure of 2 rows and 2 columns, each light source sensing area is a rounded square structure, and the shared cathode is located in an area surrounded by rounded corners of four light source sensing areas. Wherein, FIG. 1 is a cross-sectional structure taking x-x' as a tangential plane, and the corresponding FIG. 2 is a similar cross-sectional structure.
The back-illuminated silicon-based single photon avalanche diode structure provided by the embodiment of the invention can be also applied to a photoelectric detection chip based on a back-illuminated three-dimensional framework, the chip is divided into two layers, the light-sensitive device layer can be manufactured on the top chip by adopting the diode structure provided by the embodiment of the invention, so that the filling rate is obtained to the maximum extent, the detection efficiency is improved, the dark counting rate is lower, other circuits are manufactured on the bottom chip, and copper-copper bonding can be adopted between the two layers.
In order to verify the effectiveness of the back-illuminated silicon-based single photon avalanche diode structure proposed by the embodiments of the present invention, the following experiment is used for illustration.
For the light source sensing region, a larger filling rate means higher photon utilization rate and detection efficiency, and a smaller light source sensing region distance means better image fineness. Based on the device structure corresponding to the above-mentioned alternative, referring to fig. 4, fig. 4 shows the corresponding filling rate change of the light source sensing region under different sizes and pitches, it can be seen that for the back-illuminated silicon-based single photon avalanche diode structure provided by the embodiment of the invention, when the size of the active p+ layer 7 in the light source sensing region is within the range of 2 μm to 6 μm, for silicon-based SPAD, the smaller light source sensing region pitches all obtain higher filling rate. For example, the filling rate is 0.25% when the size of the active P+ layer 7 in the light source sensing region is 2 μm and the interval between the light source sensing regions is 2.5 μm, and the filling rate is more than 0.5% when the size of the active P+ layer 7 in the light source sensing region is 6 μm and the interval between the light source sensing regions is 17 μm.
Referring to fig. 5 (a) -5 (b), fig. 5 (a) is a schematic diagram of electric field distribution of a back-illuminated silicon-based single photon avalanche diode structure according to an embodiment of the present invention. When the reverse bias breakdown voltage of the device reaches 2V, the device structure can lock a strong electric field in the middle position of the light source induction area, wherein the polycrystalline silicon electrode protection ring 6 plays a good role in protection, the electric field at the edge of a pixel is obviously lower than the electric field in the central area of the light source induction area, and the edge breakdown is effectively inhibited, and the avalanche ionization rate distribution diagram of the back-illuminated silicon-based single photon avalanche diode structure provided by the embodiment of the invention can be seen, the avalanche ionization mainly occurs in the middle position of the light source induction area, a larger value is kept in a wider range, and the device structure provided by the embodiment of the invention can realize the avalanche nose multiplication process efficiently.
Referring to fig. 6 (a) -6 (b), fig. 6 (a) is a simulation result of electric field distribution of the polysilicon electrode guard ring 6 disposed in the middle of the shallow trench isolation layer 3 in the back-illuminated silicon-based single photon avalanche diode structure according to the embodiment of the invention, and fig. 6 (b) is a simulation result of electric field distribution of the polysilicon electrode guard ring 6 disposed in the boundary of the shallow trench isolation layer 3 in the back-illuminated silicon-based single photon avalanche diode structure according to the embodiment of the invention. As can be seen from fig. 6 (a) - (6 (b)), although the polysilicon electrode guard ring 6 is also used to suppress edge breakdown, when the polysilicon electrode guard ring 6 is disposed in the middle of the shallow trench isolation layer 3, the electric field at the edge of the shallow trench isolation layer 3 is significantly lower than the electric field at the boundary of the shallow trench isolation layer 3 where the polysilicon electrode guard ring 6 is disposed. Among them, it can be seen that the polysilicon electrode guard ring 6 plays a good role in protection, effectively suppressing edge breakdown, and the electric field near the shallow trench isolation layer 3 is significantly reduced, which effectively reduces the dark count rate of the device due to trap trapping.
It should be noted that, in the embodiment of the present invention, the P-type doping is doped with a group V element, such as boron, aluminum, etc., and the N-type doping is doped with a group III element, such as phosphorus, antimony, etc.
In summary, the back-illuminated silicon-based single photon avalanche diode structure provided by the embodiment of the invention is a novel structure based on a compatible high-voltage CMOS process, and the structure can ensure that the diode has a larger filling rate and has high detection efficiency in a wider spectral response range, thereby improving the detection efficiency and having a lower dark count rate, and particularly, an isolated N well 4 in an isolated structure forms a reverse bias PN junction structure with a P well protection ring 11 in a light source induction region, so that crosstalk between adjacent light source induction regions formed by carrier drift or tunneling is avoided; the electrode protection ring 6 in the isolation structure introduces an electric field peak value at the interface of the shallow slot isolation layer 3 into the shallow slot isolation layer 3, so that dark counting and post-pulse caused by trapped charges on the surface of the shallow slot isolation layer 3 under strong field use can be effectively reduced, the N-type buried layer 10 is positioned at the position closest to the surface of the device, electrons are provided for the deep N well 9, and electric field enhancement at the shared cathode position caused by full depletion of the P-type epitaxial layer 1 is avoided.
Meanwhile, the deep N well 9 is a retrograde doped well, the doping concentration of the deep N well 9 is controlled to be beneficial to reducing the doping concentration required for forming the P well protection ring 11, and the depletion region width is wider due to the continuous reduction of the doping concentration, so that the device detection probability and the spectral response range are improved.
In a second aspect, an embodiment of the present invention provides a photodetector including a plurality of the above-mentioned back-illuminated silicon-based single photon avalanche diode structures distributed in an array. The photoelectric detector provided by the embodiment of the invention is formed based on the back-illuminated silicon-based single photon avalanche diode structure, and the implementation of the SPAD is not repeated here. By adopting the back-illuminated silicon-based single photon avalanche diode structure, the photoelectric detector also has larger filling rate and high detection probability in a wider spectral response range, thereby achieving the purposes of improving detection efficiency and having lower dark count rate.
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the embodiments of the present invention, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
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| CN105185796A (en) * | 2015-09-30 | 2015-12-23 | 南京邮电大学 | High-detective-efficiency single photon avalanche diode detector array unit |
| CN105810775A (en) * | 2014-12-31 | 2016-07-27 | 湘潭大学 | CMOS image sensor technology-based NP type single-photon avalanche diode |
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| CN109300992B (en) * | 2018-08-16 | 2020-01-21 | 杭州电子科技大学 | Single photon avalanche diode with high detection efficiency and manufacturing method thereof |
| CN109638092A (en) * | 2018-11-15 | 2019-04-16 | 天津大学 | The SPAD of the low dark counting of high detection efficient based on standard CMOS process |
| CN111999719B (en) * | 2019-05-10 | 2024-03-12 | 中国科学院半导体研究所 | Single-photon TOF image sensor for lidar |
| CN112490300B (en) * | 2020-10-29 | 2022-07-22 | 西安电子科技大学 | A SPAD device sharing deep N well and its photodetection array |
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| CN105810775A (en) * | 2014-12-31 | 2016-07-27 | 湘潭大学 | CMOS image sensor technology-based NP type single-photon avalanche diode |
| CN105185796A (en) * | 2015-09-30 | 2015-12-23 | 南京邮电大学 | High-detective-efficiency single photon avalanche diode detector array unit |
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