CN114513201A

CN114513201A - GaN transistor drive circuit

Info

Publication number: CN114513201A
Application number: CN202011282053.9A
Authority: CN
Inventors: 陈欣璐; 黄兴
Original assignee: Pn Junction Semiconductor Hangzhou Co ltd
Current assignee: Pn Junction Semiconductor Hangzhou Co ltd
Priority date: 2020-11-17
Filing date: 2020-11-17
Publication date: 2022-05-17
Anticipated expiration: 2040-11-17
Also published as: CN114513201B

Abstract

The present invention relates to a GaN transistor driving circuit. It is used for a driven GaN transistor, including an upper and lower tube circuit and an upper and lower tube control circuit, the upper and lower tube circuits include an upper tube and a lower tube, the upper tube and the lower tube are both GaN transistors, and the drain of the upper tube It is connected to the power supply voltage VCC, the gate is connected to the digital input VIN, the source is connected to the drain of the lower tube, and is connected to the gate of the driven GaN transistor as the output of the GaN transistor drive circuit; the gate of the lower tube is connected to the upper and lower tubes. The upper and lower tube control circuits use the bus voltage VD, the power supply voltage VCC and the digital input VIN to control the lower tube, so that the output of the GaN transistor drive circuit is in phase with the digital input VIN, and the upper and lower tubes are in phase with the digital input VIN. The tube control circuit includes transistors, and the included transistors are all GaN transistors, which are turned on when a voltage higher than a threshold voltage is applied to the gate.

Description

GaN transistor drive circuit

Technical Field

The present invention relates to a GaN transistor, and more particularly, to a GaN transistor driving circuit.

Background

With the rapid development of power electronic systems, the market of power semiconductor devices has been rapidly developed. The performance of silicon-based devices has gradually reached the theoretical limit of materials, and the requirements of modern high-power electronic systems are increasingly not met. Under such circumstances, the third generation wide bandgap semiconductor represented by GaN and SiC is gradually replacing Si material and is the first choice for device design in high temperature and high frequency environment.

The gate driver of the existing Si device is not suitable for driving the GaN device, mainly represented by the low gate driving voltage (6V) of the enhancement type GaN transistor, and the difference between the gate breakdown voltage and the full turn-on voltage is also low (3V). Conventional gate drivers that use SiMOSFETs to generate the gate voltage, while effective for most Si MOSFET devices, do not provide the low voltage gate voltage for GaN devices. Moreover, the existing driving is made by using a Si process incompatible with GaN, so that the inductance of the gate loop is increased, and because the turn-on speed of the GaN device is in the nanosecond level, dV/dt of the power loop is generally greater than 100V/ns, which causes the gate loop to induce a huge oscillation. Therefore, the direct driving of the GaN device by using the conventional gate driver may not only cause device breakdown, thereby causing system failure, but also introduce circuit oscillation to affect the system efficiency improvement.

On the other hand, although the fully integrated GaN driver in the prior art can effectively drive the main GaN device to normally work, the internal structure of the driver is often complex, and the turn-on and turn-off delays are long.

Disclosure of Invention

The present invention has been made in view of the above-mentioned circumstances of the prior art to overcome or alleviate one or more of the technical problems of the prior art, and at least to provide a useful choice.

According to an aspect of the present invention, a GaN transistor driving circuit is provided, the GaN transistor driving circuit includes an upper and lower transistor circuit and an upper and lower transistor control circuit, the upper and lower transistor circuit includes an upper transistor and a lower transistor, both of which are GaN transistors, a drain of the upper transistor is connected to a power supply voltage, a gate of the upper transistor is connected to a digital input, a source of the upper transistor is connected to a drain of the lower transistor, and is connected to a gate of the driven GaN transistor as an output of the GaN transistor driving circuit; the grid of the lower tube is connected with the upper tube control circuit and the lower tube control circuit; the upper and lower tube control circuits control the lower tube by using working voltage, power supply voltage and digital input, so that the output of the GaN transistor driving circuit is in phase with the digital input, and the upper and lower tube control circuits comprise transistors which are all GaN transistors and are conducted when voltage higher than threshold voltage is applied to a grid electrode.

According to the embodiment of the invention, the driving circuit has a simple structure and short delay.

According to some embodiments of the invention, the GaN transistor driving circuit and the GaN power device are integrated in a single chip, so that the volume of the system can be reduced, and the power consumption can be reduced.

Drawings

The invention may be better understood with reference to the following drawings, in which:

FIG. 1 is a schematic diagram of a GaN transistor driving circuit according to an embodiment of the invention;

FIG. 2 shows a schematic diagram of a GaN transistor drive circuit in accordance with another embodiment of the invention;

FIG. 3 illustrates input and output waveforms according to the embodiment shown in FIG. 4;

FIG. 4 shows a schematic diagram of a GaN transistor drive circuit according to yet another embodiment of the invention; and

fig. 5 illustrates input-output waveforms according to the embodiment shown in fig. 4.

Detailed Description

FIG. 1 is a schematic diagram of a GaN transistor driving circuit according to an embodiment of the invention. As shown in fig. 1, the GaN transistor driving circuit 1 according to an embodiment of the present invention is used to drive a driven GaN transistor Q1, the drain of the driven GaN transistor Q1 is connected to the bus voltage VD, and the source is connected to ground. The GaN transistor drive circuit 1 includes an upper and lower transistor circuit 10 and an upper and lower transistor control circuit 20. The upper and lower transistor circuit 10 includes an upper transistor Q5 and a lower transistor Q6, both of which are GaN transistors, specifically, enhancement mode GaN High Electron Mobility Transistors (HEMTs), that turn on when a high voltage higher than a threshold voltage is applied to the gate. It will be understood by those skilled in the art that in the present invention, a voltage higher than the threshold voltage of a transistor may be referred to as a high voltage, and vice versa as a low voltage. According to an embodiment of the present invention, the bus voltage VD may be a high voltage of 100V to 650V, the power voltage VCC may be 6V, the logic high level of the digital input VIN is 12V, and the logic low level is 0V. The logic high levels of the supply voltage VCC and the digital input VIN are both high voltages.

The drain of the upper tube Q5 is connected to the supply voltage VCC, the gate is connected to the digital input VIN, and the source is connected to the drain of the lower tube Q6 and to the gate of the driven GaN transistor Q1 as the output of the GaN transistor drive circuit 1. The gate of the lower tube Q6 is connected to the upper and lower tube control circuit 20. The upper and lower tube control circuit 20 controls the lower tube by using the bus voltage VD, the power supply voltage VCC, and the digital input VIN, so that the output of the GaN transistor driving circuit is in phase with the digital input VIN. The upper and lower tube control circuits 20 include transistors, and each of the included transistors is a GaN transistor that is turned on when a voltage higher than a threshold voltage is applied to a gate.

According to this embodiment, the transistors used in the up-down transistor circuit 10 and the up-down transistor control circuit 20 are GaN transistors, and therefore, the function is simple, and the entire circuit structure is simple and has a short delay.

Fig. 2 shows a schematic diagram of a GaN transistor driver circuit according to an embodiment of the present invention. Referring to fig. 1, the upper and lower tube control circuit 20 includes a first transistor Q3, a second transistor Q4, and a third transistor Q2.

The drain of the first transistor Q3 is connected to the source of the third transistor Q2 and to the gate of the down tube Q6, the gate of the first transistor Q3 is connected to the source of the second transistor Q4, and the source of the first transistor Q3 is connected to ground.

The drain of the second transistor Q4 is coupled to the digital input VIN, the gate of the second transistor Q4 is coupled to the supply voltage VCC, and the source of the second transistor Q4 is coupled to the gate of the first transistor Q3.

The drain of the third transistor Q2 is coupled to the operating voltage VD, the gate of the third transistor Q2 is coupled to the drain of the lower transistor Q6 and the source of the upper transistor Q5, and the source of the third transistor Q2 is coupled to the drain of the first transistor Q3.

When VIN is high, the upper tube Q5 is conducting. Meanwhile, since the second transistor Q4 is in a normally-on state, VIN is applied to the gate of the first transistor Q3 through the second transistor Q4, so that the first transistor Q3 is turned on. Thus, the gate of lower tube Q6 is applied with a low voltage, and lower tube Q6 is turned off. Since the upper tube Q5 is on and the lower tube Q6 is off as described above, the transistor Q2 is on, and thus a high voltage is applied to the gate of the driven GaN transistor Q1. When VIN is low, the upper tube Q5 is turned off. Meanwhile, since the second transistor Q4 is in a normally-on state, a low voltage VIN is applied to the gate of the first transistor Q3 through the second transistor Q4, so that the first transistor Q3 is also turned off. At the moment when the transistor Q3 is turned off, the transistor Q2 is still in a conducting state due to the delay of the circuit, so that the gate of the lower tube Q6 is at the same potential as the bus voltage, and the lower tube Q6 is kept on and cannot be broken down by the bus voltage due to the existence of the protection diode D1. When the circuit is in steady state, the upper tube Q5 is off and the lower tube Q6 is on, so a low voltage is applied to the gate of the driven GaN transistor Q1.

According to one embodiment of the present invention, the gate widths of the third transistor Q2, the first transistor Q3, the upper tube Q5 and the lower tube Q6 are the same, and the gate width of the second transistor Q4 is 5% -30%, more preferably 10%, of the gate width of the third transistor Q2. By using the technical scheme, the response speed of the driving circuit can be improved. In the present invention, the two transistors have the same gate width means that the difference between the gate width of one transistor and the gate width of the other transistor is within 10% of the gate width of the one transistor.

According to one embodiment, the driven transistor Q1 and the GaN transistor driver circuit of the present invention are integrated on a single chip.

Fig. 3 illustrates input-output waveforms according to the embodiment shown in fig. 2. As can be seen from the waveform diagram of fig. 3, the gate voltage of the driven device Q1 is in phase with the digital input VIN very well, the delay is short, and the output can be stabilized.

Fig. 4 shows a schematic diagram of a GaN transistor driving circuit according to still another embodiment of the present invention. As shown in fig. 4, a voltage regulator circuit 30 is provided between the power supply voltage VCC and the upper and lower pipe circuits.

The structure in the dashed line frame is the same as the embodiment shown in fig. 2, and therefore, the description thereof is omitted.

The voltage regulator circuit outside the dashed line frame is composed of a transistor Q7, resistors R1 and R2, a capacitor C1 and a diode D2 to form an LDO (low dropout linear regulator) to provide the voltage required by the drain of the upper tube Q5.

In this embodiment, the transistor Q7 has a drain connected to the power supply voltage VCC, a source connected to one end of a capacitor C1, the other end of a capacitor C1 connected to one end of a resistor R2, and the other end of a resistor R2 connected to ground. The power supply voltage VCC is also connected to one end of a resistor R1, the other end of the resistor R1 is connected to the gate of the transistor Q7 and the anode of the diode D2, and the cathode of the diode D2 is grounded. The transistor Q7 has the same gate width as that of the transistor Q4, the diode D2 is a clamp diode, and the clamp voltage is 9V.

The capacitor C1 may be replaced with an enhancement mode device source drain short and gate. In addition, the resistors R1 and R2, the capacitor C1 and the diode D2 may be formed by discrete components outside the chip.

According to this embodiment, the logic high of the power voltage VCC and the digital input VIN may average to 12V, and the logic low of the digital input VIN is 0V.

Fig. 5 illustrates input-output waveforms according to the embodiment shown in fig. 4. As can be seen from the waveform diagram of fig. 5, the gate voltage of the driven device Q1 is in phase with the digital input VIN very well, the delay is short, and the output can be stabilized. While the voltage at the drain of the upper tube Q5 is also very stable.

Embodiments in accordance with the invention may have one or more of the following advantages.

(1) The GaN transistor is adopted in the whole chip, so that the monolithic integration of the gate drive circuit and the main device is facilitated.

(2) The designed driving circuit can provide more accurate grid voltage for the main device (the transistor Q1), so that the main device can work safely and stably.

(3) Further reduction of driver size and power consumption is achieved on the premise that a satisfactory gate voltage is provided for the main device.

It will be appreciated by those skilled in the art that some embodiments according to the invention may not have any of the above advantages, but may merely provide an alternative.

The above detailed description of the present invention is only for the purpose of enabling those skilled in the art to further connect the present invention for implementing the present invention, and does not limit the scope of the present invention. Only the claims should be looked to in order to determine the scope of the invention. Thus, combinations of features in the foregoing detailed description do not necessarily represent the broadest scope of the invention. The various features of the teachings presented in this specification may be combined in various ways to obtain additional useful embodiments of the invention, and such combinations are within the scope of the invention.

Claims

1. A GaN transistor drive circuit for a driven GaN transistor (Q1), wherein the GaN transistor drive circuit comprises an upper and lower tube circuit and an upper and lower tube control circuit,

The upper and lower tube circuits include an upper tube (Q5) and a lower tube (Q6), and the upper tube and the lower tube are both GaN transistors,

The drain of the upper tube is connected to the power supply voltage (VCC), the gate of the upper tube is connected to the digital input (VIN), the source of the upper tube is connected to the drain of the lower tube, and serves as the The output of the GaN transistor driving circuit is connected to the gate of the driven GaN transistor;

The grid of the lower tube is connected with the upper and lower tube control circuit;

The upper and lower tubes control circuit uses the power supply voltage (VCC) and the digital input (VIN) to control the lower tubes, so that the output of the GaN transistor drive circuit is in phase with the digital input (VIN), and the upper and lower tubes control The circuit includes transistors, and the included transistors are all GaN transistors that conduct when a voltage above a threshold voltage is applied to the gate.

2 . The GaN transistor driving circuit according to claim 1 , wherein the upper and lower tube circuits further comprise a GaN diode, the anode of the GaN diode is connected to the gate of the lower tube, and the cathode is connected to the ground. 3 .

3. The GaN transistor drive circuit according to claim 1, wherein the upper and lower tube control circuit comprises a first transistor (Q3), a second transistor (Q4) and a third transistor (Q2),

The drain of the first transistor (Q3) is connected to the source of the third transistor (Q2) and the gate of the lower transistor (Q6), and the gate of the first transistor (Q3) is connected to the The source of the second transistor (Q4) is connected, and the source of the first transistor (Q3) is grounded;

The drain of the second transistor (Q4) is connected to the digital input (VIN), the gate of the second transistor (Q4) is connected to the supply voltage VCC, and the source of the second transistor (Q4) The pole is connected to the gate of the first transistor (Q3);

The drain of the third transistor (Q2) is connected to the bus voltage (VD), the gate of the third transistor (Q2) is connected to the drain of the lower transistor (Q6), the third transistor The source of (Q2) is connected to the drain of the first transistor (Q3).

4. The GaN transistor drive circuit according to claim 1, characterized in that a voltage regulator circuit is provided between the power supply voltage (VCC) and the upper and lower tube circuits (10).

5. The GaN transistor drive circuit according to claim 4, wherein the voltage regulator circuit comprises a GaN transistor (Q7), a first resistor (R1), a second resistor (R2), a capacitor (C1) and a diode (D2),

The drain of the GaN transistor (Q7) is connected to the power supply voltage (VCC), the source is connected to one end of the capacitor (C1), and the other end of the capacitor (C1) is connected to one end of the second resistor (R2) , the other end of the second resistor (R2) is grounded, the power supply voltage (VCC) is also connected to one end of the first resistor (R1), and the other end of the first resistor (R1) is connected to the GaN The gate of the transistor (Q7) and the anode of the diode (D2) are connected, and the cathode of the diode (D2) is grounded.

6 . The GaN transistor driving circuit according to claim 1 , wherein the GaN transistor driving circuit and the driven GaN transistor are integrated on a single chip. 7 .

7. The GaN transistor driving circuit according to claim 3, wherein the third transistor (Q2) is a high-voltage transistor, the first transistor (Q3), the second transistor (Q4), the upper transistor (Q5) and the The lower tube (Q6) is a low voltage transistor.

8. The GaN transistor driving circuit according to claim 7, wherein the gate width of the third transistor (Q2), the first transistor (Q3), the upper transistor (Q5) and the lower transistor (Q6) are the same, The gate width of the second transistor (Q4) is 5-30% of the gate width of the third transistor (Q2).