CN114499512A - Double-loop phase-locked loop - Google Patents
Double-loop phase-locked loop Download PDFInfo
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- CN114499512A CN114499512A CN202210087617.6A CN202210087617A CN114499512A CN 114499512 A CN114499512 A CN 114499512A CN 202210087617 A CN202210087617 A CN 202210087617A CN 114499512 A CN114499512 A CN 114499512A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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Abstract
本公开提供了一种双环路锁相环，其包括：压控振荡器、鉴频鉴相器，以及位于二者之间积分路径上的第一电荷泵和第一环路滤波器和位于二者之间比例路径上的第二电荷泵和第二环路滤波器，其中，该第二环路滤波器包括：电压生成器，用于接收输入电压并根据扫频斜率变化生成偏置电压；以及滤波电路，用于根据该偏置电压调节其输入节点的电位，以维持该双环路锁相环扫频过程中位于比例路径上的环路滤波器的输出电压的电位，由此可根据扫频斜率要求，在比例路径上的环路滤波器的输入节点施加不同的初始电压，以在比例路径上的环路滤波器上施加初始电压后，系统参数将能精准控制，大幅提升双环路锁相环的稳定性、可靠性以及相关性能参数。
The present disclosure provides a dual-loop phase-locked loop, which includes a voltage-controlled oscillator, a frequency discriminator, a phase detector, and a first charge pump and a first loop filter located on an integration path between the two and a first loop filter located on the second a second charge pump and a second loop filter on a proportional path between them, wherein the second loop filter includes: a voltage generator for receiving an input voltage and generating a bias voltage according to a change in the sweep frequency slope; and a filter circuit for adjusting the potential of its input node according to the bias voltage to maintain the potential of the output voltage of the loop filter located on the proportional path during the frequency sweep of the dual-loop phase-locked loop, so that the potential of the output voltage of the loop filter on the proportional path can be maintained according to the sweep The frequency slope requires that different initial voltages are applied to the input node of the loop filter on the proportional path, so that after applying the initial voltage to the loop filter on the proportional path, the system parameters can be precisely controlled, greatly improving the dual-loop lock. The stability, reliability and related performance parameters of the phase loop.
Description
Technical Field
The disclosure relates to the technical field of electronic circuits, in particular to a double-loop phase-locked loop.
Background
In the application of integrated circuits, a clock system is an important module of chip design, and is realized by adopting a phase-locked loop circuit in order to meet different clock requirements of the system.
The frequency locking of the frequency synthesis phase-locked loop in the related technology is realized by a single loop, and the loop is formed by sequentially connecting a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a prescaler and a frequency divider. Firstly, a voltage-controlled oscillator generates an oscillation signal with a certain frequency through self-oscillation, the signal enters a phase frequency detector after passing through a prescaler and a frequency divider, is compared with a reference frequency, and generates a frequency difference signal and a phase difference signal to enter a charge pump. The charge pump determines the current to be drawn or pumped according to the frequency difference and the phase difference, and converts the current to a voltage value. The output voltage of the charge pump enters the voltage-controlled oscillator after being filtered by the loop filter, and the frequency of the oscillation signal of the voltage-controlled oscillator is changed by adjusting the value of a variable capacitor in the voltage-controlled oscillator. In practice, the whole loop is to lock the frequency of the signal generated by the voltage-controlled oscillator in the required frequency band according to the frequency difference, and then to lock the oscillation frequency at the required frequency point by a fine tuning mode of gradually approaching the frequency of the output signal of the frequency divider to the reference frequency.
In the traditional phase-locked loop, the frequency range covered by the variable capacitor of the voltage-controlled oscillator is very limited, and the traditional phase-locked loop is completely inapplicable to broadband application, such as a ZigBee system. If the variable capacitor array is adopted to select the frequency band, the control signal and the frequency band of the capacitor array need to be set to be in a one-to-one correspondence relationship, namely, a certain digital control value is preset to correspond to a certain frequency band, when the frequency band oscillation signal is needed, a set digital code control word is manually input to enable the oscillation frequency of the digital code control word to be in the frequency band, then the loop frequency is finely adjusted, and finally the signal is locked at a certain oscillation frequency in the frequency band. However, due to the influence of process deviation, voltage variation and temperature drift, the frequency signal generated by the actual voltage-controlled oscillator circuit is far from the preset value, the one-to-one correspondence relationship between the control word of the variable capacitor array and the frequency band generates large deviation, and more loop cycles are needed to approach the frequency to lock the required oscillation frequency, so that the frequency locking time of the phase-locked loop is greatly prolonged.
On the basis, as shown in fig. 1, the improved dual-loop phase-locked loop proposed on the basis is a dual-loop phase-locked loop 100 including an integral path 120 and a proportional path 130, when a frequency sweep is performed, an output voltage of a loop filter 122 on the integral path 120 may change according to an output frequency, and an output voltage of a loop filter 132 on the proportional path 130 may ideally remain unchanged, but in an actual circuit, on one hand, because an input phase difference of a phase frequency detector 110 is not 0 during the frequency sweep, an output voltage of the loop filter 132 on the proportional path 130 may change and deviate from an expected value thereof, and this deviation may cause a loop parameter of the dual-loop phase-locked loop 100 to change, thereby deteriorating an overall performance of the phase-locked loop, or even causing a loss of lock.
On the other hand, the loop filter 132 on the proportional path 130 in the current dual-loop phase-locked loop 100 generally adopts a differential virtual ground connection, and as shown in fig. 2, a virtual ground is connected to a connection node of the resistor R1 and the resistor R2 connected in series. This connection does not avoid the output voltage of the loop filter 132 on the proportional path 130 from deviating from the desired value during the frequency sweep.
Disclosure of Invention
In order to solve the above technical problem, the present disclosure provides a dual loop phase locked loop.
The present disclosure provides a dual loop phase locked loop, comprising:
a voltage controlled oscillator having a power supply terminal and a control terminal for generating a high frequency clock signal;
a phase frequency detector for detecting a phase difference between a phase of the high frequency clock signal and a phase of the reference signal and generating an integrated signal representing an integrated value of the phase difference and a proportional signal representing a current value of the phase difference;
the first charge pump and the first loop filter are positioned on an integration path between the voltage-controlled oscillator and the phase frequency detector and used for receiving an integration signal and supplying an adjusted integration signal to a power supply terminal of the voltage-controlled oscillator;
a second charge pump and a second loop filter located in a proportional path between the voltage controlled oscillator and the phase frequency detector for receiving the proportional signal and supplying an adjusted proportional signal to a control terminal of the voltage controlled oscillator;
wherein the second loop filter comprises:
the voltage generator is used for receiving input voltage and generating bias voltage according to the change of the frequency sweep slope; and
a filter circuit for obtaining the bias voltage through its input node and adjusting the potential of the input node according to the bias voltage to maintain the potential of the output voltage of the loop filter on the proportional path during the frequency sweep of the dual-loop phase-locked loop,
the voltage controlled oscillator generates a high frequency clock signal having an oscillation frequency controlled by both the adjusted integration signal and the proportional signal such that a phase of the high frequency clock signal is locked to a phase of the reference signal.
Preferably, the aforementioned dual-loop phase-locked loop further includes:
a frequency divider coupled between the voltage-controlled oscillator and the phase frequency detector for dividing the frequency of the high-frequency clock signal to obtain a low-frequency signal,
wherein the phase frequency detector detects a phase difference by comparing a phase of the low frequency signal with a phase of a reference signal.
Preferably, the aforementioned loop filter further includes:
and the gain amplifier is connected between the output end of the voltage generator and the input node of the filter circuit and is used for performing gain amplification on the bias voltage.
Preferably, the input nodes of the second loop filter include a first input node and a second input node, and the filter circuit includes:
a first resistor and a third resistor connected in series between the first input node and the first output node;
a second resistor and a fourth resistor connected in series between a second input node and a second output node, the first output node and the second output node being configured to provide the output voltage;
the first end of the first capacitor is connected with the connection node of the first resistor and the third resistor, and the second end of the first capacitor is connected with the connection node of the second resistor and the fourth resistor;
and a second capacitor having a first end connected to the first output node and a second end connected to the second output node.
Preferably, the aforementioned voltage generator includes:
a switch resistance network, which has a plurality of fifth resistances connected in series between the power supply terminal and the ground in sequence, and the connection node between any two adjacent fifth resistances is connected with a switch element,
in the frequency sweeping process of the double-loop phase-locked loop, two switch elements which are sequentially gated are respectively communicated to the first input node and the second input node so as to provide the bias voltage.
Preferably, the aforementioned offset voltage is a voltage value that enables an offset voltage amount of an output voltage of the loop filter located on the proportional path to become zero when the dual-loop phase-locked loop switches from the locked mode to the sweep mode stage and operates at a predetermined sweep slope.
Preferably, the aforementioned first loop filter includes:
a first end of the third capacitor and a first end of the sixth resistor are connected to a third output node of the first charge pump, a second end of the third capacitor is grounded, and a second end of the sixth resistor is connected to the power supply terminal;
a second end of the fourth capacitor and a first end of the seventh resistor are connected to the ground in common, the first end of the fourth capacitor is connected to the aforementioned power supply terminal, and the second end of the seventh resistor is connected to the fourth output node of the first charge pump.
Preferably, a connection node of the first resistor and the third resistor in the aforementioned second loop filter is connected to a fifth output node of the second charge pump, a connection node of the second resistor and the fourth resistor is connected to a sixth output node of the second charge pump, and the first output node and the second output node of the second loop filter are used for providing an output voltage to the aforementioned control terminal.
Preferably, the magnitude of the bias voltage in the second loop filter is proportional to the slope of the frequency sweep and proportional to the output current of the first charge pump on the proportional path.
The beneficial effects of this disclosure are: the utility model provides a double loop phase-locked loop, this double loop phase-locked loop has charge pump and loop filter of proportional path and integral path to couple between phase frequency detector and voltage controlled oscillator, wherein, the loop filter who is located the proportional path includes: the voltage generator is used for receiving input voltage and generating bias voltage according to the change of the frequency sweep slope; and the filter circuit is used for acquiring the bias voltage through the input node of the filter circuit, and adjusting the potential of the input node according to the bias voltage so as to maintain the potential of the output voltage of the loop filter positioned on the proportional path in the frequency sweeping process of the double-loop phase-locked loop.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
FIG. 1 illustrates a circuit diagram of a prior art two-loop phase-locked loop;
FIG. 2 is a schematic diagram of a loop filter in the scale path of the dual loop phase locked loop of FIG. 1;
fig. 3 is a circuit diagram of a dual loop phase locked loop according to an embodiment of the disclosure;
figure 4 shows a schematic diagram of a second loop filter for use in the two-loop phase-locked loop of figure 3;
figure 5 shows a circuit configuration diagram of the second loop filter of figure 4 at the voltage generator;
fig. 6 is a circuit configuration diagram illustrating a first loop filter located on an integration path in the dual-loop phase-locked loop shown in fig. 3.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are set forth in the accompanying drawings. However, the present disclosure may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
In a radio transceiver, a variable local oscillator signal from a reference signal source (e.g., a crystal oscillator) is synthesized, typically using a Phase Locked Loop (PLL), the crystal oscillator having a stable output with low phase noise. The PLL generates an output signal that is phase locked to the reference signal. Typically, the desired output radio frequency is higher than a reference frequency from a suitable reference source. An important characteristic of a PLL when used as a local oscillator is the selectivity of its communication channel, i.e. the gap between its output channels or its resolution.
The earliest and simplest type is an integer NPLL single loop, where the output signal is fed back to the phase comparator of the PIL through a frequency divider with an integer divide ratio N. In general, the comparison signal conveys a reference signal derivation through a reference divider having an integer divide ratio R. The selection of the output communication channel is equal to the comparison frequency. Such a PLL is well developed with a sufficiently low power consumption for battery applications. However, this simple type of PLL suffers from phase noise problems when the frequency division ratios R and N are set to provide a high output frequency with a narrow selection of communication channels.
Another very important type of PL is the fractional NPLL, which has the same structure as the integer NPL except that the division ratio of the feedback divider is an integer plus a rational fraction. The choice of the communication channel of the output signal is therefore also a rational fraction of the comparison frequency. However, it is difficult to implement a fractional NPLL for low noise and low power. A high performance fractional NPL requires high complexity, consumes large areas of silicon and is not easily integrated with other low noise systems on the same module.
An improvement of a single loop PLL can be obtained by using a dual loop PLL combining two phase locked loops.
A loop filter 122 in the conventional dual loop phase-locked loop architecture 100 (for example, a loop filter on the proportional path 120). When the dual-loop phase-locked loop 100 performs frequency sweeping, the output voltage of the loop filter 132 on the integral path 130 changes according to the output frequency, and the output voltage of the loop filter 122 on the proportional path 120 ideally remains unchanged, but in an actual circuit, because the input phase difference of the phase frequency detector 110 is not 0 during the frequency sweeping process, the current loop filter 122 on the proportional path 120 in the dual-loop phase-locked loop 100 adopts a differential virtual ground connection mode, which cannot avoid that the output voltage of the loop filter 122 on the proportional path changes and deviates from the expected value thereof during the frequency sweeping process. This deviation causes a change in the loop parameters of the dual-loop pll 100, which degrades the overall performance of the pll and even causes loss of lock, which affects the performance of the pll.
Based on this, the dual-loop phase-locked loop (PLL) in the embodiment of the present disclosure is provided to effectively make up for the voltage deviation defect, so that the PLL maintains the expected system parameters under the requirement of different frequency sweep slopes, and the dual-loop phase-locked loop can adapt to different application requirements.
The present disclosure is described in detail below with reference to the accompanying drawings.
Fig. 3 is a circuit block diagram of a dual-loop phase-locked loop according to an embodiment of the disclosure, fig. 4 is a schematic diagram of a structure of a second loop filter used in the dual-loop phase-locked loop shown in fig. 3, fig. 5 is a circuit block diagram of a voltage generator in the second loop filter shown in fig. 4, and fig. 6 is a circuit block diagram of a first loop filter on an integration path in the dual-loop phase-locked loop shown in fig. 3.
Referring to fig. 3, an embodiment of the present disclosure provides a dual loop Phase Locked Loop (PLL)200 that may be adapted to synthesize a local oscillator signal of a radio frequency transceiver, such as a mobile telephone. In this embodiment, the dual-loop phase-locked loop 200 at least includes: a phase frequency detector 210, an integration path 230, a proportional path 220, and a voltage controlled oscillator 240.
Wherein the voltage controlled oscillator 240 has a power terminal b and a control terminal a for generating a high frequency clock signal fout;
the phase frequency detector 210 is configured to detect a phase difference Φ between a phase of the high frequency clock signal fout and a phase of the reference signal fref, and generate an integrated signal representing an integrated value of the phase difference Φ and a proportional signal representing a current value of the phase difference Φ;
the integration path 230 comprises a first charge pump 231 and a first loop filter 232 for receiving the aforementioned integration signal and supplying an adjusted integration signal Vco1 to the power supply terminal b of the aforementioned voltage-controlled oscillator 240;
the proportional path 220 includes a second charge pump 221 and a second loop filter 222 for receiving the proportional signal and supplying an adjusted proportional signal Vco2 to a control terminal a of the Vco 240,
the second loop filter 222 is configured to receive an input voltage VDD, generate an offset voltage Vdiff according to a change of a frequency sweep slope, and adjust a potential of an input node of the second loop filter 222 according to the offset voltage Vdiff, so as to maintain a potential of an output voltage (i.e., a proportional signal Vco2, the same applies below) of the second loop filter 222 during a frequency sweep of the dual loop phase locked loop 200,
the aforementioned voltage-controlled oscillator 240 generates a high-frequency clock signal fout having an oscillation frequency controlled by both the adjusted integration signal Vco1 and the adjusted proportional signal Vco2 such that the phase of the high-frequency clock signal fout is locked to the phase of the aforementioned reference signal fref.
In this embodiment, the Voltage Controlled Oscillator (VCO)240 generates the high frequency clock signal fout based on at least two controllable parameters, such as VCO1 and VCO2, which are separately controlled based on a proportional signal and an integral signal. And adjusts the frequency of the high frequency clock signal fout accordingly.
The frequency of the high frequency clock signal fout provided by the voltage controlled oscillator 240 is a function of the control voltage. Furthermore, the VCO has another controllable parameter. When the VCO has a ring oscillator topology including delay cells connected in series, for example, the number of delay cells, the size of the delay cells, the value of the load capacitance of the delay cells, the current through the delay cells, and the like may be used to control the frequency of the oscillation signal OUT. The proportional signal and the integral signal are used separately, for example, to adjust the control voltage and the size of the delay unit.
In another embodiment, the voltage controlled oscillator 240 may alternatively be implemented as an inductor-capacitor (LC) type oscillator. The frequency of the LC-type oscillator depends on the inductance and capacitance of the LC-type oscillator. In one example, the capacitance of the LC-type oscillator is determined in common by at least one variable capacitor and one capacitor bank. The variable capacitor has a voltage controlled capacitor, and the capacitor bank has a plurality of capacitors optionally included in an LC type oscillator. The proportional signal and the integral signal are used, for example, separately to control the capacitance of the variable capacitor and the number of capacitors selected in the capacitor bank.
Further, in this embodiment, the aforementioned dual-loop phase-locked loop 200 further includes:
a frequency divider 250, the frequency divider 250 coupled between the voltage controlled oscillator 240 and the phase frequency detector 210, for dividing the frequency of the high frequency clock signal fout to obtain a low frequency signal fb, wherein the phase frequency detector 210 detects the phase difference Φ by comparing the phase of the low frequency signal fb with the phase of the reference signal fref. In a swept frequency system, the frequency sweep of the output frequency is typically achieved by varying the input division ratio N (N is an integer) of the divider 250.
In the present embodiment, the phase frequency detector 210 receives the frequency-divided low frequency signal fb and the reference signal fref, and generates a pair of signals (the first control signal UP and the second control signal DN) having variable width pulses. The pulse width varies based on the phase difference phi between the divided low frequency signal fb and the reference signal fref. For example, when the divided low-frequency signal fb precedes the reference signal fref by a positive phase difference, the second control signal DN has a wider pulse width proportional to the positive phase difference; when the divided low-frequency signal fb lags the reference signal fref by a positive phase difference, the first control signal UP has a wider pulse width proportional to the positive phase difference.
Further, in this embodiment, the aforementioned two-loop phase-locked loop 200 may further include an external crystal oscillator 201, where the oscillator 201 is configured to provide a reference (frequency) signal fref.
Further, referring to fig. 4, in this embodiment, the second loop filter 222 includes: the voltage generator 2221 is configured to receive an input voltage VDD and generate a bias voltage Vdiff according to a change in frequency sweep slope, the filter circuit 2223 is configured to obtain the bias voltage Vdiff through an input node (a1 and a2) of the filter circuit 2223 and adjust a potential of the input node (a1 and a2) according to the bias voltage Vdiff to maintain a potential of an output voltage Vco2 of the second loop filter 222 on the proportional path 220 during a frequency sweep of the dual loop phase locked loop 200, and the gain amplifier 2222 is connected between an output terminal of the voltage generator 2221 and the input node (a1 and a2) of the filter circuit 2223 for performing gain amplification on the bias voltage Vdiff.
Further, in this embodiment, the input nodes of the second loop filter 222 include a first input node a1 and a second input node a2, and the filter circuit 2223 includes: a first resistor R1, a third resistor R3, a second resistor R2, a fourth resistor R4, a first capacitor C1 and a second capacitor C2,
the first resistor R1 and the third resistor R3 are connected in series between the first input node a1 and the first output node, the second resistor R2 and the fourth resistor R4 are connected in series between the second input node a2 and the second output node, the first output node and the second output node are used for providing the output voltage Vco2, the first end of the first capacitor C1 is connected to the connection node between the first resistor R1 and the third resistor R3, the second end of the first capacitor C1 is connected to the connection node between the second resistor R2 and the fourth resistor R4, the first end of the second capacitor C2 is connected to the first output node, and the second end of the second capacitor C2 is connected to the second output node.
In the present embodiment, referring to fig. 3 and fig. 4, the connection node of the first resistor R1 and the third resistor R3 in the second loop filter 222 is connected to the fifth output node of the second charge pump 221, the connection node of the second resistor R2 and the fourth resistor R4 is connected to the sixth output node of the second charge pump 221, and the first output node and the second output node of the second loop filter 222 are used to provide the output voltage Vco2 to the control terminal a.
Referring to fig. 5, in the present embodiment, the aforementioned voltage generator 2221 includes:
a switch resistance network which is provided with a plurality of fifth resistors R5 sequentially connected in series between the power supply end and the ground, and a switch element is connected to the connection node between any two adjacent fifth resistors R5,
during the frequency sweep, the two sequentially enabled switching elements of the dual-loop pll 200 are respectively connected to the first input node a1 and the second input node a2 to provide the aforementioned bias voltage Vdiff.
Further, in the present embodiment, the magnitude of the bias voltage Vdiff is a voltage value that makes the offset voltage amount of the output voltage Vco2 of the second loop filter 222 on the proportional path 220 become zero when the dual-loop phase locked loop 200 switches from the locked mode to the frequency sweep mode and operates at a predetermined frequency sweep slope.
Further, referring to fig. 6, in the present embodiment, the first loop filter 232 includes: a third capacitor C3 and a sixth resistor R6, and a fourth capacitor C4 and a seventh resistor R7,
a first end of the third capacitor C3 and a first end of the sixth resistor R6 are commonly connected to the third output node of the first charge pump 231, a second end of the third capacitor C3 is grounded, and a second end of the sixth resistor R6 is connected to the power terminal b; a second end of the fourth capacitor C4 and a first end of the seventh resistor R7 are commonly connected to ground, a first end of the fourth capacitor C4 is connected to the power terminal b, and a second end of the seventh resistor R7 is connected to the fourth output node of the first charge pump 231.
Specifically, as will be understood from the foregoing description, the second loop filter 222 for the dual-loop pll 200 provided in the embodiment of the present disclosure is obtained by adding an additional bias circuit to a loop filter structure on a conventional proportional path, and splitting the node a into two nodes a1 and a2, where the node a1 and the node a2 are equipotential points in the conventional mode, and the embodiment of the present disclosure uses a voltage generator 2221 to generate two bias voltages with a difference value of Vdiff, and pushes the two bias voltages through a unit gain amplifier 2222(unit gain buffer). The bias voltage Vdiff is a desired voltage predicted according to the slope of the frequency sweep and the characteristics of the phase-locked loop system, and the value of the desired voltage is determined by the following steps:
the method comprises the following steps:
1) fixing the potential of a node (A1/A2) in the second loop filter 222 on the proportional path 220 in the dual-loop PLL 200 to 0, so that the whole dual-loop PLL 200 works in a locked mode;
2) on the basis of the step 1, enabling the double-loop lock ring 200 to enter a frequency sweeping mode, wherein the frequency sweeping slope is set according to the current working environment requirement;
3) in the frequency sweep mode of the conventional dual-loop lock-up loop 100, the second charge pump 121 on the proportional path 120 has an offset of an output voltage, and the offset voltage amount Vdiff output by the second charge pump 121 on the proportional path 120 is measured;
4) the voltage difference controlled by the voltage generator 2221 is Vdiff, and the offset voltage between the first input node a1 and the second input node a2 is set to-Vdiff, at this time, the offset voltage on the proportional path 220 is the same as that in the lock mode, and is 0;
5) by repeating the steps 1) to 4), the required input voltage values on different frequency sweep slopes can be obtained, so that the dual-loop phase-locked loop 200 can adapt to different application requirements.
The second method comprises the following steps:
by analyzing the principle of the circuit structure of the second loop filter 222 shown in fig. 4, it can be known that:
sweep frequency phase difference
And
bias voltage
Wherein,
for the slope of the frequency sweep, C3 is represented as the capacitance of the first loop filter 232 on the integral path 230, R1 is the resistance of the second loop filter 222 on the proportional path 220, Icp1 is represented as the output current of the second charge pump 221 on the proportional path 220, and Kvco is represented as a parameter of the vco 240.
1) According to the formula (1), the phase difference phi generated by the dual-loop phase-locked loop 200 during frequency sweeping is known, and the phase difference phi is related to the following parameters: a frequency sweep slope ((framep)/(Δ T)), a magnitude of a capacitance C3 of the first loop filter 232 on the integration path 230, a resistance magnitude of the second loop filter 222 on the proportional path 220, a magnitude of a current Icp1 of the second charge pump 221 output node on the proportional path 220, and a parameter Kvco of the voltage controlled oscillator 240;
2) according to the formula (2), the magnitude of the bias voltage Vdiff in the second loop filter 222 is proportional to the slope of the frequency sweep and proportional to the output current of the second charge pump 221 on the proportional path 220, and according to the relationship between the phase difference Φ and the bias voltage Vdiff, the magnitude of the bias voltage Vdiff can be adjusted by adjusting the position of the gate switch (the number of the series-connected fifth resistors R5) in the voltage generator 2221, so as to compensate the offset phase;
3) after the phase compensation is carried out, the offset voltage Vdiff is zero, so that the frequency sweep mode is the same as the locking condition in the conventional (locking) mode;
4) by repeating the steps 1) -3), the size of the voltage generator 2221 (i.e., the bias voltage Vdiff) required for different frequency sweep slopes can be obtained, so that the dual-loop phase-locked loop 200 can adapt to different application requirements.
Therefore, the system parameters of the dual-loop phase-locked loop 200 provided by the embodiment of the disclosure can be accurately controlled, so that the stability and reliability of the phase-locked loop are greatly improved.
In the loop filter 122 on the proportional path 120 in the prior art, the node a is connected to a virtual ground, and the loop output voltage in the actual frequency sweeping state cannot be accurately controlled, so that parameter deviations occur in the design of a post-stage circuit and the whole system, and the system performance is deteriorated. In the embodiment of the disclosure, after the initial voltage (i.e., the bias voltage Vdiff) is applied to the second loop filter 222 on the proportional path 220, the system parameters can be precisely controlled, so that the stability, reliability and related performance parameters of the dual-loop phase-locked loop 200 are greatly improved.
To sum up, in the dual-loop phase-locked loop 200 provided in the embodiment of the present disclosure, the second loop filter 222 located on the proportional path 220 may receive the input voltage VDD by using the voltage generator 2221 and generate the bias voltage Vdiff according to the change of the slope of the frequency sweep; the offset voltage Vdiff is obtained through the input nodes (a1 and a2) of the filter circuit 2223, and the potentials of the input nodes a1 and a2 are adjusted according to the offset voltage Vdiff, so as to maintain the potential of the output voltage Vco2 of the second loop filter 222 located on the proportional path 220 during the frequency sweep of the dual-loop pll 200, and thus different initial voltages can be applied to the input nodes of the second loop filter 222 on the proportional path 220 according to the requirement of the slope of the frequency sweep, so that the system parameters can be precisely controlled, and the stability and reliability of the dual-loop pll 200 can be greatly improved.
It should be noted that in the description of the present disclosure, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientation or positional relationship, are only for convenience in describing the present disclosure and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure.
Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present disclosure, and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention as herein taught are within the scope of the present disclosure.
Claims (9)
1. A dual loop phase locked loop, comprising:
a voltage controlled oscillator having a power supply terminal and a control terminal for generating a high frequency clock signal;
a phase frequency detector for detecting a phase difference between a phase of the high frequency clock signal and a phase of a reference signal and generating an integral signal representing an integral value of the phase difference and a proportional signal representing a current value of the phase difference;
a first charge pump and a first loop filter in an integration path between the voltage controlled oscillator and the phase frequency detector for receiving the integrated signal and supplying a regulated integrated signal to a power supply terminal of the voltage controlled oscillator; and
a second charge pump and a second loop filter in a proportional path between the voltage controlled oscillator and the phase frequency detector for receiving the proportional signal and supplying an adjusted proportional signal to a control terminal of the voltage controlled oscillator,
wherein the second loop filter comprises:
the voltage generator is used for receiving input voltage and generating bias voltage according to the change of the frequency sweep slope;
a filter circuit for obtaining the bias voltage through an input node thereof and adjusting the potential of the input node according to the bias voltage to maintain the potential of the output voltage of the second loop filter located on the proportional path during the frequency sweep of the dual loop phase locked loop,
the voltage controlled oscillator generates a high frequency clock signal having an oscillation frequency controlled by both the adjusted integration signal and the proportional signal such that a phase of the high frequency clock signal is locked to a phase of the reference signal.
2. The dual loop phase locked loop of claim 1, further comprising:
a frequency divider coupled between the voltage-controlled oscillator and the phase frequency detector for dividing the frequency of the high-frequency clock signal to obtain a low-frequency signal,
wherein the phase frequency detector detects the phase difference by comparing a phase of the low frequency signal with a phase of the reference signal.
3. The loop filter of claim 2, further comprising:
and the gain amplifier is connected between the output end of the voltage generator and the input node of the filter circuit and is used for performing gain amplification on the bias voltage.
4. The loop filter of claim 3 wherein the input nodes of the second loop filter comprise a first input node and a second input node, the filtering circuit comprising:
a first resistor and a third resistor connected in series between the first input node and a first output node;
a second resistor and a fourth resistor connected in series between the second input node and a second output node, the first output node and the second output node for providing the output voltage;
a first capacitor, a first end of which is connected with a connection node of the first resistor and the third resistor, and a second end of which is connected with a connection node of the second resistor and the fourth resistor;
and a second capacitor, wherein a first end of the second capacitor is connected to the first output node, and a second end of the second capacitor is connected to the second output node.
5. The loop filter of claim 4, wherein the voltage generator comprises:
a switch resistance network, which is provided with a plurality of fifth resistors connected in series between the power supply end and the ground in sequence, and the connection node between any two adjacent fifth resistors is connected with a switch element,
in the frequency sweeping process of the double-loop phase-locked loop, the two sequentially-gated switch elements are respectively communicated to the first input node and the second input node to provide the bias voltage.
6. The loop filter of claim 5, wherein the bias voltage is of a magnitude such that when the dual loop phase locked loop switches from the locked mode to the swept mode phase and operates at a predetermined sweep slope, the offset voltage of the output voltage of the loop filter on the proportional path becomes zero.
7. The dual loop phase locked loop of claim 6, wherein the first loop filter comprises:
a first end of the third capacitor and a first end of the sixth resistor are connected with a third output node of the first charge pump together, a second end of the third capacitor is grounded, and a second end of the sixth resistor is connected to the power supply terminal;
a fourth capacitor and a seventh resistor, a second end of the fourth capacitor and a first end of the seventh resistor are commonly connected to ground, a first end of the fourth capacitor is connected to the power supply terminal, and a second end of the seventh resistor is connected to a fourth output node of the first charge pump.
8. The dual loop phase locked loop of claim 7, wherein a connection node of the first resistor and the third resistor in the second loop filter is connected to a fifth output node of the second charge pump, a connection node of the second resistor and the fourth resistor is connected to a sixth output node of the second charge pump, and the first output node and the second output node of the second loop filter are configured to provide the output voltage to the control terminal.
9. The dual loop phase locked loop of claim 8, wherein a magnitude of a bias voltage in the second loop filter is proportional to the frequency sweep slope and proportional to an output current of the first charge pump on the proportional path.
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| CN114499512B (en) | 2025-10-17 |
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Denomination of invention: Dual-loop phase-locked loop Granted publication date: 20251017 Pledgee: Bank of Hangzhou Limited by Share Ltd. science and Technology Branch Pledgor: Hangzhou Shengde Micro Integrated Circuit Technology Co.,Ltd. Registration number: Y2025980051122 |