CN114496815A

CN114496815A - SiP packaging design method of IPC monitoring chip

Info

Publication number: CN114496815A
Application number: CN202011160682.4A
Authority: CN
Inventors: 丁海松
Original assignee: Hefei Ingenic Technology Co ltd
Current assignee: Hefei Ingenic Technology Co ltd
Priority date: 2020-10-27
Filing date: 2020-10-27
Publication date: 2022-05-13

Abstract

The present invention provides a SiP package design method for an IPC monitoring chip, which fully utilizes the layout of the die in the package and adjusts the distribution sequence of the DDR PHY interface signal of the main control die, saves the RDL, and is bound to reduce the production cost of the IPC monitoring chip. More cost-effective and more competitive in marketing. The method includes the following steps: S1, determining the specifications of the chip SiP memory die; S2, collecting position information of each solder joint map of signals on the memory die; S3, adjusting the master control die according to the information collected in S2 when designing the back end of the master control die The position of the solder joints of the memory PHY interface keeps the solder joints of the main control die DDR memory PHY interface in the same order as the interface solder joints of the memory die; S4, place the main control die and the memory die on the same level on the substrate, through the bonding wire Realize the main control die memory PHY one-by-one mapping and wiring to the memory die.

Description

SiP packaging design method of IPC monitoring chip

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a SiP packaging design method of an IPC monitoring chip.

Background

The integrated circuit can be divided into an application-specific integrated circuit and a general-purpose integrated circuit, i.e., a specific chip and a general-purpose chip. The special chip has the characteristics of high reliability, good performance, high function utilization rate and the like, and the universal chip has the characteristics of strong universality, high portability, good expansibility and the like.

With the development of electronic engineering, the development of a single component from the beginning gradually enters a stage of integrating a plurality of components into a system. Under the requirements of high performance and light and thin appearance of products, chips with different functions begin to step towards the integration stage. During this period, the development and breakthrough of packaging technology has become one of the forces for promoting integration, and the concept of SiP has been proposed. SiP, a packaging technology, refers to a technology that a plurality of chips die are collected in a single package, so that the chips can obtain system functions.

The electronic devices in the IPC monitoring products in the current market mainly comprise a main control chip, a system operation memory chip, a storage chip for storing operation programs, a network transmission chip, an image sensor chip and the like. The interconnection lines of the main control chip and the memory chip on the PCB are complex, the memory chip occupies a large PCB area, in order to simplify and facilitate the PCB hardware design of the IPC monitoring product and reduce the development cost, the IPC monitoring chip generally adopts the SiP technology to seal the main control chip die and the memory DDR chip die into one chip, the current common SiP stacking mode of the IPC monitoring chip is as shown in the attached drawing 1, the main control die1 is on the top, and the memory DDR die4 is on the bottom. However, the pressure pads of the existing common memory DDR die4 are located in the middle of the die, which requires the RDL 2 (as shown in fig. 2 for example) to arrange the pressure pads to the edge of the die, so that the DDR PHY interface of the main control die and the memory die bonding wire 4 can be interconnected conveniently.

At present, the market competition of the IPC monitoring chip is intense, and how to reduce the cost of the IPC monitoring chip and realize the basically unchanged function becomes the demand of wide attention increasingly.

Commonly used technical terms in the prior art include:

SIP (System In a Package) is a packaging scheme that integrates multiple functional wafers, including functional wafers such as processors and memories, into one Package according to factors such as application scenarios and the number of layers of a Package substrate, thereby achieving a basic complete function.

die, a wafer die, is a very small unit of silicon wafer that includes a single chip designed to be complete and a portion of the scribe line area of the chip adjacent to the horizontal and vertical directions. Grains are small irregularly shaped crystals constituting a polycrystal, and each grain sometimes consists of a number of sub-grains slightly different in orientation. The average diameter of the grains is typically in the range of 0.015 to 0.25mm, while the average diameter of the sub-grains is typically of the order of 0.001 mm.

RDL: the abbreviation of Redistribution Layer rewiring Layer is that the pads can be rearranged to any reasonable position on the wafer die. Conventional through die center pads may be redistributed to die perimeter using RDL techniques.

IPC: IP Camera, which is a new generation of video cameras generated by combining conventional video cameras with internet technology, is an abbreviation, IP is internet protocol, Camera is a Camera, and IP Camera, as its name implies, is a webcam.

PCB: the acronym of Printed Circuit Board is an important electronic component, which is a support for electronic components and a carrier for electrical connection of electronic components. It is called a "printed" circuit board because it is made using electronic printing.

Memory PHY: in the physical layer of the memory, the MAC and PHY are integrated into one chip in common network card chips, but at present, the south bridge chip of many motherboards already includes the ethernet MAC control function, and only does not provide a physical layer interface, so the PHY chip needs to be externally connected to provide an access channel of the ethernet. Such PHY network chips are commonly called "soft network card chips", and commonly used PHY function chips include RTL8201BL, VT6103, and the like.

Bonding wires: the core material for semiconductor packaging is a component for connecting a lead pin and a silicon wafer and transmitting an electric signal.

Routing: also called Wire Bonding, also called Bonding, Wire Bonding, means that a metal Wire (gold Wire, aluminum Wire, etc.) is used to complete the connection of the interconnection wires inside the solid-state circuit in the microelectronic device, i.e. the connection between the chip and the circuit or the lead frame, by using a heat pressing or ultrasonic energy source. Commonly found in surface mount processes such as the COB process.

Disclosure of Invention

In order to solve the above problems, the method aims to: the method for designing the SiP package makes full use of the layout of die in the package and adjusts the signal distribution sequence of the main control die DDR PHY interface, saves RDL, and can reduce the production and manufacturing cost of an IPC monitoring chip, so that the method has higher cost performance and is more competitive in market popularization.

Specifically, the invention provides a SiP packaging design method of an IPC monitoring chip, which comprises the following steps:

s1, determining the specification of chip SiP memory die;

s2, collecting the position information of each welding point diagram of the signal on the memory die;

s3, adjusting the position of the main control die memory PHY interface welding spot when the main control die back end is designed according to the information collected in S2, so that the position of the main control die DDR memory PHY interface welding spot is consistent with the sequence of the interface welding spot of the memory die;

and S4, placing the main control die and the memory die on the same level on the substrate, and realizing one-to-one mapping routing of the main control die memory PHY to the memory die through the bonding wire.

In S2, the positions of each of the signal pads on the memory die are interface pads including a0, a1, a2, A3, a4, a5, and a6 pad positions.

In S3, the main control die memory PHY interface pads include pad positions a0, a1, a2, a3, a4, a5, and a 6.

And the main control die and other signals of the memory die in the S3 are processed similarly through the interconnection welding point of the bonding wire.

In S4, the substrate may be replaced by a frame, and the package substrate or frame is a carrier for each wafer die in the SiP package.

In S4, the layout of die in the package and the distribution sequence of the DDR PHY interface signals of the main control die memory are adjusted, so that the signal pads of the main control die and the memory die are mapped one by one, and the main control die and the memory die are directly connected by bonding wires.

In the method, a packaging substrate is a carrier for packaging a wafer die in the packaging substrate, and other signals related to the main control die and the memory die are wire-bonded to the packaging substrate through bonding wires and then connected to solder balls to form the chip package; the master control die is a main signal processing unit of the IPC chip; the memory die is a DDR memory unit operated by an IPC system; the DDR PHY interface welding spot is positioned at the edge of the master control die, is designed and distributed at the rear end of the master control die and carries out information interaction with the memory die; the bonding wire is an interconnection wire of a main control die DDR PHY interface welding spot and a memory die interface welding spot.

Thus, the present application has the advantages that: the embodiment of the invention provides an IPC monitoring SiP chip and an encapsulation method thereof, which fully utilize the layout of die in the encapsulation and adjust the signal distribution sequence of a DDR PHY interface of a main control die memory, save RDL, definitely reduce the production and manufacturing cost of the IPC monitoring chip, and ensure that the IPC monitoring chip has higher cost performance and higher competitiveness in market popularization.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention.

Fig. 1 is a schematic side view of a SiP package structure of a common IPC monitoring chip in the market.

FIG. 2 is a schematic top view of a DDR die RDL of an IPC monitor chip.

FIG. 3 is a schematic side view of an embodiment of an IPC monitoring chip SiP package structure.

FIG. 4 is a schematic top view of an IPC monitoring chip SiP package structure according to an embodiment of the present invention.

FIG. 5 is a schematic flow chart of the IPC monitoring chip SiP package according to the embodiment of the present invention.

Fig. 6 is a schematic flow chart of a method according to an embodiment of the present method.

Detailed Description

In order that the technical contents and advantages of the present invention can be more clearly understood, the present invention will now be described in further detail with reference to the accompanying drawings.

The embodiment of the invention provides a packaging design scheme of an IPC monitoring chip SiP, which comprises the following steps: the packaging substrate, a main control die and a memory die4 which are positioned on the packaging substrate, DDR PHY interface welding spots and bonding wires. The packaging substrate is a carrier for packaging the wafer die in the packaging substrate, and other signals related to the main control die and the memory die are wire-bonded to the packaging substrate through bonding wires and then connected to the welding balls to form the chip package; the master control die is a main signal processing unit of the IPC chip; the memory die is a DDR memory unit operated by an IPC system; the DDR PHY interface welding spot is positioned at the edge of the master control die, is designed and arranged at the rear end of the master control die and carries out information interaction with the memory die; the bonding wire is an interconnection wire of a main control die DDR PHY interface welding spot and a memory die interface welding spot.

As shown in fig. 6, an embodiment of the method of the present application includes the following steps:

s1, determining the specification of the chip SiP memory die 4;

s2, collecting the position information of each welding point diagram of the signals in the memory die 4;

s3, adjusting the position of the main control die memory PHY interface welding spot 8 when the main control die1 rear end is designed according to the information collected in S2, so that the sequence of the main control die DDR memory PHY interface welding spot position 8 and the sequence of the main control die interface welding spot 7 are kept consistent;

and S4, placing the main control die1 and the memory die4 on the same level on the substrate, and realizing one-to-one mapping routing of the main control die memory PHY to the memory die through the bonding wire 3.

In the embodiment of the present invention, the specification of the chip SiP memory die4 is first determined, and the position information of each solder point diagram of signals in the memory die4 is studied (as shown in fig. 4, 7 shows solder point positions of a0, a1, a2, A3, a4, a5, a6, and the like, and other signals in the memory die4 are similar). Accordingly, when the main control die1 is designed at the back end, the positions of the main control die memory PHY interface pads 8 are adjusted (as shown in fig. 4, pad positions such as a0, a1, a2, a3, a4, a5, a6, and the like are processed similarly with other pad interconnections of the main control die1 and the memory die4 through bonding wires), so that the sequence of the main control die DDR memory PHY interface pad positions 8 and the interface pads 7 of the memory die are kept consistent. As shown in fig. 3, the main control die1 and the memory die4 are placed on the same level on the substrate, and the bonding wires 3 can implement the one-to-one mapping routing of the main control die memory PHY to the memory die, so as to save RDL 2 and achieve the purpose of interconnection, thereby reducing the cost of the IPC monitoring chip.

Further, as shown in fig. 5, first, the memory die specification is determined; secondly, researching the position of a signal welding spot of the memory die; thirdly, the master control die and the memory die are placed on the substrate in the same horizontal direction; and finally, adjusting the position of the corresponding signal welding spot of the main control die to enable the main control die and the signal welding spots of the memory die to be mapped and corresponding one by one.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes may be made to the embodiment of the present invention by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. a SiP package design method of IPC monitoring chip, is characterized in that, described method may further comprise the steps:

S1, determine the specifications of the chip SiP memory die (4);

S2, collect the position information of each solder joint map of the signal on the memory die (4);

S3, according to the information collected in S2, adjust the position of the main control die memory PHY interface solder joint (8) when designing the back end of the main control die (1), so that the main control die DDR memory PHY interface solder joint position (8) and the memory die The sequence of the interface solder joints (7) shall be consistent;

S4, the main control die (1) and the memory die (4) are placed on the same level on the substrate, and the main control die memory PHY is mapped to the memory die one by one through the bonding wire (3).

2. the SiP package design method of a kind of IPC monitoring chip according to claim 1, is characterized in that, in described S2, each solder joint map position of signal on described memory die is that interface solder joint (7) comprises A0 , A1, A2, A3, A4, A5, A6 solder joint positions.

3. The SiP package design method of an IPC monitoring chip according to claim 1, wherein in said S3, said main control die memory PHY interface solder joint (8) comprises a0, a1, a2, a3, a4, a5, a6 solder joint positions.

4. the SiP package design method of a kind of IPC monitoring chip according to claim 1, is characterized in that, in described S3, main control die (1) and other signals of memory die (4) interconnect solder joints through bonding wires Similar processing.

5. the SiP packaging design method of a kind of IPC monitoring chip according to claim 1, is characterized in that, in described S4, described substrate can be replaced by frame, and described packaging substrate or frame is each wafer crystal in SiP package. particle carrier.

6. The SiP package design method of a kind of IPC monitoring chip according to claim 1, is characterized in that, in described S4, utilizes the layout of die in the package and adjusts the distribution order of main control die memory DDR PHY interface signals, so that The signal pads of the main control die and the memory die are mapped one-to-one, so that the two are directly connected by bonding wires.

7. the SiP package design method of a kind of IPC monitoring chip according to claim 1, is characterized in that, in the described method, the package substrate is the carrier of the wafer die inside the package, and other signals related to the main control die and the memory die pass through the key The bonding wire is connected to the packaging substrate, and then connected to the solder balls to form the chip package as seen; the main control die is the main signal processing unit of the IPC chip; the memory die is the DDR memory unit running in the IPC system; The DDR PHY interface solder joint is located on the edge of the main control die, and is designed and arranged by the back end of the main control die to exchange information with the memory die; the bonding wire is the main control die DDRPHY interface solder joint and memory die interface solder joint interconnecting wires.