CN114461546A - Memory control method and device, storage medium and electronic equipment - Google Patents

Abstract

The embodiments of the present application provide a memory control method, device, storage medium, and electronic device. The present application uses the feature of acquiring data from the memory when the processor cache is missing by obtaining the number of cache misses per unit time in the cache of the processor. , and further obtain the target bandwidth required by the memory according to the number of cache misses. The target bandwidth reflects the actual demand for the data volume of the processor to access the memory, so that the memory bandwidth can be adjusted to the target bandwidth to meet the processor's access requirements to the memory. . Compared with the related art, the present application does not select from several fixed bandwidth widths, but analyzes the actual bandwidth requirements of the memory, so as to adjust the bandwidth of the memory in real time according to the actual bandwidth requirements, so as to meet the needs of the memory. Access performance usage requirements. At the same time, since the bandwidth after adjusting the memory is matched with the actual bandwidth requirement, there is no waste of bandwidth, and waste of power consumption can also be avoided.

Description

Memory control method, device, storage medium and electronic device

technical field

The present application relates to the technical field of processors, and in particular, to a memory control method, apparatus, storage medium and electronic device.

Background technique

Memory, also known as internal memory or main memory, is used to temporarily store operational data in the processor and data exchanged with external memory. Electronic devices such as smart phones, tablet computers and other electronic devices are usually configured with memory, and all applications deployed by the electronic devices are executed in the memory, so the processor needs to access the memory frequently. The access performance of the processor to the memory depends on the bandwidth that the memory can provide. The higher the bandwidth, the higher the corresponding access performance, but the higher the power consumption.

SUMMARY OF THE INVENTION

The embodiments of the present application provide a memory control method, apparatus, storage medium and electronic device, which can not only meet the usage requirements for memory access performance, but also avoid waste of power consumption.

The present application discloses a memory control method, including:

Get the number of cache misses in the processor's cache per unit time;

The target bandwidth required to obtain memory according to the number of cache misses;

Adjust the bandwidth of the memory to the target bandwidth.

The present application also discloses a memory control device, comprising:

A quantity acquisition module, which is used to acquire the number of cache misses within a unit time of the cache in the processor;

a bandwidth obtaining module, configured to obtain the target bandwidth required to be provided by the memory according to the number of cache misses;

A bandwidth adjustment module, configured to adjust the bandwidth of the memory to the target bandwidth.

The present application also discloses a storage medium on which a computer program is stored, and when the computer program is loaded by a processor, the memory control method provided by the present application is executed.

The present application also discloses an electronic device including a processor, a memory and a memory, wherein the memory stores a computer program, and the processor executes the memory control method provided by the present application by loading the computer program.

In the embodiment of the present application, by obtaining the number of cache misses of the cache in the processor per unit time, using the feature of acquiring data from the memory when the processor cache misses, and further obtaining the target bandwidth required by the memory according to the number of cache misses, The target bandwidth reflects the actual demand for the amount of data the processor needs to access the memory, so that the memory bandwidth can be adjusted to the target bandwidth to meet the processor's demand for memory access. Compared with the related art, the present application does not select from several fixed bandwidth widths, but analyzes the actual bandwidth demand of the memory, so as to adjust the bandwidth of the memory in real time according to the actual bandwidth demand, so as to meet the needs of the memory. Access performance usage requirements. At the same time, since the bandwidth after adjusting the memory is matched with the actual bandwidth requirement, there is no waste of bandwidth, and waste of power consumption can also be avoided.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the accompanying drawings that are used in the description of the embodiments.

FIG. 1 is a schematic flowchart of a memory control method provided by the present application.

FIG. 2 is a schematic diagram of a processor accessing a memory according to an embodiment of the present application.

FIG. 3 is another schematic diagram of a processor accessing a memory in an embodiment of the present application.

FIG. 4 is another schematic flowchart of the memory control method provided by the present application.

FIG. 5 is a schematic structural diagram of a memory control device provided by the present application.

FIG. 6 is a schematic structural diagram of an electronic device provided by the present application.

Detailed ways

The technical solutions provided in the embodiments of the present application can be applied to various scenarios where data communication is required, which is not limited in the embodiments of the present application.

Referring to FIG. 1 , the present application provides a memory control method, a memory control device, a storage medium, and an electronic device. The execution body of the memory control method may be the memory control apparatus provided in the embodiments of the present application, or an electronic device integrating the memory control apparatus, where the memory control apparatus may be implemented in hardware or software. Wherein, the electronic device may be a mobile electronic device such as a smart phone, a tablet computer, a palmtop computer, and a notebook computer, or a stationary electronic device such as a desktop computer and an advertising machine.

Please refer to FIG. 1. FIG. 1 is a schematic flowchart of a memory control method provided by an embodiment of the present application. A specific process of the memory control method provided by an embodiment of the present application may be as follows:

In 110, the number of cache misses per unit time period of the cache in the processor is obtained.

It should be noted that, referring to FIG. 2, a cache, or cache memory, is usually configured in the processor, and its function is to better utilize the principle of locality (including temporal locality and spatial locality), that is, the most recent The data in the memory accessed by the processor will also be accessed by the processor in the short term (temporal locality); other data near the data accessed by the processor will also be accessed by the processor in the short term (spatial locality). Therefore, if the processor caches the data that has just been accessed in the cache, then the next time the processor accesses it, the processor can directly fetch it from the cache without having to fetch it from the memory, so that the access speed of the processor can be improved by an order of magnitude. improvement.

Based on the above related descriptions, when the data to be accessed by the processor is cached in the cache, it is called a "hit", and when the data to be accessed by the processor is not cached in the cache, it is called a "miss". Based on this, in the present application, firstly, the cache misses in the cache in the processor in a unit duration (the unit duration can be obtained from an empirical value according to actual needs by those of ordinary skill in the art, for example, the unit duration can be configured as 1 second) The number of cache misses is obtained. , that is, the number of times that the processor needs to access data that is not cached in the cache when the processor accesses data within a unit time. For example, in a unit duration of 1 second, the processor accesses the cache 10,000 times, of which 5,000 access data is cached in the cache, while the other 5,000 access data is not cached in the cache, and needs to be accessed from the memory. Reads, therefore, can get a cache miss count of 5000.

In 120, the target bandwidth required to be provided by the memory is obtained according to the number of cache misses.

As mentioned above, it can be understood that for the data missing from the cache, the processor needs to obtain the required data from the memory, and whether the processor can stably obtain the required data from the memory depends on whether the memory can provide enough bandwidth. For example, if the amount of data required by the processor from the memory in one second per unit time is 512Mb, the memory needs to provide at least 512Mb/s of bandwidth in order for the processor to access it stably.

It can be seen from the above that the number of cache misses per unit time of the cache is positively related to the bandwidth required by the memory, that is, the larger the number of cache misses in the cache, the greater the bandwidth required by the memory, and when the cache The smaller the number of cache misses, the less bandwidth the memory needs to provide. Therefore, the bandwidth required by the memory can be obtained according to the number of cache misses in the cache per unit time, and the bandwidth required by the processor to access the memory is recorded as the target bandwidth.

At 130, the bandwidth of the memory is adjusted to the target bandwidth.

According to the above related descriptions, it can be understood that the memory provides the target bandwidth for the processor to access stably, that is to say, when the bandwidth provided by the memory is less than the target bandwidth, the memory cannot ensure the stable access of the processor, and when the bandwidth provided by the memory is less than the target bandwidth When the bandwidth provided by the memory is greater than the target bandwidth, the bandwidth provided by the memory will be wasted. Therefore, in the embodiment of the present application, after obtaining the target bandwidth required by the processor to access the memory according to the number of cache misses in the cache per unit time, the bandwidth of the memory can be adjusted to the aforementioned target bandwidth, thereby ensuring processing This ensures stable access to memory by the server without wasting bandwidth.

It can be seen from the above that the present application obtains the number of cache misses of the cache in the processor per unit time, and utilizes the feature of acquiring data from the memory when the processor cache misses, and further obtains the target bandwidth required by the memory according to the number of cache misses, The target bandwidth reflects the actual demand for the amount of data the processor needs to access the memory, so that the memory bandwidth can be adjusted to the target bandwidth to meet the processor's demand for memory access. Compared with the related art, the present application does not select from several fixed bandwidth widths, but analyzes the actual bandwidth demand of the memory, so as to adjust the bandwidth of the memory in real time according to the actual bandwidth demand, so as to meet the needs of the memory. Access performance usage requirements. At the same time, since the bandwidth after adjusting the memory is matched with the actual bandwidth requirement, there is no waste of bandwidth, and waste of power consumption can also be avoided.

Optionally, in an embodiment, when the processor includes a performance monitoring unit, acquiring the number of cache misses of the cache in the processor within a unit duration, including:

Obtains the number of cache misses per unit time from the cache in the processor from the performance monitoring unit.

It should be noted that, for some models of processors, a performance monitoring unit is provided, and the performance monitoring unit is a hardware module for recording processor access information, as shown in FIG. 3 . For example, a processor of the ARM architecture is usually configured with a performance monitoring unit, which is used to record the number of data accessed by the processor in the cache within a unit time, and the number of accessed data that is not in the cache.

Therefore, in this embodiment of the present application, when the processor includes a performance monitoring unit, the number of cache misses within a unit duration of the cache in the processor may be directly obtained from the performance monitoring unit.

Optionally, in an embodiment, when the processor does not include a performance monitoring unit, acquiring the number of cache misses of the cache in the processor within a unit duration, including:

(1) Obtain the access delay of the processor accessing the target data within a unit time, and obtain multiple access delays;

(2) Predicting the number of cache misses within a unit time length of the cache in the processor according to multiple access delays.

It should be noted that the memory is hierarchical. The closer the memory is to the processor, the faster the access speed, the higher the cost per byte, and the smaller the capacity. The register is closest to the CPU and has the fastest access speed, followed by the cache (the cache is also hierarchical, such as the first level cache, the second level cache, the third level cache, etc.), and then the main memory (ie memory). Generally, the access latency of the processor to the first level cache is 5-10 nanoseconds, the access delay of the processor to the second level cache is 40-60 nanoseconds, and the access delay of the processor to the memory is 100-150 nanoseconds second. Therefore, the access delay required by the processor to access data can roughly determine whether the processor is accessing the memory or the cache, and then the number of cache misses in the cache can be predicted.

Wherein, when the processor does not include the performance monitoring unit, the number of cache misses in the cache per unit time cannot be directly obtained from the performance monitoring unit. Therefore, in the embodiment of the present application, when the processor accesses the target data, the The spent access delay is recorded, wherein the target data accessed by the processor each time may be the same or different. Correspondingly, when acquiring the number of cache misses in the cache of the processor within a unit time, the access delay of the processor accessing the target data recorded in the unit time can be obtained, and multiple access delays can be obtained. For example, in a unit duration of 1 second, 10,000 access delays of the processor to the target data are recorded, and correspondingly, 10,000 access delays will be obtained.

Based on the above related descriptions, the lengthening of the access time can reflect to a certain extent that the target data accessed by the processor is located in the cache or in the memory. Therefore, in the embodiment of the present application, the default configuration 1 is used to determine whether the target data is located in the cache. The cache is also the delay threshold in the memory, which is recorded as the preset delay threshold, which can be configured by those of ordinary skill in the art according to the actual read and write performance of the cache and memory. The value of the preset delay threshold is not specifically limited here. .

Correspondingly, after obtaining the multiple access delays recorded in the unit time, the number of access delays greater than or equal to the preset delay threshold among the multiple access delays can be further determined, and the number is set as the high speed. The number of cache misses cached per unit duration. For example, a total of 10,000 access delays recorded in a unit duration are obtained. If 2,000 access delays are greater than or equal to the preset delay threshold, it can be determined that the number of cache misses in the cache per unit duration is 2,000.

Optionally, in an embodiment, adjusting the bandwidth of the memory to the target bandwidth includes:

(1) According to the corresponding relationship between bandwidth and clock frequency, obtain the target clock frequency required by the memory to provide the target bandwidth;

(2) Adjust the clock frequency of the memory to the target clock frequency to adjust the bandwidth of the memory to the target bandwidth.

It should be noted that the bandwidth provided by the memory has the following correspondence with its clock frequency:

Bandwidth=clock frequency×bus bits×multiplication factor/8;

Taking DDR400 memory as an example, its operating frequency is 200MHz and the number of bus bits is 64bit. Since data is transmitted on both the rising and falling edges, the multiplication factor is 2, and the bandwidth is: 200×64×2/8=3.2GB /s.

Among them, the number of bits of the bus and the multiplication factor of the memory are fixed. When the hardware circuit of the memory is determined, the number of bits of the bus and the multiplication factor of the memory are determined accordingly. In other words, by changing the clock frequency at which the memory runs, you can change the bandwidth provided by the memory.

Correspondingly, in the embodiment of the present application, when the bandwidth of the memory is adjusted to the target bandwidth, the clock frequency corresponding to the aforementioned target bandwidth can be obtained according to the corresponding relationship between the above bandwidth and the clock frequency, which is recorded as the memory required to provide the target bandwidth. target bandwidth. After that, adjusting the clock frequency of the memory operation to the target clock frequency, the bandwidth provided by the memory can be adjusted to the target bandwidth.

Optionally, in an embodiment, after adjusting the clock frequency of the memory to the target clock frequency, the method further includes:

According to the preset corresponding relationship between the clock frequency and the working voltage, the working voltage of the memory is adjusted to the target working voltage corresponding to the target clock frequency.

It should be noted that whether the memory can work stably at a clock frequency depends on whether a corresponding working voltage is provided to the memory, which is related to the hardware circuit of the memory itself.

Therefore, for a memory, the working voltage required for stable operation at different clock frequencies can be pre-calibrated, thereby obtaining the preset corresponding relationship between the clock frequency and the working voltage.

In the embodiment of the present application, in order to ensure that the memory can stably work at the adjusted target bandwidth, the working voltage corresponding to the aforementioned target clock frequency is also determined according to the preset corresponding relationship between the clock frequency and the working voltage, which is recorded as the target voltage . Then, the working voltage of the memory is adjusted to the target working voltage corresponding to the target clock frequency.

Optionally, in an embodiment, obtaining the target bandwidth required to be provided by the memory according to the number of cache misses includes:

(1) According to the number of cache misses and the data volume of cache lines in the cache, obtain the required data bandwidth for the processor to access the memory within a unit time;

(2) Obtain the cleaning bandwidth required for the cache to perform the cleaning operation within a unit time;

(3) Obtain the aforementioned target bandwidth according to the data bandwidth and the cleaning bandwidth.

The cleaning operation refers to: for the dirty (that is, overwritten) cache line data in the cache, forcibly writing it into the memory, and clearing the dirty bit in the cache line.

Correspondingly, in the embodiment of the present application, when obtaining the target bandwidth required by the memory according to the number of cache misses, the required bandwidth for accessing the memory within a unit time can be obtained according to the number of cache misses and the data volume of the cache line in the cache. Bandwidth, denoted as data bandwidth. It should be noted that each time the processor reads data from the memory, the data is obtained according to the data amount of the cache line.

For example, the data volume of each cache line in the cache is 32 bytes. If the number of cache misses in the cache per unit duration is 5000, then the amount of data accessed by the processor in the unit duration 1 second is 5000* 32=160000 (bytes), correspondingly, the data bandwidth required by the processor to access the memory within 1 second per unit time is 160000 bytes/second.

As mentioned above, in addition to the normal access of the processor to the memory that requires bandwidth, when the cache is cleaned up, the corresponding data in the cache needs to be written to the memory, and the write operation to the memory will also occupy the bandwidth of the memory. , therefore, also obtains the cleaning bandwidth required by the cache unit to perform the cleaning operation within a unit time.

After the above data bandwidth and cleaning bandwidth are obtained, the target bandwidth required by the memory can be obtained according to the foregoing data bandwidth and cleaning bandwidth. For example, the bandwidth and value of the aforementioned data bandwidth and cleanup bandwidth can be directly calculated as the target bandwidth that the memory needs to provide.

Optionally, in an embodiment, acquiring the target bandwidth according to the data bandwidth, the first operating bandwidth, and the second operating bandwidth includes:

(1) Calculate the sum of data bandwidth and cleanup bandwidth and set it as a candidate bandwidth;

(2) obtaining the application type of the foreground application run by the processor, and determining the target correction coefficient corresponding to the aforementioned application type according to the preset correspondence between the application type and the correction coefficient;

(3) Modify the candidate bandwidth according to the target correction coefficient, and set the corrected candidate bandwidth as the target bandwidth.

It should be noted that when the processor runs different types of applications, the processor's memory bandwidth requirements vary to a different degree. For example, when the processor is running a class A application, the processor's memory bandwidth requirements vary to a lesser extent. When the processor is running a class B application, the processor's memory bandwidth requirements vary to a greater extent. Based on this, the present application performs statistics on the degree of change of memory bandwidth requirements when the processor runs different types of application programs in advance, and allocates correction coefficients accordingly. Wherein, with the positive correlation between the correction coefficient and the degree of change as a constraint, a person of ordinary skill in the art can allocate the correction coefficient according to actual needs, thereby forming a corresponding relationship between the application type and the correction coefficient.

Correspondingly, when obtaining the target bandwidth required to be provided by the memory according to the data bandwidth and the cleaning bandwidth, the sum of the aforementioned data bandwidth and the aforementioned bandwidth may be calculated first, and the calculated sum value may be recorded as the candidate bandwidth provided by the memory; then, Further obtain the application type of the foreground application run by the processor, and determine the correction coefficient corresponding to the application type of the foreground application according to the preset application type and correction coefficient, which is recorded as the target correction coefficient; correction, which can be expressed as:

W'=W*r;

Among them, W represents the candidate bandwidth, W' represents the modified candidate bandwidth, and r represents the target correction coefficient.

As above, after the modification of the candidate bandwidth is completed, the modified candidate bandwidth is set as the target bandwidth required to be provided by the memory.

FIG. 4 is another schematic flowchart of a memory control method provided by an embodiment of the present application. The following description is given by taking an example where the execution body of the memory control method is a processor in an electronic device. As shown in FIG. 4 , the process of the memory control method provided by the embodiment of the present application may be as follows:

In 210, the processor obtains, from the performance monitoring unit, the number of cache misses in the cache within a unit duration.

It should be noted that, referring to FIG. 3 , a cache, or cache memory, is usually configured in the processor, and its function is to make better use of the principle of locality (including temporal locality and spatial locality), that is, the most recent The data in the memory accessed by the processor will also be accessed by the processor in the short term (temporal locality); other data near the data accessed by the processor will also be accessed by the processor in the short term (spatial locality). Therefore, if the processor caches the data that has just been accessed in the cache, then the next time the processor accesses it, the processor can directly fetch it from the cache without having to fetch it from the memory, so that the access speed of the processor can be improved by an order of magnitude. improvement.

Based on the above related descriptions, when the data to be accessed by the processor is cached in the cache, it is called a "hit", and when the data to be accessed by the processor is not cached in the cache, it is called a "miss". Based on this, in the present application, firstly, the cache misses in the cache in the processor in a unit duration (the unit duration can be obtained from an empirical value according to actual needs by those of ordinary skill in the art, for example, the unit duration can be configured as 1 second) The number of cache misses is obtained. , that is, the number of times that the processor needs to access data that is not cached in the cache when the processor accesses data within a unit time. For example, in a unit duration of 1 second, the processor accesses the cache 10,000 times, of which 5,000 access data is cached in the cache, while the other 5,000 access data is not cached in the cache, and needs to be accessed from the memory. Reads, therefore, can get a cache miss count of 5000.

It should be noted that, for some models of processors, a performance monitoring unit is provided, and the performance monitoring unit is a hardware module for recording processor access information, as shown in FIG. 3 . For example, a processor of the ARM architecture is usually configured with a performance monitoring unit, which is used to record the number of data accessed by the processor in the cache within a unit time, and the number of accessed data that is not in the cache.

Therefore, in this embodiment of the present application, when the processor includes a performance monitoring unit, the number of cache misses within a unit duration of the cache in the processor may be directly obtained from the performance monitoring unit.

In 220, the processor obtains the data bandwidth required by the processor to access the memory within a unit time period according to the number of cache misses and the data amount of the cache line in the cache.

As mentioned above, it can be understood that for the data missing from the cache, the processor needs to obtain the required data from the memory, and whether the processor can stably obtain the required data from the memory depends on whether the memory can provide enough bandwidth. For example, if the amount of data required by the processor from the memory in one second per unit time is 512Mb, the memory needs to provide at least 512Mb/s of bandwidth in order for the processor to access it stably.

It can be seen from the above that the number of cache misses per unit time of the cache is positively related to the bandwidth required by the memory, that is, the larger the number of cache misses in the cache, the greater the bandwidth required by the memory, and when the cache The smaller the number of cache misses, the less bandwidth the memory needs to provide.

It should be noted that in addition to normal access operations that consume memory bandwidth, cache cleanup operations also consume memory bandwidth. Therefore, in this embodiment of the present application, the target bandwidth required to be provided by the processor is determined according to the access operation of the processor and the cleaning operation of the cache.

Correspondingly, in the embodiment of the present application, when obtaining the target bandwidth required by the memory according to the number of cache misses, the required bandwidth for accessing the memory within a unit time can be obtained according to the number of cache misses and the data volume of the cache line in the cache. Bandwidth, denoted as data bandwidth. It should be noted that each time the processor reads data from the memory, the data is obtained according to the data amount of the cache line.

For example, the data volume of each cache line in the cache is 32 bytes. If the number of cache misses in the cache per unit duration is 5000, then the amount of data accessed by the processor in the unit duration 1 second is 5000* 32=160000 (bytes), correspondingly, the data bandwidth required by the processor to access the memory within 1 second per unit time is 160000 bytes/second.

In 230, the processor obtains the flushing bandwidth required by the cache to perform the flushing operation per unit time.

As mentioned above, in addition to the normal access of the processor to the memory that needs to occupy the bandwidth, the memory bandwidth is also occupied when the cache cleaning operation is performed. Therefore, the cleaning bandwidth required by the cache unit to perform the cleaning operation per unit time is also obtained. .

At 240, the processor calculates the sum of the data bandwidth and the cleaning bandwidth as a candidate bandwidth.

It should be noted that when the processor runs different types of applications, the processor's memory bandwidth requirements vary to a different degree. For example, when the processor is running a class A application, the processor's memory bandwidth requirements vary to a lesser extent. When the processor is running a class B application, the processor's memory bandwidth requirements vary to a greater extent. Based on this, the present application performs statistics on the degree of change of memory bandwidth requirements when the processor runs different types of application programs in advance, and allocates correction coefficients accordingly. Wherein, with the positive correlation between the correction coefficient and the degree of change as a constraint, a person of ordinary skill in the art can allocate the correction coefficient according to actual needs, thereby forming a corresponding relationship between the application type and the correction coefficient.

Correspondingly, the sum of the foregoing data bandwidth and the foregoing bandwidth may be calculated first, and the calculated sum may be recorded as the candidate bandwidth required to be provided by the memory.

In 250, the processor obtains the application type of the foreground application running by itself, and determines the target correction coefficient corresponding to the application type according to the preset correspondence between the application type and the correction coefficient.

The processor further acquires the application type of the foreground application running by itself, and determines the correction coefficient corresponding to the application type of the foreground application according to the preset application type and correction coefficient, which is recorded as the target correction coefficient.

In 260, the processor modifies the candidate bandwidth according to the target modification coefficient, and sets the modified candidate bandwidth as the target bandwidth.

The candidate bandwidth is modified according to the target modification coefficient, which can be expressed as:

W'=W*r;

Among them, W represents the candidate bandwidth, W' represents the modified candidate bandwidth, and r represents the target correction coefficient.

As above, after the modification of the candidate bandwidth is completed, the modified candidate bandwidth is set as the target bandwidth required to be provided by the memory.

In 270, the processor obtains the target clock frequency required by the memory to provide the target bandwidth according to the corresponding relationship between the bandwidth and the clock frequency, and adjusts the clock frequency of the memory to the target clock frequency, so as to adjust the bandwidth of the memory to the target bandwidth.

It should be noted that the bandwidth provided by the memory has the following correspondence with its clock frequency:

Bandwidth=clock frequency×bus bits×multiplication factor/8;

Taking DDR400 memory as an example, its operating frequency is 200MHz, and the number of bus bits is 64bit. Since data is transmitted on both the rising and falling edges, the multiplication factor is 2. At this time, the bandwidth is: 200×64×2/8=3.2GB /s.

Among them, the number of bus bits and the multiplication factor of the memory are fixed, and when the hardware circuit of the memory is determined, the number of bits of the bus and the multiplication factor are determined accordingly. In other words, by changing the clock frequency at which the memory runs, you can change the bandwidth provided by the memory.

Correspondingly, in the embodiment of the present application, when the bandwidth of the memory is adjusted to the target bandwidth, the clock frequency corresponding to the aforementioned target bandwidth can be obtained according to the corresponding relationship between the above bandwidth and the clock frequency, which is recorded as the memory required to provide the target bandwidth. target bandwidth. After that, adjust the clock frequency of the memory operation to the target clock frequency, and the bandwidth provided by the memory can be adjusted to the target bandwidth.

In 280, the processor adjusts the operating voltage of the memory to a target operating voltage corresponding to the target clock frequency according to the preset correspondence between the clock frequency and the operating voltage.

It should be noted that whether the memory can work stably at a clock frequency depends on whether a corresponding working voltage is provided to the memory, which is related to the hardware circuit of the memory itself.

Therefore, for a memory, the working voltage required for stable operation at different clock frequencies can be pre-calibrated, thereby obtaining the preset corresponding relationship between the clock frequency and the working voltage.

In the embodiment of the present application, in order to ensure that the memory can stably work at the adjusted target bandwidth, the working voltage corresponding to the aforementioned target clock frequency is also determined according to the preset corresponding relationship between the clock frequency and the working voltage, which is recorded as the target voltage . Then, the working voltage of the memory is adjusted to the target working voltage corresponding to the target clock frequency.

Please refer to FIG. 5 , which is a schematic structural diagram of a memory control apparatus provided by an embodiment of the present application. The memory control device is applied to the electronic equipment provided in this application. As shown in Figure 5, the memory control device may include:

A quantity acquisition module 310, configured to acquire the cache miss quantity of the cache in the processor within a unit time length;

a bandwidth obtaining module 320, configured to obtain the target bandwidth required to be provided by the memory according to the number of cache misses;

The bandwidth adjustment module 330 is configured to adjust the bandwidth of the memory to the target bandwidth.

Optionally, in an embodiment, if the processor includes a performance monitoring unit, when acquiring the number of cache misses of the cache in the processor within a unit duration, the number acquiring module 310 is configured to:

Get the number of cache misses from the performance monitoring unit.

Optionally, in an embodiment, if the processor does not include a performance monitoring unit, when acquiring the number of cache misses of the cache in the processor within a unit duration, the number acquiring module 310 is configured to:

Obtain the access delay of the processor accessing the target data within a unit time, and obtain multiple access delays;

Predict the number of cache misses based on multiple access latencies.

Optionally, in an embodiment, when adjusting the bandwidth of the memory to the target bandwidth, the bandwidth adjustment module 330 is configured to:

According to the corresponding relationship between bandwidth and clock frequency, obtain the target clock frequency required by the memory to provide the target bandwidth;

Adjust the clock frequency of the memory to the target clock frequency to adjust the bandwidth of the memory to the target bandwidth.

Optionally, in an embodiment, after adjusting the clock frequency of the memory to the target clock frequency, the bandwidth adjustment module 330 is further configured to:

According to the preset corresponding relationship between the clock frequency and the working voltage, the working voltage of the memory is adjusted to the target working voltage corresponding to the target clock frequency.

Optionally, in an embodiment, when acquiring the target bandwidth required to be provided by the memory according to the number of cache misses, the bandwidth acquiring module 320 is configured to:

According to the number of cache misses and the data volume of cache lines in the cache, obtain the data bandwidth required by the processor to access the memory in a unit time;

Obtain the cleaning bandwidth required for the cache to perform cleaning operations within a unit time;

Get target bandwidth based on data bandwidth and cleaning bandwidth.

Optionally, in an embodiment, when obtaining the target bandwidth according to the data bandwidth and the cleaning bandwidth, the bandwidth obtaining module 320 is configured to:

Calculate the sum of data bandwidth and cleanup bandwidth and set it as a candidate bandwidth;

Acquire the application type of the foreground application run by the processor, and determine the target correction coefficient corresponding to the application type according to the preset correspondence between the application type and the correction coefficient;

The candidate bandwidth is corrected according to the target correction coefficient, and the corrected candidate bandwidth is set as the target bandwidth.

It should be noted that the memory control device provided by the embodiments of the present application and the memory control method in the above embodiments belong to the same concept, and the memory control device can execute any method provided in the memory control method embodiment, and the specific implementation process is detailed. See the above related embodiments, and details are not repeated here.

Embodiments of the present application further provide a storage medium on which a computer program is stored, and when the stored computer program is loaded by a processor of an electronic device, the steps in the memory control method provided by the embodiments of the present application are executed. The storage medium may be a magnetic disk, an optical disk, a read only memory (Read Only Memory, ROM), or a random access device (Random Access Memory, RAM), or the like.

An embodiment of the present application further provides an electronic device. Referring to FIG. 6 , the electronic device includes a processor 410 and a memory 420 .

The processor in this embodiment of the present application is a general-purpose processor 410, such as a processor of an ARM architecture.

A computer program is stored in the memory 420, which may be a high-speed random access memory, or a non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage devices.

The memory 430 can be any type of memory (also called main memory), which is higher than DDR (Double Data Rate, double data rate) memory.

In addition, the memory 420 may also include a memory controller to provide access to the memory 420 by the processor 410, and the processor 410 implements the following functions by loading a computer program in the memory 420:

Get the number of cache misses in the processor's cache per unit time;

The target bandwidth required to obtain the memory 430 according to the number of cache misses;

Adjust the bandwidth of the memory 430 to the target bandwidth.

Optionally, in an embodiment, if the processor includes a performance monitoring unit, when acquiring the number of cache misses of the cache in the processor within a unit duration, the processor 410 is configured to execute:

Get the number of cache misses from the performance monitoring unit.

Optionally, in an embodiment, if the processor does not include a performance monitoring unit, when acquiring the number of cache misses of the cache in the processor within a unit duration, the processor 410 is configured to execute:

Obtain the access delay of the processor accessing the target data within a unit time, and obtain multiple access delays;

Predict the number of cache misses based on multiple access latencies.

Optionally, in an embodiment, when adjusting the bandwidth of the memory 430 to the target bandwidth, the processor 410 is configured to execute:

According to the corresponding relationship between the bandwidth and the clock frequency, obtain the target clock frequency required by the memory 430 to provide the target bandwidth;

The clock frequency of the memory 430 is adjusted to the target clock frequency to adjust the bandwidth of the memory 430 to the target bandwidth.

Optionally, in an embodiment, after adjusting the clock frequency of the memory 430 to the target clock frequency, the processor 410 is further configured to execute:

According to the preset corresponding relationship between the clock frequency and the working voltage, the working voltage of the memory 430 is adjusted to the target working voltage corresponding to the target clock frequency.

Optionally, in an embodiment, when acquiring the target bandwidth required to be provided by the memory 430 according to the number of cache misses, the processor 410 is configured to execute:

Obtain the required data bandwidth for the processor to access the memory 430 within a unit time according to the number of cache misses and the data amount of the cache line in the cache;

Obtain the cleaning bandwidth required for the cache to perform cleaning operations within a unit time;

Get target bandwidth based on data bandwidth and cleaning bandwidth.

Optionally, in an embodiment, when acquiring the target bandwidth according to the data bandwidth and the cleaning bandwidth, the processor 410 is configured to execute:

Calculate the sum of data bandwidth and cleanup bandwidth and set it as a candidate bandwidth;

Acquire the application type of the foreground application run by the processor, and determine the target correction coefficient corresponding to the application type according to the preset correspondence between the application type and the correction coefficient;

The candidate bandwidth is corrected according to the target correction coefficient, and the corrected candidate bandwidth is set as the target bandwidth.

It should be noted that the electronic device provided by the embodiment of the present application and the memory control method in the above embodiment belong to the same concept, and any method provided in the memory control method embodiment can be executed on the electronic device, and the specific implementation process is detailed. See the above embodiments, and details are not repeated here.

A memory control method, a storage medium, and an electronic device provided by the embodiments of the present application have been described in detail above. The principles and implementations of the present application are described with specific examples. The descriptions of the above embodiments are only used for Help to understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation and application scope. In summary, the content of this specification does not It should be understood as a limitation of this application.

Claims (10)

1. a memory control method, is characterized in that, described memory control method comprises: Get the number of cache misses in the processor's cache per unit time; The target bandwidth required to obtain memory according to the number of cache misses; Adjust the bandwidth of the memory to the target bandwidth. 2 . The memory control method according to claim 1 , wherein, when the processor includes a performance monitoring unit, the acquiring the number of cache misses of the cache in the processor within a unit time length comprises: 2 . The number of cache misses is acquired from the performance monitoring unit. 3 . The memory control method according to claim 1 , wherein, when the processor does not include a performance monitoring unit, the acquiring the number of cache misses of the cache in the processor within a unit time length comprises: 3 . Obtain the access delay of the processor accessing the target data within a unit time, and obtain multiple access delays; The number of cache misses is predicted according to the plurality of access delays. 4. The memory control method according to claim 1, wherein the adjusting the bandwidth of the memory to the target bandwidth comprises: According to the corresponding relationship between the bandwidth and the clock frequency, obtain the target clock frequency required by the memory to provide the target bandwidth; The clock frequency of the memory is adjusted to the target clock frequency to adjust the bandwidth of the memory to the target bandwidth. 5. The memory control method according to claim 4, wherein after adjusting the clock frequency of the memory to the target clock frequency, the method further comprises: According to the preset corresponding relationship between the clock frequency and the working voltage, the working voltage of the memory is adjusted to a target working voltage corresponding to the target clock frequency. 6 . The memory control method according to claim 1 , wherein acquiring the target bandwidth required by the memory according to the number of cache misses comprises: 6 . According to the number of cache misses and the data amount of the cache line of the cache, obtain the data bandwidth required by the processor to access the memory within a unit time; Obtain the cleaning bandwidth required by the cache to perform the cleaning operation within a unit time; The target bandwidth is obtained according to the data bandwidth and the cleaning bandwidth. 7. The memory control method according to claim 6, wherein the acquiring the target bandwidth according to the data bandwidth and the cleaning bandwidth comprises: Calculate the sum of the data bandwidth and the cleaning bandwidth, and set it as a candidate bandwidth; Acquire the application type of the foreground application run by the processor, and determine the target correction coefficient corresponding to the application type according to the preset correspondence between the application type and the correction coefficient; The candidate bandwidth is modified according to the target modification coefficient, and the modified candidate bandwidth is set as the target bandwidth. 8. A memory control device, wherein the memory control device comprises: A quantity acquisition module, which is used to acquire the number of cache misses within a unit time of the cache in the processor; a bandwidth obtaining module, configured to obtain the target bandwidth required to be provided by the memory according to the number of cache misses; A bandwidth adjustment module, configured to adjust the bandwidth of the memory to the target bandwidth. 9. A storage medium on which a computer program is stored, characterized in that, when the computer program is loaded by a processor, the memory control method according to any one of claims 1-7 is executed. 10. An electronic device, comprising a processor, a memory and a memory, wherein the memory stores a computer program, wherein the processor executes the method according to any one of claims 1-7 by loading the computer program memory control method.

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