CN114448604B

CN114448604B - Hybrid parallel computing encryption and decryption system, transmitter device and receiver device

Info

Publication number: CN114448604B
Application number: CN202110998474.XA
Authority: CN
Inventors: 林义雄; 陈浩铭; 林友钦
Original assignee: Leedarson Lighting Co Ltd
Current assignee: Leedarson Lighting Co Ltd
Priority date: 2020-10-30
Filing date: 2021-08-27
Publication date: 2025-04-04
Anticipated expiration: 2041-08-27
Also published as: TW202218372A; CN114448604A

Abstract

The present application relates to the field of encryption technology, and specifically provides a hybrid parallel computing encryption and decryption system, including a transmitting end device and a receiving end device, wherein the transmitting end device includes a data generation module and a data encryption module, wherein the data encryption module obtains at least one data packet from the data generation module, encrypts the data packet via a fourth-order encryptor, and then outputs an encrypted sequence. The receiving end device includes a data target module and a data decryption module. The data decryption module obtains the encrypted sequence from the transmitting end device, decrypts the encrypted sequence via a fourth-order decryptor, and then outputs the restored data packet to the data target module.

Description

Mixed parallel operation encryption and decryption system, transmitting end device and receiving end device

Technical Field

The application relates to the technical field of encryption and provides an encryption and decryption system, a transmitting end device and a receiving end device.

Background

The advanced encryption standard (Advanced Encryption Standard, AES), also known in cryptography as Rijndael encryption, is a segment encryption standard adopted by the federal government in the united states. This standard is used to replace the original DES, has been analyzed by multiple parties and is widely used worldwide.

Advanced encryption standards have been subject to numerous hacking attempts, with 128-bit versions of keys having 10 cycles of encryption, 192-bit versions of keys having 12 cycles of encryption, and 256-bit versions of keys having 14 cycles of encryption. By 2006, the most notable attacks were made for the 128-bit key version of the 7 encryption cycles, the 192-bit key version of the 8 encryption cycles, and the 256-bit key version of the 9 encryption cycles of AES. As the efficiency of hardware increases, it is estimated that the day of completely breaking AES with brute force attacks is not far apart.

Furthermore, with the continued upgrade of hardware, artificial intelligence is now sufficient to reach the stage of the commercialization hierarchy. With the processing capabilities of hard devices and the powerful computing power of artificial intelligence, encryption standards widely used today are likely to be broken through artificial intelligence by way of extensive computation. For the above reasons, improvements to existing encryption techniques are needed.

Disclosure of Invention

In order to solve the above problems, the present application provides a hybrid parallel computing encryption and decryption system, which includes a transmitting end device and a receiving end device. The data generation module comprises an encryption level setting device and a fourth-order encryptor, wherein the fourth-order encryptor comprises a parallel stream encryptor, a sixty-four bit stream encryptor, a hundred twenty-eight bit stream encryptor and a two hundred fifty-six bit stream encryptor which are sequentially connected, the encryption level setting device is used for selecting an encryption level, the data encryption module obtains at least one data packet from the data generation module, and the fourth-order encryptor encrypts the data packet according to the encryption level and then outputs an encryption sequence. The receiving end device comprises a data target module and a data decryption module, wherein the data decryption module comprises a decryption level setter and a fourth-order decryptor, the fourth-order decryptor comprises a parallel stream decryptor, a sixty-four bit stream decryptor, a hundred twenty-eight bit stream decryptor and a two hundred fifty-six bit stream decryptor which are sequentially connected, the decryption level corresponds to the encryption level, the decryption level is selected, the data decryption module obtains the encryption sequence from the transmitting end device, and the fourth-order decryptor decrypts the encryption sequence according to the decryption level and outputs the restored data packet.

The application further provides a transmitting end device which comprises a data generating module and a data encrypting module. The data encryption module comprises an encryption level setting device and a fourth-order encryptor, wherein the fourth-order encryptor comprises a parallel stream encryptor, a sixty-four bit stream encryptor, a hundred twenty-eight bit stream encryptor and a two hundred fifty-six bit stream encryptor which are sequentially connected, the encryption level setting device is used for selecting an encryption level, the data encryption module obtains at least one data packet from the data generation module, and the fourth-order encryptor encrypts the data packet according to the encryption level and then outputs an encryption sequence.

The application further provides a receiving end device which comprises a data target module and a data decryption module. The data decryption module comprises a decryption level setter and a fourth-order decryptor, wherein the fourth-order decryptor comprises a parallel stream decryptor, a sixty-four bit stream decryptor, a hundred twenty-eight bit stream decryptor and a two hundred fifty-six bit stream decryptor which are sequentially connected, the decryption level corresponds to an encryption level, the decryption level is selected, the data decryption module obtains an encryption sequence from a transmitting end device, and the fourth-order decryptor decrypts the encryption sequence according to the decryption level and outputs a restored data packet.

Therefore, compared with the prior art, the application can adjust the secret key to be an internal secret key or an external secret key according to the required encryption mode and adjust the encryption hierarchy according to the requirement, and can realize different encryption modes through one set of hardware.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic block diagram (a) of a hybrid parallel computing encryption and decryption system according to an embodiment of the present application.

Fig. 2 is a schematic block diagram (two) of a hybrid parallel computing encryption and decryption system according to an embodiment of the present application.

Fig. 3 is a schematic block diagram of a parallel-stream encryptor according to an embodiment of the present application.

Fig. 4 is a schematic block diagram of an encryption key setter according to an embodiment of the present application.

Fig. 5 is a schematic block diagram of an encryption input controller according to an embodiment of the present application.

Fig. 6 is a schematic diagram of a logic operation of a parallel-serial stream encryptor according to an embodiment of the present application.

Fig. 7 is a schematic diagram of a logic operation of a fourth-order encryptor according to an embodiment of the present application.

Fig. 8 is a schematic block diagram of a parallel stream decryptor according to an embodiment of the present application.

Fig. 9 is a schematic block diagram of a decryption key setter according to an embodiment of the present application.

Fig. 10 is a schematic block diagram of a decryption input controller according to an embodiment of the present application.

Fig. 11 is a logic operation diagram of a parallel stream decryptor according to an embodiment of the present application.

Fig. 12 is a schematic diagram of a logic operation of a fourth-order decryptor according to an embodiment of the present application.

Fig. 13 is a schematic flow chart of a hybrid parallel operation encryption and decryption system according to an embodiment of the present application.

Fig. 14 is a flowchart of a fourth-order encryptor according to an embodiment of the present application.

Fig. 15 is a flowchart of a fourth-order decryptor according to an embodiment of the present application.

100 Parts of a mixed parallel operation encryption and decryption system, 10 parts of a transmitting end device, 12 parts of a data generating module, 14 parts of a data encrypting module, 142 parts of an encryption level setter, 144 parts of a fourth-order encryptor, 1442 parts of a parallel stream encryptor, 14422 parts of an eight-bit encryption operand generator, 14422L parts of an encryption linear feedback shift register, 14422G parts of a generated encryption logic gate, 14424 parts of a sixteen-bit encryption operand generator, 14424L parts of an encryption linear feedback shift register, 14424G parts of a generated encryption logic gate, 14426 parts of a thirty-two-bit encryption operand generator, 14426L parts of an encryption linear feedback shift register, 14426G parts of a generated encryption logic gate, 1442O parts of an external encryption key input device, 14422O parts of an encryption key generator, 14424O parts of an encryption controller, 1442I parts of an internal decryption key storage, G1 parts of an encryption logic operation unit, G12 parts of an encryption logic operation module, G14 parts of a data encryption logic gate, 1444 parts of a sixty four-bit encryption linear feedback shift register, 1444L parts of an encryption linear feedback shift register, 1444G, 1444 parts of an encryption linear feedback shift register, 1446 parts of a generated encryption logic gate, 1446 parts of a 1446L parts of a generated encryption logic gate, 1446 parts of a generated encryption logic gate, 14426, a three-bit linear feedback shift register, 1448 parts of a linear feedback shift register, a 1448 part of a linear input device, 14426L parts of a linear feedback input device, 24422, a linear decryption key generator, a 2438O parts of an encryption key generator, a 35O parts of an encryption logic input device, a 8 parts of an encryption logic 24426G, generating a decryption logic gate; 2442O external decryption key input, 24422O decryption key generator, 24424O decryption controller, 2442I internal decryption key storage, G2 decryption logic operator, G22 decryption logic operation module, G24 data decryption logic gate, 2444 sixty-four bit stream decryptor, 2444L decryption linear feedback shift register, 2444G decryption logic gate, 2446 one hundred twenty-eight bit stream decryptor, 2446L decryption linear feedback shift register, 2446G decryption logic gate, 2448 two hundred-fifty bit stream decryptor, 2448L decryption linear feedback shift register, 2448G decryption logic gate, 246 decryption key setter, 30 encryption input controller, 32 encryption input controller, 34 encryption input controller, 40 decryption input controller, 42 decryption input controller, 44 decryption controller, A1 encryption operand, B1 encryption operand, C1 encryption operand, D1 encryption operand, E1 encryption, F2 encryption operand, A2 encryption operand, B2 encryption operand, ES2 decryption operand sequence ES2 encryption operand sequence ES2, and sequence ES2 encryption operand.

Detailed Description

The detailed description and technical content of the present application will now be described with reference to the drawings. In the following, a preferred embodiment of the present application is described with reference to fig. 1, which is a schematic block diagram (one) of a parallel operation encryption/decryption system according to the present application, as shown in the following:

The present embodiment mainly provides a hybrid parallel computing encryption and decryption system 100, which is used for encrypting and decrypting data transmitted by a plurality of devices when the devices transmit data to each other. The Device for generating data or receiving data may be a Computer (Computer), a Server (Server), a Mobile Device (Mobile Device), an internet of things Device (such as a monitor, a television, a cloud hard disk, a lamp), a mass production Device or a machine, etc., which is not limited in the present application. The device is defined as a transmitting end device 10 as a data transmitting source and a receiving end device 20 corresponding to the transmitting end device 10 for receiving data of the transmitting end device 10 according to the receiving and transmitting relation of signals in the present application. It should be noted that the present application is not limited to the transmitting device 10 only performing the data encryption function and the receiving device 20 only performing the data decryption function, and specifically, the transmitting device 10 and the receiving device 20 generally both have the functions of encrypting and decrypting at the same time, so as to ensure that the data are encrypted or decrypted by the keys of each other in the bidirectional transmission process, which must be described in the foregoing.

The transmitting device 10 and the receiving device 20 can transmit data via a wired or wireless network.

In a preferred embodiment, the transmitting device 10 and the receiving device 20 can transmit data through the Internet (Internet), a local area network, or any wired or wireless communication port, which is not limited in the present application. In order to perform the functions of encrypting, decrypting and transmitting data, the transmitting device 10 and the receiving device 20 at least include a Processor (Processor), a storage unit, and a communication unit, which cooperate with each other to perform the corresponding functions, such as a physical network card, a wireless network card, a Bluetooth module (Bluetooth), a Zigbee module (Zigbee), etc., and the signal transmission mode and the transmission interface are not within the scope of the present application.

In one embodiment, the modules, devices, units, or combinations thereof and the corresponding functions thereof described in the hybrid parallel computing encryption/decryption system 100 of the present application may be cooperatively executed by a single chip or a combination of multiple chips, where the number of chip configurations is not within the scope of the present application. In addition, the chip may be, but is not limited to, a Processor, a central processing unit (Central Processing Unit, CPU), a Microprocessor (Microprocessor), a digital signal Processor (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuits (ASIC), programmable logic device (Programmable Logic Device, PLD), other similar devices or combinations of these devices that can process, convert, or use information or signals.

In one embodiment, the transmitting device 10 mainly includes a data generating module 12 and a data encrypting module 14. The data generation module 12 may be, for example, a Cache memory (Cache), a Dynamic Random Access Memory (DRAM), and a persistent memory (PERSISTENT MEMORY) for storing and managing data to be transferred and encrypted. The data encryption module 14 obtains at least one data packet from the data generation module 12, and the data encryption module 14 may be a processor or a microprocessor for performing encryption calculation processing, which is not limited in the present application. Finally, the data encryption module 14 outputs the encrypted data packet to the receiving device 20, where the encrypted data packet output by the data encryption module 14 is defined as an encryption sequence.

In one embodiment, referring to fig. 2, the data encryption module 14 includes an encryption hierarchy setter 142 and a fourth order encryptor 144. Wherein the output of the encryption hierarchy setter 142 is connected to the input of the fourth order encryptor 144. The encryption level setter 142 is used for selecting an encryption level of the fourth-order encryptor 144, and the fourth-order encryptor 144 encrypts the data packet according to the encryption level and outputs an encryption sequence.

In one embodiment, the data encryption module 14 further includes an encryption key setter 146, the output of the encryption key setter 146 being connected to the other input of the fourth-order encryptor 144, the encryption key setter 146 selecting either the external encryption key mode or the internal encryption key mode.

In one embodiment, the four-stage encryptor 144 includes a parallel stream encryptor 1442, a sixty-four bit stream encryptor 1444, a one hundred twenty-eight bit stream encryptor 1446, and a two hundred fifty-six bit stream encryptor 1448, which are connected in sequence. Referring to fig. 3, the parallel stream encryptor 1442 includes an eight-bit encryption operand generator 14422, a sixteen-bit encryption operand generator 14424, a thirty-two-bit encryption operand generator 14426, an external encryption key input 1422O, an internal encryption key store 1442I, and an encryption logic operator G1. The outputs of the encryption key setter 146 (here defined as eight-bit encryption operand generator 14422, sixteen-bit encryption operand generator 14424, and thirty-two-bit encryption operand generator 14426-collectively referred to as encryption operand generator) are coupled to the input of the external encryption key input 1442O and the output of the internal encryption key store 1442I, respectively, and the encryption key setter 146 is configured to select either the external encryption key mode or the internal encryption key mode. The external encryption key inputter 1442O is started and the external encryption key is output in the external encryption key mode, and the internal encryption key storage 1442I is started and the internal encryption key is output in the internal encryption key mode. The output end of the external encryption key input unit 1442O is connected to the input end of the encryption operand generator, the output end of the internal encryption key storage 1442I is connected to the other input end of the encryption operand generator, the encryption operand generator generates encryption operands according to the external encryption keys generated by the external encryption key input unit or the internal encryption keys stored by the internal encryption key storage, respectively, and the encryption operands and the data packets are operated by the encryption logic operator G1 to obtain a first encryption sequence ES1.

In one embodiment, referring to fig. 4, the eight-bit encryption operand generator 14422, the sixteen-bit encryption operand generator 14424, and the thirty-two-bit encryption operand generator 14426 respectively include an encryption Linear Feedback shift register (Linear Feedback SHIFT REGISTER, LFSR) and one or more generated encryption gates (Logic Gate), the encryption Linear Feedback shift register has the internal encryption key or the external encryption key, the encryption Linear Feedback shift register performs a logical operation on the internal encryption key or the plurality of encryption bit taps of the external encryption key to obtain the encryption operand, the encryption operand uses the first bit fed back to the encryption Linear Feedback shift register as an update of the encryption key, the update refers to the first bit of the encryption key input to the encryption Linear Feedback shift register, the first bit of the encryption key is moved to the second bit, the second bit of the original encryption key is moved to the third bit, and so on, the last bit of the encryption key is covered by the last bit of the encryption key, and so on. The eight-bit encryption operand generator 14422 includes an encryption linear feedback shift register 14422L (with eight-bit encryption keys a [1] through a [8], a [ n ] being the n-th bit of the eight-bit encryption key) and a generate encryption logic gate 14422G, the sixteen-bit encryption operand generator 14424 includes an encryption linear feedback shift register 14424L (with sixteen-bit encryption keys b [1] through b [16], b [ n ] being the n-th bit of the thirty-bit encryption key) and a generate encryption logic gate 14424G, the thirty-bit encryption operand generator 14426 includes an encryption linear feedback shift register 14426L (with thirty-bit encryption keys c [1] through c [32], c [ n ] being the n-th bit of the thirty-bit encryption key) and a generate encryption logic gate 14426G, wherein the eight-bit encryption key, the sixteen-bit encryption key and the thirty-bit encryption key may be internal encryption keys or external encryption keys. The encryption linear feedback shift register 14422L performs logic operation on a plurality of encryption bit taps of the eight-bit encryption key through the encryption generation logic gate 14422G to obtain an encryption operand A1, the encryption linear feedback shift register 14424L performs logic operation on a plurality of encryption bit taps of the sixteen-bit encryption key through the encryption generation logic gate 14424G to obtain an encryption operand B1, and the encryption linear feedback shift register 14426L performs logic operation on a plurality of encryption bit taps of the thirty-two-bit encryption key through the encryption generation logic gate 14426G to obtain an encryption operand C1.

In one embodiment, the generate encryption gates 14422G, 14424G, 14426G and the logical operations all use Exclusive Or (XOR) as the operations.

In one embodiment, the generating encryption logic 14422G, 14424G, 14426G AND the logic operation may be implemented by an AND gate, an OR gate, other logic gates, OR a combination of logic gates, which is not limited in this disclosure.

In one embodiment, the number of bits of the encrypted bit tap is two.

In one embodiment, the number of encryption bit taps may be an even number.

In one embodiment, referring to fig. 5, the external encryption key input unit 1442O includes an encryption key generator 14422O and an encryption controller 14424O. The encryption Key Generator 14422O may be, but is not limited to, a Key Generator (Key Generator), a random number Generator (Random Number Generator, RNG), a pseudo random number Generator (Pseudorandom Number Generator, PRNG), or the like, which may generate various sequences, and is not limited in the present application. The encryption key generator 14422O generates an external encryption key according to the external encryption key pattern. The encryption Controller 14424O may be, but is not limited to, a Controller (Controller) or other device capable of controlling signal output, and is not limited in this disclosure. The encryption controller 14424O outputs the external encryption key to the encryption operand generator according to the external encryption key mode.

In another embodiment, referring to fig. 6, the external encryption key inputter 1442O is an encryption input controller 30, and the encryption input controller 30 includes an encryption inputter 32 and an encryption controller 34. The encryption importer 32 may be, but is not limited to, an Input Device (Input Device), a Keyboard (Keyboard), a Computer (Computer), or other Device that can be used to provide data and control signals, without limitation in the present application. The encryption inputter 32 is used to input an external encryption key. The encryption Controller 34 may be, but is not limited to, a Controller (Controller) or other device capable of controlling signal output. The encryption controller 34 outputs the external encryption key to the encryption operand generator according to the input external encryption key and the external encryption key pattern.

In one embodiment, the internal encryption key storage 1424I may be, but is not limited to, a device such as persistent memory (PERSISTENT MEMORY) that can be used to store and manage data, which is not limited in this disclosure. The internal encryption key store 1424I outputs the internal encryption keys of the encryption operand generator according to an internal encryption key pattern.

In one embodiment, referring to fig. 3, the encryption logic operator G1 includes an encryption logic operation module G12 and a data encryption logic gate G14. The input end of the encryption logic operation module G12 is connected to the output end of the eight-bit encryption operand generator 14422, the output end of the sixteen-bit encryption operand generator 14424 and the output end of the thirty-two-bit encryption operand generator 14426, respectively, and the encryption logic operation module G12 receives the encryption operands A1, B1 and C1 and performs an operation to obtain a parallel encryption operand. The input end of the data encryption logic gate G14 receives the parallel encryption operand and the data packet, respectively, and the data encryption logic gate G14 is configured to encrypt the data packet via the parallel encryption operand and output a first encryption sequence ES1. The encryption Logic operation module G12 and the data encryption Logic Gate G14 are one or more Logic gates (Logic gates). All the logic gates use Exclusive Or (XOR) as the operation.

In one embodiment, the logic gate may be implemented as an AND gate, an OR gate, other logic gates, OR a combination of logic gates, without limitation in the present application.

In one embodiment, referring to fig. 7, the sixty-four bit stream encryptor 1444, the one hundred twenty-eight bit stream encryptor 1446 and the two hundred fifty-six bit stream encryptor 1448 respectively include an encryption Linear Feedback shift register (Linear Feedback SHIFT REGISTER, LFSR) and one or more encryption Logic gates (Logic Gate), the encryption Linear Feedback shift register has an encryption key, the encryption Linear Feedback shift register logically operates on a plurality of encryption bit taps of the encryption key through the encryption Logic Gate to obtain an encryption operand, the encryption operand uses a first bit fed back to the encryption Linear Feedback shift register as an update of the encryption key, the update refers to the first bit of the encryption key input to the encryption Linear Feedback shift register, the first bit of the encryption key is moved to a second bit, the second bit of the encryption key is moved to a third bit, and so on, the last bit of the encryption key is covered by the previous bit, thereby achieving the update of the encryption key. The sixty-four bit stream encryptor 1444 includes an encryption linear feedback shift register 1444L (with sixty-four bit encryption keys d [1] to d [64], d [ n ] being the nth bit of the sixty-four bit encryption key) and an encryption logic gate 1444G, the one hundred twenty-eight bit stream encryptor 1446 includes an encryption linear feedback shift register 1446L (with one hundred twenty-eight bit encryption keys e [1] to e [128], d [ n ] being the nth bit of the one hundred twenty-eight bit encryption key) and an encryption logic gate 1446G, and the two hundred fifty-six bit stream encryptor 1448 includes an encryption linear feedback shift register 1448L (with two hundred-fifty-six bit encryption keys f [1] to f [ n ], d [ n ] being the nth bit of the two hundred-fifty-six bit encryption key) and an encryption logic gate 1448G. The encryption linear feedback shift register 1444L performs logic operation on a plurality of encryption bit taps of the sixty-four bit encryption key through the encryption logic gate 1444G to obtain an encryption operand D1, the encryption linear feedback shift register 1446L performs logic operation on a plurality of encryption bit taps of the one hundred twenty eight bit encryption key through the encryption logic gate 1446G to obtain an encryption operand E1, and the encryption linear feedback shift register 1448L performs logic operation on a plurality of encryption bit taps of the two hundred fifty six bit encryption key through the encryption logic gate 1448G to obtain an encryption operand F1.

In one embodiment, the encryption logic gates 1444G, 1446G, 1448G and the logic operation all use Exclusive OR (XOR) as the operation.

In one embodiment, the encryption logic gates 1444G, 1446G, 1448G AND the logic operation may be implemented as AND gates, OR gates, other logic gates, OR a combination of logic gates, without limitation in the present application. In one embodiment, the number of bits of the encrypted bit tap is two.

In one embodiment, the number of encryption bit taps may be an even number.

In one embodiment, referring to fig. 1, the receiving end device 20 includes a data destination module 22 and a data decryption module 24. The data targeting module 22 may also be a Cache memory (Cache), dynamic Random Access Memory (DRAM), persistent memory (PERSISTENT MEMORY) for storing and managing received data. The data decryption module 24 may be a processor or microprocessor for performing decryption computation processing, and is not limited in this disclosure. Finally, the data decryption module 24 is configured to decrypt the received encrypted sequence in the internal decryption key mode and the external decryption key mode corresponding to the internal encryption key mode and the external encryption key mode, and then output the restored original data packet to the data destination module 22 for storage.

In one embodiment, referring to fig. 2, the data decryption module 24 includes a decryption level setter 242 and a fourth-order decryptor 244. Wherein the output of the decryption level setter 242 is connected to the input of the fourth-order decryptor 244. The decryption level setter 242 is configured to select a decryption level of the fourth-order decryptor 244, and the fourth-order decryptor 244 decrypts the encrypted sequence according to the decryption level and outputs the data packet.

In one embodiment, the data decryption module 24 further includes a decryption key setter 246, an output of the decryption key setter 246 being connected to another input of the fourth order decryptor 244, the decryption key setter 246 selecting either the external decryption key mode or the internal decryption key mode.

In one embodiment, the fourth order decryptor 244 includes a parallel stream decryptor 2442, a sixty-four bit stream decryptor 2444, a one hundred twenty-eight bit stream decryptor 2446, and a two hundred fifty-six bit stream decryptor 2448 connected in sequence. Referring to fig. 8, the parallel stream decryptor 2442 includes an eight-bit decryption operand generator 24422, a sixteen-bit decryption operand generator 24424, a thirty-two-bit decryption operand generator 24426, an external decryption key input 2442O, an internal decryption key storage 2442I, and a decryption logic operator G2. The outputs of the decryption key setter 246 (herein defined as eight-bit decryption operand generator 24422, sixteen-bit decryption operand generator 24424, and thirty-two-bit decryption operand generator 24426 collectively referred to as the decryption operand generator) are coupled to the input of the external decryption key input 2442O and the output of the internal decryption key store 2442I, respectively, and the decryption key setter 246 is configured to select either the external decryption key mode or the internal decryption key mode. The external decryption key inputter 2442O is started and the external decryption key is output when in the external decryption key mode, and the internal decryption key store 2442I is started and the internal decryption key is output when in the internal decryption key mode. The output end of the external decryption key input 2442O is connected to the input end of the decryption operand generator, the output end of the internal decryption key storage 2442I is connected to the other input end of the decryption operand generator, the decryption operand generator generates decryption operands according to the external decryption keys generated by the external decryption key input or the internal decryption keys stored by the internal decryption key storage, respectively, and the decryption operands and the first encryption sequence ES1 are operated by the decryption logic operator G2 to obtain restored data packets.

In one embodiment, referring to FIG. 9, eight-bit decryption operand generator 24422, sixteen-bit decryption operand generator 24424, Thirty-two bit decryption operand generator 24426 comprises a decryption Linear Feedback shift register (Linear Feedback SHIFT REGISTER, LFSR) and one or more generation decryption Logic gates (Logic gates), wherein the decryption Linear Feedback shift register has the internal decryption key or the external decryption key, the decryption Linear Feedback shift register performs Logic operation on a plurality of decryption bit taps of the internal decryption key or the external decryption key through the generation decryption Logic gates to obtain the decryption operand, the decryption operand uses the first bit fed back to the decryption Linear Feedback shift register as the update of the decryption key, the update means that the decryption operand is input to the first bit of the decryption key of the decryption Linear Feedback shift register, so that the first bit of the original decryption key is moved to the second bit, The second bit of the original decryption key is moved to the third bit, and so on, the last bit of the original decryption key is covered by the previous bit, thereby achieving the updating of the decryption key. The eight-bit decryption operand generator 24422 includes a decryption linear feedback shift register 24422L (which includes eight-bit decryption keys identical to eight-bit encryption keys a [1] to a [8], and which includes the same reference number as the eight-bit encryption keys) and generates a decryption logic gate 24422G, the sixteen-bit decryption operand generator 24424 includes a decryption linear feedback shift register 24424L (which includes sixteen-bit decryption keys identical to sixteen-bit encryption keys b [1] to b [16], and which includes the same reference number as the sixteen-bit encryption keys), and generates a decryption logic gate 24424G, the thirty-bit decryption operand generator 24426 includes a decryption linear feedback shift register 24426L (which includes thirty-bit decryption keys identical to thirty-bit encryption keys c [1] to c [32], and which includes the same reference number as the thirty-bit encryption keys) and generates a decryption logic gate 24426G, wherein the eight-bit decryption keys, the sixteen bit decryption key and the thirty-two bit decryption key may be an internal decryption key or an external decryption key. The decryption linear feedback shift register 24422L performs logic operation on a plurality of decryption bit taps of the eight-bit decryption key through the generation decryption logic gate 24422G to obtain a decryption operand A2, the decryption linear feedback shift register 24424L performs logic operation on a plurality of decryption bit taps of the sixteen-bit decryption key through the generation decryption logic gate 24424G to obtain a decryption operand B2, and the decryption linear feedback shift register 24426L performs logic operation on a plurality of decryption bit taps of the thirty-two-bit decryption key through the generation decryption logic gate 24426G to obtain a decryption operand C2. In principle, the generation decryption logic gates 24422G, 24424G, 24426G in the parallel stream decryptor 2442 must perform inverse logical operations with the parallel stream encryptor 1442 (e.g., the parallel stream encryptor 1442 is an AND gate, then the parallel stream decryptor 2442 is a NAND gate).

In one embodiment, the number of bits of the decrypted bit tap is two.

In one embodiment, the number of decryption bit taps may be an even number.

In one embodiment, referring to fig. 10, the external decryption key input 2442O includes a decryption key generator 24422O and a decryption controller 24424O. The decryption Key Generator 24422O may be, but is not limited to, a Key Generator (Key Generator), a random number Generator (Random Number Generator, RNG), a pseudo-random number Generator (Pseudorandom Number Generator, PRNG), or the like, which may generate various sequences, and is not limited in the present application. Decryption key generator 24422O generates an external decryption key from the external decryption key pattern. The decryption Controller 24424O may be, but is not limited to, a Controller (Controller) or other device capable of controlling signal output, which is not limited in the present application. The decryption controller 24424O outputs the external decryption key to the decryption operand generator according to the external decryption key pattern.

In another embodiment, referring to fig. 11, the external decryption key inputter 2442O is a decryption input controller 40, and the decryption input controller 40 includes the decryption inputter 42 and the decryption controller 44. The decryption Input 42 may be, but is not limited to, an Input Device (Input Device), a Keyboard (Keyboard), a Computer (Computer), or other Device that can be used to provide data and control signals, and is not limited in this disclosure. The decryption inputter 42 is used to input an external decryption key. Decryption Controller 44 may be, but is not limited to, a Controller (Controller) or other device capable of controlling signal output. The decryption controller 44 outputs the external decryption key to the decryption operand generator according to the input external decryption key and the external decryption key pattern.

In one embodiment, the internal decryption key storage 24242I may be, but is not limited to, a persistent memory (PERSISTENT MEMORY) or the like capable of storing and managing data, and is not limited in this disclosure. The internal decryption key store 24242I outputs the internal decryption key of the decryption operand generator in accordance with the internal decryption key pattern.

In one embodiment, referring to fig. 8, the decryption logic unit G2 includes a decryption logic unit G22 and a data decryption logic gate G24. The input end of the decryption logic operation module G22 is connected to the output end of the eight-bit decryption operand generator 24422, the output end of the sixteen-bit decryption operand generator 24424 and the output end of the thirty-two-bit decryption operand generator 24426, respectively, and the decryption logic operation module G22 receives the decryption operands A2, B2 and C2 and performs an operation to obtain a parallel decryption operand. The input end of the data decryption logic gate G24 receives the parallel decryption operand and the first encryption sequence ES1, respectively, and the data decryption logic gate G24 is configured to decrypt the first encryption sequence ES1 via the parallel decryption operand and output the restored data packet. The decryption Logic operation module G22 and the data decryption Logic Gate G24 are one or more Logic gates (Logic gates). In principle, the decryption logic G22 AND the data decryption logic G24 must perform inverse logic operations with the parallel-stream encryptor 1442 (e.g. the parallel-stream encryptor 1442 is AND, the parallel-stream decryptor 2442 is NAND)

In one embodiment, referring to fig. 12, the sixty-four bit stream decryptor 2444, the one hundred twenty-eight bit stream decryptor 2446 and the two hundred fifty-six bit stream decryptor 2448 each include a decryption Linear Feedback shift register (Linear Feedback SHIFT REGISTER, LFSR) and one or more decryption Logic gates (Logic Gate), the decryption Linear Feedback shift register has a decryption key, the decryption Linear Feedback shift register logically computes a plurality of decryption bit taps of the decryption key through the decryption Logic Gate to obtain a decryption operand, the decryption operand uses a first bit of the decryption key fed back to the decryption Linear Feedback shift register as an update of the decryption key, the update refers to the first bit of the decryption key input to the decryption operand, the first bit of the decryption key is shifted to a second bit, the second bit of the decryption key is shifted to a third bit, and so on, the last bit of the decryption key is sequentially overwritten by the previous bit, thereby achieving the update of the decryption key. The sixty-four bit stream decryptor 2444 includes a decryption linear feedback shift register 2444L (with sixty-four bit decryption keys d [1] to d [64], d [ n ] being the nth bit of the sixty-four bit decryption key) and a decryption logic gate 2444G, the one hundred twenty-eight bit stream decryptor 2446 includes a decryption linear feedback shift register 2446L (with one hundred twenty-eight bit decryption keys e [1] to e [128], d [ n ] being the nth bit of the one hundred twenty-eight bit decryption key) and a decryption logic gate 2446G, the two hundred fifty-six bit stream decryptor 2448 includes a decryption linear feedback shift register 2448L (with two hundred fifty-six bit decryption keys f [1] to f [256], d [ n ] being the nth bit of the two hundred-fifty-six bit decryption key) and a decryption logic gate 2448G. The decryption linear feedback shift register 2444L performs logical operation on a plurality of decryption bits of the sixty-four bit decryption key to obtain a decryption operand D2, performs logical operation on the decryption operand D2 and the second encryption sequence ES2 and the decryption logic gate 2444G to obtain a first encryption sequence ES1, the decryption linear feedback shift register 2446L performs logical operation on a plurality of decryption bits of the one hundred twenty eight bit decryption key to obtain a decryption operand E2, performs logical operation on the decryption operand E2 and the third encryption sequence ES3 and the decryption logic gate 2446G to obtain a second encryption sequence ES2, and the decryption linear feedback shift register 2448L performs logical operation on a plurality of decryption bits of the twenty-five sixteen bit decryption key to obtain a decryption operand F2, and performs logical operation on the decryption operand F2 and the fourth encryption sequence ES4 and the decryption logic gate 2448G to obtain a third encryption sequence ES3.

In one embodiment, the decryption logic gates 2444G, 2446G, 2448G and the logic operation all use Exclusive OR (XOR) as the operation.

In one embodiment, the decryption logic gates 2444G, 2446G, 2448G AND logic operations may be implemented using AND gates, OR gates, other logic gates, OR a combination of logic gates, without limitation in the present application.

In one embodiment, the number of bits of the decrypted bit tap is two.

In one embodiment, the number of decryption bit taps may be an even number.

The above description is directed to a specific embodiment of the hardware architecture of the present application, and the following description is further directed to a working procedure of the present application, please refer to fig. 13, which is a schematic flow chart of the hybrid parallel computing encryption/decryption system of the present application:

Before data transmission, the encryption level setter 142 and the decryption level setter 242 set the same encryption/decryption level according to user setting/automatic configuration (e.g., when the encryption level setter 142 selects the encryption level of the fourth-order encryptor 144 to be third-order, the decryption level setter 242 selects the decryption level of the fourth-order decryptor 244 to be third-order), which is described in the following.

Similarly, the encryption key setter 146 and the decryption key setter 246 will set the same external key encryption/decryption mode and internal key encryption/decryption mode according to user settings/automatic configuration. For example, when encryption key setter 146 selects eight-bit encryption operand generator 14422 in fourth-order encryptor 144 as external encryption key mode, sixteen-bit encryption operand generator 14424 as external encryption key mode, thirty-two-bit encryption operand generator 14426 as internal encryption key mode (two external encryption key modes and one internal encryption key mode are set), decryption key setter 246 selects eight-bit decryption operand generator 24422 in fourth-order decryptor 244 as external decryption key mode, sixteen-bit decryption operand generator 24424 as external decryption key mode, thirty-two-bit decryption operand generator 24426 as internal decryption key mode (two external decryption key modes and one internal decryption key mode are set).

The encryption operand generator may be various permutations of external encryption key mode and internal encryption key mode, the decryption operand generator may be various permutations of external decryption key mode and internal decryption key mode of collocation encryption operand generator, specifically, any one or more of the encryption operand generators may be set to external encryption key mode or internal encryption key mode according to the permutation composition, any one or more of the decryption operand generators may be set to external decryption key mode or internal decryption key mode according to collocation of encryption operand generator, the various permutations and variations are not limited by the present application (for example, setting one external decryption key mode and two internal decryption key modes when setting one external encryption key mode and two internal decryption key modes, setting three external decryption key modes when setting three external decryption key modes, and setting three internal decryption key modes when setting three internal encryption key modes).

First, in the transmitting device 10, the data packet is output from the data generating module 12 to the data encrypting module 14 (step S201).

The data packet is received by the fourth-order encryptor 144 of the data encryption module 14 and encrypted according to the encryption levels set by the encryption level setter 142 and the encryption key setter 146 and the external encryption key mode or the internal encryption key mode (step S202).

The encrypted data packet is output from the fourth-order encryptor 144 to the receiving device 20 (step S203).

The encrypted sequence is decrypted by the fourth-order decryptor 244 in the data decryption module 24 according to the decryption packets and the external decryption key pattern or the internal decryption key pattern set by the decryption level setter 242 and the decryption key setter 246 (step S204).

The decrypted encryption sequence is outputted from the fourth-order decryptor 244 to the data target module 22 for storage (step S205).

In the following, an embodiment is specifically described in which the fourth-order encryptor 144 includes a parallel stream encryptor 1442, a sixty-four bit stream encryptor 1444, a one hundred twenty-eight bit stream encryptor 1446 and a two hundred fifty-six bit stream encryptor 1448 sequentially connected, wherein the parallel stream encryptor 1442 includes an eight-bit encryption operand generator 14422, a sixteen-bit encryption operand generator 14424, a thirty-two bit encryption operand generator 14426, an external encryption key input 1442O, an internal encryption key storage 1442I and an encryption logic operator G1, the fourth-order decryptor 244 includes a parallel stream decryptor 2442, a sixty-four bit stream decryptor 2444, a one hundred twenty-eight bit stream decryptor 2446 and a two hundred fifty-five sixteen bit stream decryptor 2448 sequentially connected, and the parallel stream decryptor 2442 includes an eight-bit decryption operand generator 24422, a sixteen-bit decryption operand generator 24424, a thirty-two-bit decryption operand generator 24426, an external decryption key input 2442O, an internal decryption key storage 42I and a decryption logic operator G2, and the fourth-order decryptor 244 are shown in fig. 14, fig. 15, a fourth-order decryptor and a fourth-order decryptor 144 of the present application.

The step S202 may be replaced by one or more steps of steps S2021-S2024 according to the encryption level, and the steps must be sequentially present (e.g. in the case of the third-level encryption level, step S202 must be replaced by the corresponding step S2023, and steps S2021 and S2022 must be incorporated together, so that step S202 may be replaced by steps S2021-S2023 in the case of the third-level encryption level), step S204 may be replaced by one or more steps of steps S2041-S2044 according to the decryption level, and the steps must be reversely sequentially present (e.g. in the case of the third-level decryption level, step S204 must be replaced by the corresponding step S2042, and steps S2043 and S2044 must be incorporated together, so that step S204 can be replaced by steps S2042-S2044), which will not be repeated.

In this embodiment, the logical operations of the fourth-order encryptor 144 are all XOR (exclusive or gate), and the logical operations of the fourth-order decryptor 244 are all XOR.

In one embodiment, the above-mentioned logical operations may be other logical operations such as AND, NAND, etc., AND in this embodiment, the number of the decryption tap bits selected by the decryption linear feedback shift register AND the number of the decryption tap bits selected by the decryption feedback shift register are just one embodiment, AND the decryption/decryption tap bits may be selected differently AND in number according to the actual requirement (for example, the first bit AND the seventh bit are selected as the decryption/decryption tap bits, the fourth bit, the fifth bit, the sixth bit AND the eighth bit are selected as the decryption/decryption tap bits, AND the second bit AND the thirty-seventh bit may be selected in case of more bits), where the number of bits is not within the scope of the present application. The decryption tap bits are selected to match the encryption tap bits. In this embodiment, the number of the encryption bit taps of the eight-bit encryption operand generator 14422, the sixteen-bit encryption operand generator 14424, the thirty-two bit encryption operand generator 14426, the sixty-four bit stream encryptor 1444, the one hundred twenty-eight bit stream encryptor 1446, and the two hundred fifty-six bit stream encryptor 1448 is two, and the number of the decryption bit taps of the eight-bit decryption operand generator 24422, the sixteen-bit decryption operand generator 24424, the thirty-two bit decryption operand generator 24426, the sixty-four bit stream decryptor 2444, the one hundred twenty-eight bit stream decryptor 2446, and the two hundred-fifty-six bit stream decryptor 2448 is two. In one embodiment, the number of bits of the decryption bit tap and the decryption bit tap is an even number.

Steps S2021 to S2024 are described below, please refer to fig. 4, fig. 7, and fig. 14.

The data packet is received by the parallel-stream encryptor 1442, and the data packet is encrypted and output by the parallel-stream encryptor 1442 (step S2021).

In one embodiment, the eight-bit encryption operand generator 14422 in the parallel stream encryptor 1442 extracts the second bit a [2] and the fifteenth bit a [7] to obtain the encryption operand A1, the sixteen-bit encryption operand generator 14424 extracts the second bit B [2] and the fifteenth bit B [15] to obtain the encryption operand B1, the thirty-two-bit encryption operand generator 14426 extracts the first bit C [1] and the thirty-two bit B [32] to obtain the encryption operand C1, the encryption operand A1, the encryption operand B1 and the encryption operand C1 are operated by the encryption logic operation module G12 to obtain the parallel encryption operand, and the data packet and the parallel encryption operand are encrypted and outputted by the data encryption logic gate G14. When the encryption level setting unit 142 sets the encryption of two or more levels, the first encryption sequence ES1 output from the parallel stream encryptor 1442 is output to the sixty-four bit stream encryptor 1444, and when the encryption level setting unit 142 sets the encryption of one level, the first encryption sequence ES1 output from the parallel stream encryptor 1442 is output to the receiving device 20.

The first encryption sequence ES1 is received by the sixty-four bit stream encryptor 1444, and the first encryption sequence ES1 is encrypted and output via the sixty-four bit stream encryptor 1444 (step S2022).

In one embodiment, the encryption linear feedback shift register 1444L of the sixty-four bit stream encryptor 1444 extracts the second bit D [2] and sixty-four bit D [64] for performing logic operation to obtain the encrypted operand D1, and the encrypted operand D1 and the first encrypted sequence ES1 are encrypted and output via the encryption logic gate 1444G. The second encryption sequence ES2 output from the sixty-four bit stream encryptor 1444 is output to the one hundred twenty eight bit stream encryptor 1446 when the encryption level setting unit 142 is set to encryption with three or more levels, and the second encryption sequence ES2 output from the sixty-four bit stream encryptor 1444 is output to the receiving device 20 when the encryption level setting unit 142 is set to encryption with two levels.

The second encryption sequence ES2 is received by the one hundred twenty eight bit stream encryptor 1446, and the second encryption sequence ES2 is encrypted and output via the one hundred twenty eight bit stream encryptor 1446 (step S2023).

In one embodiment, the encryption linear feedback shift register 1446L of the one hundred twenty eight bit stream encryptor 1446 extracts the first bit E [1] and the one hundred twenty eight bit d [128] for performing logic operation to obtain the encrypted operand E1, and the encrypted operand E1 and the second encrypted sequence ES2 are encrypted and output via the encryption logic gate 1446G. The third encryption sequence ES3 output from the one hundred twenty eight bit stream encryptor 1446 is output to the two hundred fifty six bit stream encryptor 1448 when the encryption level setting unit 142 is set to encryption with four or more levels, and the third encryption sequence ES3 output from the one hundred twenty eight bit stream encryptor 1446 is output to the receiving device 20 when the encryption level setting unit 142 is set to encryption with three levels.

The third encryption sequence ES3 is received by the two hundred fifty-six bit stream encryptor 1448, and the third encryption sequence ES3 is encrypted and output via the two hundred fifty-six bit stream encryptor 1448 (step S2024).

In one embodiment, the encryption linear feedback shift register 1448L of the two hundred fifty-six bit stream encryptor 1448 extracts the first bit F [1] and the two fifty-four bit F [254] for performing logic operation to obtain the encrypted operand F1, and the encrypted operand F1 and the third encrypted sequence ES3 are encrypted and outputted via the encryption logic gate 1448G. When the encryption level setting unit 142 sets the encryption level to the fourth level, the fourth encryption sequence ES4 outputted from the two hundred fifty-six bit stream encryptor 1448 is outputted from the receiving device 20.

Steps S2041-S2044 are described below, referring to fig. 9, 12 and 15.

The fourth encryption sequence ES4 is received by the two hundred fifty-six bit stream decryptor 2448, and the fourth encryption sequence ES43 is decrypted by the two hundred fifty-six bit stream decryptor 2448 and outputted (step S2041).

In one embodiment, the encryption linear feedback shift register 2448L of the two hundred fifty-six bit stream decryptor 2448 extracts the first bit F [1] and the two fifty-four bit F [254] to obtain the encrypted operand F2, and the encrypted operand F2 and the fourth encrypted sequence ES4 are decrypted by the decryption logic gate 2448G and output the third encrypted sequence ES3 to the one hundred twenty-eight bit stream decryptor 2446.

The third encryption sequence ES3 is received by the one hundred twenty eight bit stream decryptor 2446, and the third encryption sequence ES3 is decrypted by the one hundred twenty eight bit stream decryptor 2446 and output (step S2042).

In one embodiment, the encryption linear feedback shift register 2446L of the one hundred twenty eight bit stream decryptor 2446 extracts the first bit E [1] and one hundred twenty eight bits d [128] for performing a logical operation to obtain the encrypted operand E2, and the encrypted operand E2 and the third encrypted sequence ES3 are decrypted by the decryption logic gate 2446G and output the second encrypted sequence ES2 through the sixty four bit stream decryptor 2444.

The second encryption sequence ES1 is received by the sixty-four bit stream decryptor 2444, and the second encryption sequence ES2 is decrypted and output via the sixty-four bit stream decryptor 2444 (step S2043).

In one embodiment, the encryption linear feedback shift register 2444L of the sixty-four bit stream decryptor 2444 extracts the second bit D [2] and the sixty-four bit D [64] for performing a logic operation to obtain the decryption operand D2, and the decryption operand D2 and the second encryption sequence ES1 are decrypted by the decryption logic gate 2444G and output the first encryption sequence ES1 to the parallel stream decryptor 2442.

The first encryption sequence ES1 is received by the parallel stream decryptor 2442, and the first encryption sequence ES1 is decrypted by the parallel stream decryptor 2442 and outputted (step S2044).

In one embodiment, the eight-bit decryption operand generator 24422 in the parallel stream decryptor 2442 extracts the second bit a [2] and the fifteenth bit a [7] to obtain the decryption operand A2, the sixteen-bit decryption operand generator 24424 extracts the second bit B [2] and the fifteenth bit B [15] to obtain the decryption operand B2, the thirty-two-bit decryption operand generator 24426 extracts the first bit C [1] and the thirty-two bit B [32] to obtain the decryption operand C2, and the decryption operand A2, the decryption operand B2 and the decryption operand C2 are operated by the decryption logic operation module G22 to obtain the parallel decryption operand, and the parallel decryption operand and the first encryption sequence ES1 are operated by the data decryption logic gate G24 to decrypt and output the restored data packet.

Compared with the prior art, the application can adjust the secret key to be an internal secret key or an external secret key according to the required decryption mode and adjust the decryption level according to the requirement, and can realize different decryption modes through one set of hardware.

While the application has been described in detail in connection with the present application, the foregoing description is a preferred embodiment of the application, and is not intended to limit the scope of the application, i.e., it is intended to cover modifications and variations of the application as fall within the scope of the application.

Claims

1. A hybrid parallel computing encryption and decryption system, comprising:

the transmitting end device comprises a data generation module and a data encryption module, wherein the data encryption module comprises an encryption level setter and a fourth-order encryptor, the fourth-order encryptor comprises a parallel stream encryptor, a sixty-four bit stream encryptor, a hundred twenty-eight bit stream encryptor and a two hundred fifty-six bit stream encryptor which are sequentially connected, the encryption level setter is used for selecting an encryption level, the data encryption module obtains at least one data packet from the data generation module, the fourth-order encryptor encrypts the data packet according to the encryption level and then outputs an encryption sequence, and

The receiving end device comprises a data target module and a data decryption module, wherein the data decryption module comprises a decryption level setter and a fourth-order decryptor, the fourth-order decryptor comprises a parallel stream decryptor, a sixty-four bit stream decryptor, a hundred twenty-eight bit stream decryptor and a twenty-fifty-six bit stream decryptor which are sequentially connected, the decryption level corresponds to the encryption level, the decryption level is selected, the data decryption module obtains the encryption sequence from the transmitting end device, and the fourth-order decryptor decrypts the encryption sequence according to the decryption level and outputs the restored data packet;

The data packet is received by the parallel-stream encryptor, encrypted by the parallel-stream encryptor and output, when the encryption level setting device sets the encryption of more than two orders, the first encryption sequence output by the parallel-stream encryptor is output to the sixty-four bit-stream encryptor, when the encryption level setting device sets the encryption of one order, the first encryption sequence output by the parallel-stream encryptor is output to the receiving end device;

The first encryption sequence is received by the sixty-four bit stream encryptor, the first encryption sequence is encrypted by the sixty-four bit stream encryptor and output, when the encryption level setting device sets the encryption of more than three orders, the second encryption sequence output by the sixty-four bit stream encryptor is output to the one hundred twenty-eight bit stream encryptor, when the encryption level setting device sets the encryption of more than two orders, the second encryption sequence output by the sixty-four bit stream encryptor is output to the receiving end device;

The second encryption sequence is received by a hundred twenty-eight bit stream encryptor, the second encryption sequence is encrypted by the hundred twenty-eight bit stream encryptor and output, when the encryption level setting device sets the encryption of more than four orders, the third encryption sequence output by the hundred twenty-eight bit stream encryptor is output to the two hundred fifty-six bit stream encryptor, when the encryption level setting device sets the encryption of three orders, the third encryption sequence output by the hundred twenty-eight bit stream encryptor is output to the receiving end device;

a third encryption sequence is received by a two hundred fifty-six bit stream encryptor, the third encryption sequence being encrypted and output via the two hundred fifty-six bit stream encryptor;

when the encryption level setting unit sets the encryption of the fourth order, the fourth encryption sequence outputted from the two hundred fifty-six bit stream encryptor is outputted from the receiving device.

2. The hybrid parallel operation encryption and decryption system of claim 1, wherein the sixty-four bit stream encryptor, the one hundred twenty-eight bit stream encryptor and the twenty-fifty-six bit stream encryptor each include an encryption linear feedback shift register and one or more encryption logic gates, the encryption linear feedback shift register having an encryption key, the encryption linear feedback shift register logically operating on a plurality of encryption bit taps of the encryption key via the encryption logic gates to obtain an encryption operand, the encryption operand and the data packet being encrypted via the encryption logic gates to obtain the encryption sequence, the sixty-four bit stream decryptor, the one hundred twenty-eight bit stream decryptor and the twenty-fifty-six bit stream decryptor each include a decryption linear feedback shift register having a decryption key, the decryption linear feedback shift register logically operating on a plurality of decryption bit taps of the decryption key via the decryption logic gates to obtain the decryption operand and the decryption operand being decrypted via the decryption logic gates to obtain the decryption sequence.

3. The hybrid parallel operation encryption and decryption system according to claim 1, wherein the data encryption module further comprises an encryption key setter, the parallel stream encryptor comprises an eight-bit encryption operand generator, a sixteen-bit encryption operand generator, a thirty-two-bit encryption operand generator, an external encryption key input, an internal encryption key storage and an encryption logic operator, the encryption key setter selects an external encryption key mode or an internal encryption key mode, the eight-bit encryption operand generator, the sixteen-bit encryption operand generator and the thirty-two-bit encryption operand generator respectively generate encryption operands according to an external encryption key generated by the external encryption key input or an internal encryption key stored by the internal encryption key storage, and the encryption operands and the data packet are operated by the encryption logic operator to obtain a first encryption sequence; the data decryption module further comprises a decryption key setter, the parallel stream decryptor comprises an eight-bit decryption operand generator, a sixteen-bit decryption operand generator, a thirty-two-bit decryption operand generator, an external decryption key input, an internal decryption key storage and a decryption logic arithmetic unit, the decryption key setter selects an external decryption key mode or an internal decryption key mode corresponding to the encryption key setter, the eight-bit decryption operand generator, the sixteen-bit decryption operand generator and the thirty-two-bit decryption operand generator respectively generate decryption operands according to an external decryption key generated by the external decryption key input or an internal decryption key stored by the internal decryption key storage, and the decryption operand and the first encryption sequence are operated by the decryption logic operator to obtain the restored data packet.

4. The hybrid parallel computing encryption and decryption system of claim 3, wherein the external encryption key input unit includes an encryption key generator and an encryption controller, the encryption key generator generates the external encryption key according to the external encryption key pattern, the encryption controller outputs the external encryption key according to the external encryption key pattern, the decryption key input unit includes a decryption key generator and a decryption controller, the decryption key generator generates the external decryption key according to the external decryption key pattern, and the decryption controller outputs the external decryption key according to the external decryption key pattern.

5. The hybrid parallel computing encryption and decryption system of claim 3, wherein the external encryption key inputter is an encryption input controller, the encryption input controller includes an encryption inputter for inputting the external encryption key and an encryption controller for outputting the external encryption key according to the external encryption key pattern, the decryption key inputter is a decryption input controller, the decryption input controller includes a decryption inputter for inputting the external decryption key and a decryption controller for outputting the external decryption key according to the external decryption key pattern.

6. The system of claim 4 or claim 5, wherein the eight-bit encryption operand generator, the sixteen-bit encryption operand generator, and the thirty-two-bit encryption operand generator each include an encryption linear feedback shift register having the internal encryption key or the external encryption key and one or more generation encryption logic gates, the encryption linear feedback shift register performing a logical operation on the internal encryption key or the plurality of encryption bit taps of the external encryption key via the generation encryption logic gates to obtain the encryption operand, and the eight-bit decryption operand generator, the sixteen-bit decryption operand generator, and the thirty-two-bit decryption operand generator each include a decryption linear feedback shift register having the internal decryption key or the external decryption key and one or more generation decryption logic gates, the decryption linear feedback shift register performing a logical operation on the internal decryption key or the plurality of decryption bit taps of the external decryption key via the generation decryption logic gates to obtain the decryption operand.

7. Transmitting terminal device, its characterized in that includes:

data generating module, and

The data encryption module comprises an encryption level setting device and a fourth-order encryptor, wherein the fourth-order encryptor comprises a parallel stream encryptor, a sixty-four bit stream encryptor, a hundred twenty-eight bit stream encryptor and a twenty-fifty-six bit stream encryptor which are sequentially connected, the encryption level setting device is used for selecting an encryption level, the data encryption module obtains at least one data packet from the data generation module, and the fourth-order encryptor encrypts the data packet according to the encryption level and then outputs an encryption sequence;

8. The transmitting device of claim 7, wherein the sixty-four bit stream encryptor, the one hundred twenty-eight bit stream encryptor and the two hundred fifty-six bit stream encryptor each comprise an encryption linear feedback shift register and one or more encryption logic gates, the encryption linear feedback shift register having an encryption key, the encryption linear feedback shift register logically operating on a plurality of encryption bit taps of the encryption key through the encryption logic gates to obtain an encryption operand, the encryption operand and the data packet being encrypted through the encryption logic gates to obtain the encryption sequence.

9. The transmitting device of claim 7, wherein the data encryption module further comprises an encryption key setter, the parallel stream encryptor comprises an eight-bit encryption operand generator, a sixteen-bit encryption operand generator, a thirty-two-bit encryption operand generator, an external encryption key input, an internal encryption key storage, and an encryption logic operator, the encryption key setter selects an external encryption key mode or an internal encryption key mode, the eight-bit encryption operand generator, the sixteen-bit encryption operand generator, and the thirty-two-bit encryption operand generator respectively generate encryption operands according to an external encryption key generated by the external encryption key input or an internal encryption key stored by the internal encryption key storage, and the encryption operands and the data packet are operated by the encryption logic operator to obtain a first encryption sequence.

10. The transmitting-end apparatus of claim 9, wherein the external encryption key inputter includes an encryption key generator that generates the external encryption key according to the external encryption key pattern, and an encryption controller that outputs the external encryption key according to the external encryption key pattern.

11. The transmitting-end apparatus according to claim 9, wherein the external encryption key inputter is an encryption input controller including an encryption inputter for inputting the external encryption key and an encryption controller outputting the external encryption key in accordance with the external encryption key pattern.

12. The transmitting-side apparatus of claim 10 or claim 11, wherein the eight-bit encryption operand generator, the sixteen-bit encryption operand generator, and the thirty-two-bit encryption operand generator each include an encryption linear feedback shift register having the internal encryption key or the external encryption key and one or more generation encryption logic gates, the encryption linear feedback shift register logically operating on a plurality of encryption bit taps of the internal encryption key or the external encryption key via the generation encryption logic gates to obtain the encryption operand.

13. A receiving-end apparatus, comprising:

data object module, and

The data decryption module comprises a decryption level setter and a fourth-order decryptor, wherein the fourth-order decryptor comprises a parallel stream decryptor, a sixty-four bit stream decryptor, a hundred twenty-eight bit stream decryptor and a twenty-fifty-six bit stream decryptor which are sequentially connected, the decryption level corresponds to an encryption level, the decryption level is selected, the data decryption module obtains an encryption sequence from a transmitting end device, and the fourth-order decryptor decrypts the encryption sequence according to the decryption level and then outputs a restored data packet;

A fourth encryption sequence received by a two hundred fifty-six bit stream decryptor, the fourth encryption sequence decrypted and output by the two hundred fifty-six bit stream decryptor;

A third encryption sequence is received by a one hundred twenty eight bit stream decryptor, the third encryption sequence being decrypted and output by the one hundred twenty eight bit stream decryptor;

A second encrypted sequence is received by the sixty-four bit stream decryptor, the second encrypted sequence being decrypted and output via the sixty-four bit stream decryptor;

The first encrypted sequence is received by the parallel stream decryptor, decrypted by the parallel stream decryptor and output.

14. The sink device of claim 13, wherein the sixty-four bit stream decryptor, the one hundred twenty-eight bit stream decryptor and the two hundred fifty-six bit stream decryptor each comprise a decryption linear feedback shift register and one or more decryption logic gates, the decryption linear feedback shift register having a decryption key, the decryption linear feedback shift register logically operating on a plurality of decryption bit taps of the decryption key via the decryption logic gates to obtain decryption operands, the decryption operands and the encryption sequence being decrypted via the decryption logic gates to obtain the restored data packets.

15. The sink device of claim 13, wherein the data decryption module further comprises a decryption key setter, the parallel stream decryptor comprises an eight-bit decryption operand generator, a sixteen-bit decryption operand generator, a thirty-two-bit decryption operand generator, an external decryption key input, an internal decryption key store, and a decryption logic operator, the decryption key setter selects an external decryption key mode or an internal decryption key mode corresponding to the encryption key setter, the eight-bit decryption operand generator, the sixteen-bit decryption operand generator, and the thirty-two-bit decryption operand generator respectively generate decryption operands according to an external decryption key generated by the external decryption key input or an internal decryption key stored by the internal decryption key store, and the decryption operands and the first encryption sequence are operated by the decryption logic operator to obtain the restored data packet.

16. The receiver-side apparatus according to claim 15, wherein the decryption key inputter includes a decryption key generator that generates the external decryption key in accordance with the external decryption key pattern, and a decryption controller that outputs the external decryption key in accordance with the external decryption key pattern.

17. The receiver device of claim 15, wherein the decryption key inputter is a decryption input controller, the decryption input controller including a decryption inputter for inputting the external decryption key and a decryption controller outputting the external decryption key according to the external decryption key pattern.

18. The receiver apparatus of claim 16 or claim 17, wherein the eight-bit decryption operand generator, the sixteen-bit decryption operand generator, and the thirty-two-bit decryption operand generator each comprise one or more generate decryption logic gates, the decrypt linear feedback shift register having the internal decryption key or the external decryption key, the decrypt linear feedback shift register logically operating on a plurality of decryption bit taps of the internal decryption key or the external decryption key via the generate decryption logic gates to obtain the decryption operand.