CN114446943B - Semiconductor packaging structure and method for preparing semiconductor packaging structure - Google Patents
Semiconductor packaging structure and method for preparing semiconductor packaging structure Download PDFInfo
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- CN114446943B CN114446943B CN202210117449.0A CN202210117449A CN114446943B CN 114446943 B CN114446943 B CN 114446943B CN 202210117449 A CN202210117449 A CN 202210117449A CN 114446943 B CN114446943 B CN 114446943B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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Abstract
The embodiment of the invention provides a semiconductor packaging structure and a preparation method thereof, relating to the technical field of semiconductor packaging, wherein the semiconductor packaging structure comprises a substrate, a first chip, a second chip, a heat dissipation column, a first plastic package body and solder balls, the heat dissipation post is arranged on one side surface of the substrate and is positioned between the first chip and the second chip, a metal layer is arranged on one side surface of the substrate, and the bottom of the heat dissipation post is connected with the metal layer and used for dissipating heat of the substrate. Through being provided with the heat dissipation post between first chip and second chip, the heat dissipation post sets up on the metal level of base plate, can play good radiating effect. Compared with the prior art, the semiconductor packaging structure provided by the invention can realize good heat dissipation effect on the substrate, further improve the heat dissipation capacity of the whole device and ensure the performance of the device.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a preparation method of the semiconductor packaging structure.
Background
With the rapid development of the semiconductor industry, a double-sided packaging product structure or a multi-chip packaging product structure mainly forms a packaging structure on the front side and the back side of a substrate, and as a plurality of packaging materials exist in the semiconductor packaging structure formed on the substrate, a plurality of chips are required to be packaged, so that the heat dissipation capacity of the substrate and the chips is poor, and the performance of a device is affected.
Disclosure of Invention
The invention aims at providing a semiconductor packaging structure and a preparation method of the semiconductor packaging structure, which can improve the heat dissipation capacity of a device.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a semiconductor package structure, comprising:
A substrate;
A first chip and a second chip which are attached to one side surface of the substrate at intervals;
the heat dissipation column is arranged on one side surface of the substrate and positioned between the first chip and the second chip;
the first plastic package body is arranged on one side surface of the substrate and at least coated outside the first chip and the second chip;
And a solder ball disposed on the other surface of the substrate;
The first chip, the second chip and the third chip are all electrically connected with the substrate, a metal layer is arranged on one side surface of the substrate, the bottom of the heat dissipation column is connected with the metal layer and used for dissipating heat of the substrate, and the solder balls are located on at least two sides of the second plastic package body and are electrically connected with the substrate.
In an alternative embodiment, the semiconductor package structure further includes a third chip attached to the other side surface of the substrate, and a second plastic package body disposed on the other side surface of the substrate and coated outside the third chip.
In an alternative embodiment, the first plastic package body is further coated outside the heat dissipation post.
In an alternative embodiment, a plurality of heat dissipation grooves are formed on the heat dissipation columns, and each heat dissipation groove penetrates from the surface of the heat dissipation column to the surface of the metal layer.
In an alternative embodiment, the surface of the metal layer is further provided with a plurality of first grooves, and the first grooves are located at the bottoms of the heat dissipation columns and correspondingly communicated with the heat dissipation grooves.
In an alternative embodiment, the thickness of the first chip is the same as that of the second chip, and the distance H1 between the side surface of the first plastic package body, which is far away from the substrate, and the first chip is greater than the distance H2 between the side surface of the first plastic package body, which is far away from the substrate, and the heat dissipation post.
In an alternative embodiment, a distance H1 between a side surface of the first plastic package body away from the substrate and the first chip is twice a distance H2 between a side surface of the first plastic package body away from the substrate and the heat dissipation post.
In an alternative embodiment, a wiring layer is arranged in the substrate, a metal pad electrically connected with the wiring layer is arranged on the other side surface of the substrate, and the solder ball is arranged on the metal pad.
In an alternative embodiment, the surface of the metal pad is further provided with a second groove, and the solder ball covers the second groove.
In an optional embodiment, the first plastic package body is formed with a relief opening slot penetrating through the substrate, and the relief opening slot corresponds to the heat dissipation post, so that the heat dissipation post is exposed outside the first plastic package body.
In an optional embodiment, the first plastic package body is partially coated outside the heat dissipation column, and one end part of the heat dissipation column, which is far away from the substrate, extends out of the first plastic package body.
In an optional embodiment, an extended heat dissipation plate is arranged at the edge of the heat dissipation column, and the extended heat dissipation plate is attached to the surface of one side, far away from the substrate, of the first plastic package body.
In an optional embodiment, the extended heat dissipation plate covers a surface of the first plastic package body far away from the substrate, and extends to an edge of the first plastic package body.
In an optional embodiment, a fourth chip is further disposed on a side, far away from the substrate, of the first plastic package body, and the fourth chip is attached to the heat dissipation post and is electrically connected with the substrate.
In an optional embodiment, the fourth chip is a front-mounted chip, a conductive wire arc is arranged on one side, far away from the substrate, of the fourth chip, the conductive wire arc is connected with the substrate, and a filling adhesive layer is further arranged on the substrate, and the filling adhesive layer is coated on the conductive wire arc and the outside of the fourth chip.
In an optional embodiment, the fourth chip is a flip chip, the heat dissipation post has conductivity, the fourth chip is electrically connected with the substrate through the heat dissipation post, and a third plastic package body or a filling glue layer coated outside the fourth chip is further disposed on the substrate.
In an alternative embodiment, a plurality of third grooves are formed in a portion of the heat dissipation post extending out of the first plastic package body.
In a second aspect, the present invention provides a method for manufacturing a semiconductor package structure, including:
forming a heat dissipation column on a substrate;
A first chip and a second chip are attached to the base plates at intervals on two sides of the heat dissipation column;
Forming a first plastic package body which is at least coated outside the first chip and the second chip on the substrate in a plastic package mode;
Turning over the substrate, and attaching a third chip on the substrate;
Forming a second plastic package body coated outside the third chip on the substrate in a plastic package mode;
Forming solder balls on the substrate;
The first chip, the second chip and the third chip are all electrically connected with the substrate, a metal layer is arranged on one side surface of the substrate, the bottom of the heat dissipation column is connected with the metal layer and used for dissipating heat of the substrate, and the solder balls are located on at least two sides of the second plastic package body and are electrically connected with the substrate.
In an alternative embodiment, the step of forming the heat dissipation pillars on the substrate includes:
forming a dry film layer on a substrate;
Etching the dry film layer to form an etched opening;
Forming a heat-dissipating stud within the etched opening;
removing the dry film layer;
and micro etching is performed on the bottom of the heat dissipation column to form a first groove.
The beneficial effects of the embodiment of the invention include, for example:
According to the semiconductor packaging structure and the preparation method of the semiconductor packaging structure, the first chip and the second chip are attached to the substrate, so that multi-chip packaging is achieved, meanwhile, the heat dissipation column is arranged between the first chip and the second chip and is arranged on the metal layer of the substrate, and good heat dissipation effect can be achieved. Compared with the prior art, the semiconductor packaging structure provided by the invention can realize good heat dissipation effect on the substrate, further improve the heat dissipation capacity of the whole device and ensure the performance of the device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic view of a semiconductor package structure according to a first embodiment of the present invention;
FIG. 2 is an enlarged partial schematic view of II in FIG. 1;
Fig. 3 to 11 are process flow diagrams of a method for manufacturing a semiconductor package according to a first embodiment of the present invention;
fig. 12 is a schematic view of a semiconductor package structure according to a second embodiment of the present invention;
fig. 13 is a schematic view of a semiconductor package structure according to a third embodiment of the present invention;
fig. 14 is a schematic view of a semiconductor package structure according to a fourth embodiment of the present invention;
Fig. 15 is a schematic view of a semiconductor package structure according to a fifth embodiment of the present invention;
Fig. 16 is a schematic view of a semiconductor package structure according to a sixth embodiment of the present invention;
Fig. 17 is a schematic view of a semiconductor package structure according to a seventh embodiment of the present invention.
The icons are 100-semiconductor packaging structure, 110-substrate, 111-solder ball, 113-metal layer, 115-wiring layer, 117-metal pad, 119-second groove, 120-first chip, 130-second chip, 140-heat-dissipating column, 141-heat-dissipating groove, 143-first groove, 145-expanded heat-dissipating plate, 150-first plastic package, 151-abdication opening groove, 160-third chip, 170-second plastic package, 180-fourth chip, 181-conductive wire arc, 183-filled adhesive layer, 190-third plastic package, 191-third groove, 200-dry film layer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
As disclosed in the background art, the existing semiconductor packaging structure adopts a plurality of chips, so that the heating value is large, and the plastic packaging body needs to cover the plurality of chips, so that the overall heat dissipation capacity of the device is poor, and the performance of the device can be influenced. In addition, since a plurality of packaging materials exist in the semiconductor packaging structure formed on the substrate, materials of different packaging bodies are different in use, CTE coefficients among the materials are different, and in the reliability test process of the product, the delamination problem of the plastic packaging body and the chip surface and the delamination problem of the plastic packaging body and the substrate are easy to exist. Moreover, the existing semiconductor packaging structure can only realize double-sided packaging, so that the integration level is difficult to improve, and stacking cannot be realized.
In order to solve the above-mentioned problems, the present invention provides the following novel semiconductor package structure and a method for manufacturing the semiconductor package structure, and it should be noted that the features in the embodiments of the present invention may be combined with each other without collision.
First embodiment
Referring to fig. 1 and 2, the present embodiment provides a semiconductor package structure 100, which can achieve a good heat dissipation effect on a substrate 110, thereby improving the heat dissipation capability of the whole device and ensuring the performance of the device. Meanwhile, the layering problem of the plastic package body can be avoided, and the stability of the structure is ensured.
The semiconductor package structure 100 provided in this embodiment includes a substrate 110, a first chip 120, a second chip 130, a heat dissipation post 140, a first plastic package body 150, a third chip 160, a second plastic package body 170 and solder balls 111, where the first chip 120 and the second chip 130 are mounted on one side surface of the substrate 110 at intervals, the heat dissipation post 140 is also disposed on one side surface of the substrate 110 and between the first chip 120 and the second chip 130, the first plastic package body 150 is disposed on one side surface of the substrate 110 and at least covers the first chip 120 and the second chip 130, the third chip 160 is mounted on the other side surface of the substrate 110, the second plastic package body 170 is disposed on the other side surface of the substrate 110 and covers the third chip 160, the solder balls 111 are disposed on the other side surface of the substrate 110, the first chip 120, the second chip 130 and the third chip 160 are all electrically connected with the substrate 110, the bottom of the heat dissipation post 140 is connected with the metal layer 113 and is used for dissipating heat from the substrate 110, the solder balls 111 are disposed on at least two sides of the second plastic package body 170 and electrically connected with the substrate 110.
In this embodiment, a surface of one side of the substrate 110 has a mounting area and a heat dissipation area, the mounting area is located at two sides of the heat dissipation area, the metal layer 113 is disposed in the heat dissipation area, the heat dissipation area is located at a center of the substrate 110, and the first chip 120 and the second chip 130 are respectively mounted on the mounting area and electrically connected to the substrate 110. Meanwhile, in the embodiment, the mounting position of the third chip 160 corresponds to the heat dissipation area, so that the solder balls 111 can be distributed around the second plastic package 170, and the second plastic package 170 adopts a selective plastic package process, which only covers the outer edge of the third chip 160, but not the surface of the whole substrate 110, thereby facilitating the arrangement of the solder balls 111.
It should be noted that, in the present embodiment, a double-sided package structure is adopted, and in other preferred embodiments of the present invention, the other side surface of the substrate 110 may not be provided with the third chip 160 and the second plastic package 170, so as to form a single-sided package structure.
In this embodiment, the first plastic package 150 is further wrapped around the heat dissipation post 140. Specifically, the first plastic package body 150 is integrally molded outside the first chip 120, the second chip 130 and the heat dissipation post 140, so as to cover the surface of the entire substrate 110, and cover the first chip 120, the second chip 130 and the heat dissipation post 140 inside, thereby playing a good role in protection.
In the present embodiment, a plurality of heat dissipation grooves 141 are disposed on the heat dissipation post 140, and each heat dissipation groove 141 penetrates from the surface of the heat dissipation post 140 to the surface of the metal layer 113. Specifically, by providing the heat dissipation groove 141, the heat dissipation column 140 can be separated into a plurality of column structures, so that the molding compound can be filled in the heat dissipation groove 141 during the molding, thereby improving the bonding force between the first molding body 150 and the heat dissipation column 140 and the substrate 110.
In this embodiment, the heat dissipation post 140 is a copper post and is formed on the metal layer 113 by electroplating, so that the heat dissipation post 140 has a good heat dissipation effect and is capable of transferring heat to the outside. Of course, in other preferred embodiments, other heat conductive materials, such as silver or aluminum pillars, may be used for the heat dissipation pillars 140, which is not limited herein.
In this embodiment, the surface of the metal layer 113 is further provided with a plurality of first grooves 143, and the plurality of first grooves 143 are located at the bottom of the heat dissipation columns 140 and correspondingly communicate with the plurality of heat dissipation grooves 141. Specifically, after the heat dissipation grooves 141 are in one-to-one correspondence with the plurality of first grooves 143, after the heat dissipation columns 140 are formed, etching can be continued on the metal layer 113 through a micro etching process to form the first grooves 143, and by setting the first grooves 143, the molding compound can be continuously filled downwards, so that the bonding force among the first molding body 150, the heat dissipation columns 140 and the substrate 110 is improved.
It should be noted that, in the present embodiment, the width of the first groove 143 is equivalent to the width of the heat dissipation groove 141, and the heat dissipation post 140 is formed by adopting a metal electroplating process, so that the heat dissipation post 140 and the metal layer 113 can be formed into a whole, further facilitating heat transfer, and meanwhile, the molding compound of the first plastic package body 150 can be continuously filled into the first groove 143, so that the first plastic package body 150 and the metal layer 113 can be embedded into each other, the bonding force between the first plastic package body 150 and the substrate 110 is improved, and further the layering problem between the substrate 110 and the first plastic package body 150 is prevented.
In the present embodiment, the thickness of the first chip 120 and the second chip 130 are the same, and the distance H1 between the side surface of the first plastic package 150 away from the substrate 110 and the first chip 120 is greater than the distance H2 between the side surface of the first plastic package 150 away from the substrate 110 and the heat dissipation post 140. Specifically, the first chip 120 and the second chip 130 are flip chips, and the thicknesses of the first chip 120 and the second chip 130 are the same, so that the heights of the first chip 120 and the second chip 130 are the same, and meanwhile, the first plastic package body 150 is completely coated outside the first chip 120, the second chip 130 and the heat dissipation column 140, so that the thickness of the first plastic package body 150 at the positions of the first chip 120 and the second chip 130 is larger than that at the position of the heat dissipation column 140, and the first plastic package bodies 150 with different thicknesses are formed at the positions of the first chip 120 and the heat dissipation column 140, so that the layering thicknesses of the positions of the first plastic package body 150 are consistent, and the problem of layering of the back surface of the chip and the first plastic package body 150 is prevented. Of course, in other preferred embodiments of the present invention, the first chip 120 and the second chip 130 may be front-mounted chips and electrically connected to the substrate 110 by wire bonding.
It should be noted that, in the present embodiment, the distance H1 between the side surface of the first plastic package body 150 away from the substrate 110 and the first chip 120 refers to the distance between the back surface of the first chip 120 and the surface of the first plastic package body 150, and the distance H2 between the side surface of the first plastic package body 150 away from the substrate 110 and the heat dissipation post 140 refers to the distance between the end of the heat dissipation post 140 away from the substrate 110 and the surface of the first plastic package body 150.
In the present embodiment, the distance H1 between the side surface of the first plastic package 150 away from the substrate 110 and the first chip 120 is twice the distance H2 between the side surface of the first plastic package 150 away from the substrate 110 and the heat dissipation post 140. Specifically, by reasonably setting the proportional relationship between H1 and H2, the delamination phenomenon of the first plastic package 150 can be better prevented.
In the present embodiment, a wiring layer 115 is provided in a substrate 110, a metal pad 117 electrically connected to the wiring layer 115 is provided on the other side surface of the substrate 110, and a solder ball 111 is provided on the metal pad 117. Specifically, the wiring layer 115 adopts a conventional wiring structure, while the metal pads 117 are disposed on at least two sides of the second molding 170, and the solder balls 111 can pass through the copper pillars and the wiring layer 115 Li Lianjie. The solder balls 111 are solder balls, and preferably, the height of the solder balls 111 with respect to the substrate 110 is greater than that of the second molding body 170, so that external soldering can be better achieved.
In this embodiment, the surface of the metal pad 117 is further provided with a second groove 119, and the solder ball 111 covers the second groove 119. Specifically, the second groove 119 may be formed on the metal pad 117 by micro etching, and the second groove 119 is located at the center of the metal pad 117, so that the second groove 119 can play a role in buffering when the solder ball 111 is formed, thereby releasing the internal stress of the solder ball 111, and improving the bonding force of the solder ball 111.
Referring to fig. 3 to 11 in combination, the present embodiment further provides a method for manufacturing the semiconductor package 100, which includes the following steps:
s1, forming a heat dissipation column 140 on the substrate 110.
Referring to fig. 3 to 6 in combination, in particular, a substrate 110 is provided, and heat dissipation pillars 140 are formed on the substrate 110. In performing step S1, a dry film layer 200 may be formed on the substrate 110, then the dry film layer 200 is etched to form an etched opening, then the heat dissipation post 140 is formed in the etched opening, then the dry film layer 200 is removed, and finally the first groove 143 is micro-etched at the bottom of the heat dissipation post 140, thereby completing the process of the heat dissipation post 140. The thickness of the dry film layer 200 may be set according to the height of the heat dissipation pillars 140.
In actual preparation, a substrate 110 may be first taken, a heat dissipation area and a mounting area are defined on the substrate 110, a copper pillar is formed in the heat dissipation area, a layer of dry film is first laid on the substrate 110, then a portion where the copper pillar needs to be formed is etched and removed by etching, copper is electroplated in the opening to form a copper pillar structure, the dry film is removed, and then micro etching is performed at the bottom of the copper pillar to form a first groove 143 structure.
S2, the first chip 120 and the second chip 130 are mounted on the substrate 110 at intervals on two sides of the heat dissipation post 140.
Referring to fig. 7 in combination, specifically, after the heat dissipation posts 140 are formed, the mounting of the first and second chips 120 and 130 is completed using a flip-chip process or a forward mounting process, and the first and second chips 120 and 130 are connected to pads on the surface of the substrate 110, thereby achieving electrical connection between the first and second chips 120 and 130 and the substrate 110.
S3, forming a first plastic package body 150 at least covering the first chip 120 and the second chip 130 by plastic package on the substrate 110.
Referring to fig. 8 in combination, specifically, the first molding compound 120, the mounting area of the second chip 130, and the heat dissipation area are filled with a molding compound by a molding process, and after curing, a first molding body 150 is formed that covers the first chip 120, the second chip 130, and the heat dissipation post 140 at the same time.
S4, the substrate 110 is turned over, and the third chip 160 is attached to the substrate 110.
Referring to fig. 9 in combination, specifically, after the substrate 110 is flipped over, the third chip 160 is mounted again on the back surface of the substrate 110 using a front-loading or flip-chip process.
S5, molding the substrate 110 to form a second molding body 170 wrapping the third chip 160.
Referring to fig. 10 in detail, after the mounting of the third chip 160 is completed, a second plastic package 170 is formed by using a plastic package process, and when the second plastic package 170 is formed, a selective plastic package process may be used, so that the second plastic package 170 covers only the third chip 160, thereby avoiding the metal pads 117 on the substrate 110 for ball mounting.
S6, forming solder balls 111 on the substrate 110.
Referring to fig. 11 in combination, specifically, after the second molding compound 170 is formed, the preparation of the solder balls is completed by a ball-implanting process, and then the product is cut into individual pieces by a cutting process.
In summary, the semiconductor package structure 100 and the method for manufacturing the semiconductor package structure 100 according to the present embodiment achieve double-sided packaging by respectively attaching the first chip 120, the second chip 130 and the third chip 160 on both sides of the substrate 110, and meanwhile, the heat dissipation pillars 140 are disposed between the first chip 120 and the second chip 130, and the heat dissipation pillars 140 are disposed on the metal layer 113 of the substrate 110, so that a good heat dissipation effect can be achieved. In addition, by forming the first groove 143 at the bottom of the heat dissipation post 140, the bonding force between the first plastic package body 150 and the substrate 110 and between the first plastic package body 150 and the heat dissipation post 140 can be further improved, so that the layering phenomenon between the first plastic package body 150 and the substrate 110 is avoided. Meanwhile, the height of the heat dissipation post 140 is different from the heights of the first chip 120 and the second chip 130, so that layering phenomenon between the first plastic package 150 and the back surface of the chip can be avoided. In addition, the second groove 119 is also arranged on the metal pad 117, so that a buffer effect can be achieved when the solder ball 111 is prepared, and therefore the internal stress of the solder ball 111 is released, and the binding force between the solder ball 111 and the metal pad 117 is improved.
Second embodiment
Referring to fig. 12, the present embodiment provides a semiconductor package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the embodiment is not mentioned.
In the present embodiment, the first plastic package 150 is formed with a relief opening groove 151 penetrating through the substrate 110, and the relief opening groove 151 corresponds to the heat dissipation post 140, so that the heat dissipation post 140 is exposed outside the first plastic package 150. Specifically, when forming the first plastic package body 150, a selective plastic package process may be adopted, so that the first plastic package body 150 is two plastic packages arranged at intervals, and is respectively coated outside the first chip 120 and the second chip 130.
In the present embodiment, the relief opening groove 151 corresponds to a heat dissipation area on the substrate 110, so that the heat dissipation post 140 can be directly exposed to the outside, and the heat dissipation capability of the heat dissipation post is further improved. In addition, the heat dissipation pillars 140 are provided with a plurality of heat dissipation grooves 141, so that the heat dissipation area of the heat dissipation pillars 140 can be further increased, and the heat dissipation capacity can be improved.
It should be noted that, in this embodiment, the height of the heat dissipation post 140 may be smaller than that of the first plastic package body 150, and the forming process of the heat dissipation post 140 is the same as that of the first embodiment, and compared with the first embodiment, the manufacturing process is different in that the first plastic package body 150 is manufactured, and the first plastic package body 150 adopts a selective plastic package process, and simultaneously forms two plastic package body structures coated outside the first chip 120 and outside the second chip 130.
Third embodiment
Referring to fig. 13, the present embodiment provides a semiconductor package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the embodiment is not mentioned.
In this embodiment, the first plastic package body 150 is partially wrapped around the heat dissipation post 140, and one end portion of the heat dissipation post 140 away from the substrate 110 extends out of the first plastic package body 150. Specifically, the height of the heat dissipation post 140 is higher than that of the first plastic package body 150, so that the top end of the heat dissipation post 140 can partially extend out of the first plastic package body 150 and be exposed outside, and the heat dissipation capability of the heat dissipation post can be improved.
In this embodiment, an extended heat dissipation plate 145 is disposed at the edge of the heat dissipation post 140, and the extended heat dissipation plate 145 is attached to a surface of the first plastic package body 150, which is far away from the substrate 110. The extended heat dissipation plate 145 is horizontally attached to the surface of the first plastic package body 150, and the extended heat dissipation plate 145 and the heat dissipation column 140 form an L-shaped structure, on one hand, by arranging the extended heat dissipation plate 145, the contact area between the extended heat dissipation plate 145 and the first plastic package body 150 can be increased, so that the bonding force between the first plastic package body 150 and the L-shaped structure is increased, on the other hand, the extended heat dissipation plate 145 is attached to the surface of the first plastic package body 150, the first plastic package body 150 can be pressed, the warping phenomenon of the substrate 110 is reduced, and the layering problem of the back surfaces of the first chip 120 and the second chip 130 can be prevented.
It should be noted that, in this embodiment, the extended heat dissipation plate 145 and the heat dissipation column 140 are both made of metal materials, and the extended heat dissipation plate 145 is at least distributed on two sides of the edge of the top of the heat dissipation column 140, and is limited between the first chip 120 and the second chip 130, so that the extended heat dissipation plate 145 will not shield the first chip 120 and the second chip 130, and the performance of the device is ensured.
Fourth embodiment
Referring to fig. 14, the present embodiment provides a semiconductor package structure 100, whose basic structure and principle and technical effects are the same as those of the third embodiment, and for brevity, reference is made to the corresponding contents of the third embodiment where the description of the embodiment is not mentioned.
In this embodiment, the edge of the heat dissipation post 140 is provided with an extended heat dissipation plate 145, the extended heat dissipation plate 145 is attached to a side surface of the first plastic package body 150 away from the substrate 110, and the extended heat dissipation plate 145 covers a side surface of the first plastic package body 150 away from the substrate 110 and extends to the edge of the first plastic package body 150. Specifically, the heat dissipation plate 145 is expanded to entirely cover the surface of the entire first plastic package body 150, so that the contact area with the first plastic package body 150 is further improved, and the pressing function is better performed.
In this embodiment, the extended heat dissipation plate 145 and the heat dissipation post 140 are integrally formed, and made of a metal material, and the heat dissipation post 140 is connected to the metal layer 113, so that the extended heat dissipation plate 145 completely shields the first chip 120 and the second chip 130. In this case, the metal layer 113 is connected to the ground line in the wiring layer 115, so that the metal layer 113 can be grounded, and the expansion heat dissipation plate 145 further has the effect of partition electromagnetic shielding.
It should be noted that, in this embodiment, the expansion heat dissipation plate 145 may be implemented by adopting an electroplating manner, and by setting the expansion heat dissipation plate 145 that completely covers the surface of the first plastic package body 150, the contact area with the first plastic package body 150 can be further improved, and the lamination effect is better, and the heat dissipation plate can be directly and completely laminated on the surface of the first plastic package body 150, thereby playing a better role in preventing warpage.
Fifth embodiment
Referring to fig. 15, the present embodiment provides a semiconductor package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment or the third embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment or the third embodiment where the description of the present embodiment is not mentioned.
In this embodiment, a fourth chip 180 is further disposed on a side of the first plastic package 150 away from the substrate 110, and the fourth chip 180 is mounted on the heat dissipation post 140 and electrically connected to the substrate 110. Specifically, the fourth chip 180 is disposed corresponding to the heat dissipation area on the substrate 110 and is attached to the heat dissipation post 140, and the heat dissipation post 140 can perform a good supporting function.
In this embodiment, the fourth chip 180 is a front-mounted chip, and a conductive wire arc 181 is disposed on one side of the fourth chip 180 away from the substrate 110, the conductive wire arc 181 is connected with the substrate 110, and a filling adhesive layer 183 is further disposed on the substrate 110 and covers the conductive wire arc 181 and the fourth chip 180. Specifically, the fourth chip 180 is being mounted on the heat dissipation post 140, and the filling adhesive layer 183 covers the substrate 110 and the first plastic package body 150 at the same time, so that the fourth chip 180 and the conductive wire arc 181 are both covered, and good protection effect is achieved.
In this embodiment, the first chip 120 and the heat dissipation post 140 may also be fixed by using adhesive, specifically, the adhesive is filled between the first chip 120 and the heat dissipation post 140, so as to achieve a good adhesive fixing effect.
In this embodiment, the middle position of the heat dissipation post 140 may not need to be filled with plastic packaging material, so as to ensure the heat dissipation effect.
It should be noted that, here, the chip structure may also be stacked on the fourth chip 180, so as to further increase the stacking number of the devices.
The semiconductor package structure 100 provided in this embodiment can further increase the number of stacked package structures by stacking the fourth chips 180, thereby increasing the integration level of the device. Meanwhile, the filling adhesive layer 183 is arranged, so that the wire bonding structure can be effectively protected, and the structure reliability is improved.
Sixth embodiment
Referring to fig. 16, the present embodiment provides a semiconductor package structure 100, whose basic structure and principle and technical effects are the same as those of the third embodiment, and for brevity, reference is made to the corresponding contents of the third embodiment where the description of the embodiment is not mentioned.
In this embodiment, a fourth chip 180 is further disposed on a side of the first plastic package 150 away from the substrate 110, and the fourth chip 180 is mounted on the heat dissipation post 140 and electrically connected to the substrate 110. Specifically, the fourth chip 180 is disposed corresponding to the heat dissipation area on the substrate 110 and is attached to the heat dissipation post 140, and the heat dissipation post 140 can perform a good supporting function, and meanwhile, the fourth chip 180 adopts a flip-chip structure.
In this embodiment, the fourth chip 180 is a flip chip, the heat dissipation post 140 has conductivity, the fourth chip 180 is electrically connected to the substrate 110 through the heat dissipation post 140, and the substrate 110 is further provided with a third plastic package 190 covering the fourth chip 180. Specifically, the heat dissipation post 140 is connected with the metal layer 113, and the metal layer 113 is connected with the wiring layer 115 through the conductive post at the bottom, so that the fourth chip 180 can be electrically connected with the substrate 110 through the heat dissipation post 140, and meanwhile, the third plastic package body 190 can be completely coated on the surface of the first plastic package body 150, thereby playing a good role in protection.
In this embodiment, the heat dissipation post 140 is a copper post, and the fourth chip 180 is soldered to the heat dissipation post 140. And the heat dissipation post 140 is exposed outside the first plastic package body 150, and a portion of the heat dissipation post 140 extending out of the first plastic package body 150 is provided with a plurality of third grooves 191. By providing the third groove 191, the bonding force of the bottom of the third plastic package body 190 can be improved, thereby avoiding the delamination phenomenon between the third plastic package body 190 and the first plastic package body 150.
The semiconductor package structure 100 provided in this embodiment can further increase the number of stacked package structures by stacking the fourth chips 180, thereby increasing the integration level of the device. Meanwhile, by arranging the third groove 191, the bonding force of the bottom of the third plastic package body 190 can be further improved, so that layering phenomenon between the third plastic package body 190 and the first plastic package body 150 is avoided.
Seventh embodiment
Referring to fig. 17, the present embodiment provides a semiconductor package structure 100, whose basic structure and principle and technical effects are the same as those of the third embodiment, and for brevity, reference is made to the corresponding contents of the third embodiment where the description of the embodiment is not mentioned.
In this embodiment, a fourth chip 180 is further disposed on a side of the first plastic package 150 away from the substrate 110, and the fourth chip 180 is mounted on the heat dissipation post 140 and electrically connected to the substrate 110. The fourth chip 180 is a flip chip, the heat dissipation post 140 has conductivity, the fourth chip 180 is electrically connected with the substrate 110 through the heat dissipation post 140, and the substrate 110 is further provided with a filling adhesive layer 183 or a protective cover covering the fourth chip 180.
In this embodiment, the filling glue layer 183 is preferably used, and by setting the filling glue layer 183, a good protection effect can be achieved on the fourth chip 180, and the filling glue layer 183 can only cover the periphery of the fourth chip 180, so that the whole surface of the first plastic package body 150 is not required to be covered, and the cost is low.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (18)
1. A semiconductor package structure, comprising:
A substrate;
A first chip and a second chip which are attached to one side surface of the substrate at intervals;
the heat dissipation column is arranged on one side surface of the substrate and positioned between the first chip and the second chip;
the first plastic package body is arranged on one side surface of the substrate and at least coated outside the first chip and the second chip;
And a solder ball disposed on the other surface of the substrate;
The first chip and the second chip are electrically connected with the substrate, a metal layer is arranged on one side surface of the substrate, the bottom of the heat dissipation column is connected with the metal layer and used for dissipating heat of the substrate, and the solder balls are electrically connected with the substrate;
The semiconductor package structure further includes:
a third chip attached to the other surface of the substrate;
the second plastic package body is arranged on the other side surface of the substrate and is coated outside the third chip;
The solder balls are positioned on at least two sides of the second plastic package body.
2. The semiconductor package according to claim 1, wherein the first molding compound is further coated outside the heat dissipation post.
3. The semiconductor package according to claim 2, wherein a plurality of heat dissipation grooves are provided on the heat dissipation pillars, and each of the heat dissipation grooves penetrates from a surface of the heat dissipation pillar to a surface of the metal layer.
4. The semiconductor package according to claim 3, wherein the surface of the metal layer is further provided with a plurality of first grooves, and the plurality of first grooves are located at the bottom of the heat dissipation pillars and correspondingly communicate with the plurality of heat dissipation grooves.
5. The semiconductor package according to claim 2, wherein the first chip and the second chip have the same thickness, and a distance H1 between a side surface of the first plastic package away from the substrate and the first chip is greater than a distance H2 between a side surface of the first plastic package away from the substrate and the heat dissipation post.
6. The semiconductor package according to claim 5, wherein a distance H1 between a side surface of the first plastic package away from the substrate and the first chip is twice a distance H2 between a side surface of the first plastic package away from the substrate and the heat dissipation post.
7. The semiconductor package according to claim 1, wherein a wiring layer is provided in the substrate, a metal pad electrically connected to the wiring layer is provided on the other side surface of the substrate, and the solder ball is provided on the metal pad.
8. The semiconductor package according to claim 7, wherein the surface of the metal pad is further provided with a second recess, and the solder ball covers the second recess.
9. The semiconductor package according to claim 1, wherein the first molding compound has a relief opening formed therethrough to the substrate, the relief opening corresponding to the heat dissipation post such that the heat dissipation post is exposed outside the first molding compound.
10. The semiconductor package according to claim 1, wherein the first molding body is partially coated outside the heat dissipation post, and an end portion of the heat dissipation post away from the substrate extends out of the first molding body.
11. The semiconductor package according to claim 10, wherein an extended heat dissipation plate is provided at an edge of the heat dissipation post, and the extended heat dissipation plate is attached to a surface of the first plastic package body far away from the substrate.
12. The semiconductor package according to claim 11, wherein the extended heat spreader covers a surface of the first plastic package body away from the substrate and extends to an edge of the first plastic package body.
13. The semiconductor package according to any one of claims 10 to 12, wherein a fourth chip is further disposed on a side of the first molding compound away from the substrate, and the fourth chip is attached to the heat dissipation post and electrically connected to the substrate.
14. The semiconductor package according to claim 13, wherein the fourth chip is a front-mounted chip, and a conductive wire arc is disposed on a side of the fourth chip away from the substrate, the conductive wire arc is connected with the substrate, and a filling adhesive layer is further disposed on the substrate, wherein the filling adhesive layer is coated on the conductive wire arc and the fourth chip.
15. The semiconductor package according to claim 13, wherein the fourth chip is a flip chip, the heat dissipation post has conductivity, the fourth chip is electrically connected to the substrate through the heat dissipation post, and a third molding compound or a filling adhesive layer is further disposed on the substrate, and the third molding compound or the filling adhesive layer is coated outside the fourth chip.
16. The semiconductor package according to claim 15, wherein the portion of the heat dissipation post extending out of the first molding body is provided with a plurality of third grooves.
17. A method for manufacturing a semiconductor package structure according to claim 1, comprising:
forming a heat dissipation column on a substrate;
A first chip and a second chip are attached to the base plates at intervals on two sides of the heat dissipation column;
Forming a first plastic package body which is at least coated outside the first chip and the second chip on the substrate in a plastic package mode;
Turning over the substrate, and attaching a third chip on the substrate;
Forming a second plastic package body coated outside the third chip on the substrate in a plastic package mode;
Forming solder balls on the substrate;
The first chip, the second chip and the third chip are all electrically connected with the substrate, a metal layer is arranged on one side surface of the substrate, the bottom of the heat dissipation column is connected with the metal layer and used for dissipating heat of the substrate, and the solder balls are located on at least two sides of the second plastic package body and are electrically connected with the substrate.
18. The method of manufacturing a semiconductor package according to claim 17, wherein the step of forming the heat dissipation pillars on the substrate comprises:
forming a dry film layer on a substrate;
Etching the dry film layer to form an etched opening;
Forming a heat-dissipating stud within the etched opening;
removing the dry film layer;
and micro etching is performed on the bottom of the heat dissipation column to form a first groove.
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| CN115377079A (en) * | 2022-07-19 | 2022-11-22 | 杭州巨星科技股份有限公司 | An LED integrated package structure and manufacturing method with improved heat dissipation |
| CN115274580A (en) * | 2022-07-29 | 2022-11-01 | 华天科技(南京)有限公司 | Packaging design method and packaging structure for chip-on-back plastic package of substrate |
| CN116093075A (en) * | 2023-04-10 | 2023-05-09 | 北京华封集芯电子有限公司 | Chip and design method for realizing interconnection of various chips |
| CN120127067B (en) * | 2025-05-14 | 2025-08-22 | 甬矽电子(宁波)股份有限公司 | Stacked package structure and preparation method thereof |
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