CN114446168A - Manufacturing method of array substrate and array substrate - Google Patents
Manufacturing method of array substrate and array substrate Download PDFInfo
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- CN114446168A CN114446168A CN202210076979.5A CN202210076979A CN114446168A CN 114446168 A CN114446168 A CN 114446168A CN 202210076979 A CN202210076979 A CN 202210076979A CN 114446168 A CN114446168 A CN 114446168A
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Abstract
本申请实施例公开了一种阵列基板的制作方法以及阵列基板，阵列基板的制作方法包括以下步骤：在基板上形成过孔；在过孔内填充导电浆料以形成连接电极，连接电极包括设于过孔内的第一导电块、搭接于第一导电块的一端的第二导电块以及搭接于第一导电块的另一端的第三导电块，第二导电块和第三导电块设于过孔外；在基板的一侧形成第一走线，第一走线覆盖于基板和第二导电块上；在基板的另一侧形成第二走线，第二走线覆盖于基板和第三导电块上，可以解决显示面板的正面走向和背面走线难以通过过孔电性连接的技术问题。
The embodiment of the present application discloses a method for fabricating an array substrate and an array substrate. The fabricating method for the array substrate includes the following steps: forming a via hole on the substrate; filling the via hole with conductive paste to form a connection electrode, and the connection electrode includes setting The first conductive block in the via hole, the second conductive block overlapped with one end of the first conductive block, and the third conductive block overlapped with the other end of the first conductive block, the second conductive block and the third conductive block It is located outside the via hole; a first wiring is formed on one side of the substrate, and the first wiring is covered on the substrate and the second conductive block; a second wiring is formed on the other side of the substrate, and the second wiring is covered on the substrate and the third conductive block, the technical problem that the front direction of the display panel and the back wiring are difficult to be electrically connected through the via hole can be solved.
Description
Technical Field
The application relates to the field of display, in particular to a manufacturing method of an array substrate and the array substrate.
Background
With the development of display technology, a full-screen has become a hot spot of market pursuit. Limited by the current technology, the screen occupation ratio of the full screen can be up to more than 90%. The display panel generally includes a display area and a non-display area, and in order to realize a full screen, the size of the non-display area needs to be reduced, for example, the display panel adopts a narrow-frame or frameless design.
The packaging of the driver IC (chip) is particularly important for display panels that use narrow-frame or frameless designs, where the connection of the driver IC and the display panel is accomplished by a Bonding process. In the preparation process of the display panel, binding positions of the driving ICs are reserved. In order to realize a narrow frame or frameless design, a driving IC, such as a Chip On Film (COF), needs to be bent to the back of the display panel, and a bonding area of an external circuit needs to be disposed On the back of the display panel. However, the lines of the folded COF are easily damaged, which affects the conduction of the lines, and a large gap exists between the COF and the side surface of the display panel. Even with driver IC through binding the structure setting at display panel's back, then bind printed circuit board and driver IC in order to avoid COF's buckling, nevertheless because the restriction of technique, there is the gap still in current binding structure and display panel's side, need set up the frame of certain width and shelter from, can't realize the narrow frame or the no frame of display especially tiled display ware.
In view of the above drawbacks, a new back binding structure has appeared, in which the wires on the front side and the wires on the back side of the display panel are connected by means of the via holes, so as to transfer the binding region of the display panel to the back side of the display panel, thereby facilitating the design of a narrow frame or no frame. However, when the front surface and the back surface of the display panel are entirely coated with copper to form the wires, the copper layer is difficult to fill the via holes due to the small aperture of the via holes, so that the front surface wires and the back surface wires of the display panel cannot be normally connected.
Disclosure of Invention
The embodiment of the application provides a manufacturing method of an array substrate and the array substrate, which can solve the technical problem that front routing and back routing of a display panel are difficult to electrically connect through a via hole.
The embodiment of the application provides a manufacturing method of an array substrate, which comprises the following steps:
step B1, forming a via hole on the substrate;
step B2, filling conductive paste in the via hole to form a connection electrode, wherein the connection electrode comprises a first conductive block arranged in the via hole, a second conductive block lapped at one end of the first conductive block and a third conductive block lapped at the other end of the first conductive block, and the second conductive block and the third conductive block are arranged outside the via hole;
step B3, forming a first trace on one side of the substrate, forming a second trace on the other side of the substrate, wherein the first trace covers the substrate and the second conductive block, and the second trace covers the substrate and the third conductive block.
Optionally, in some embodiments of the present application, in the step B2, a cross-sectional area of the second conductive block is larger than a cross-sectional area of the first conductive block, and the second conductive block covers the substrate; and/or the presence of a gas in the gas,
the cross sectional area of the third conductive block is larger than that of the first conductive block, and the third conductive block covers the substrate.
Optionally, in some embodiments of the present application, the aperture of the via is greater than or equal to 20 microns.
Optionally, in some embodiments of the present application, in step B1, the via hole is formed on the substrate by laser drilling;
in the step B2, filling the conductive paste in the via hole by using an inkjet printing method.
Optionally, in some embodiments of the present application, the step B1 further includes: and forming a flow guide groove on the substrate, wherein the flow guide groove is communicated with the corresponding through hole.
The embodiment of the present application further provides an array substrate, including:
a substrate provided with a via hole;
the connection electrode comprises a first conductive block arranged in the through hole, a second conductive block lapped at one end of the first conductive block and a third conductive block lapped at the other end of the first conductive block, and the second conductive block and the third conductive block are arranged outside the through hole;
the first routing is arranged on one side of the substrate and covers the substrate and the second conductive blocks; and
and the second wire is arranged on the other side of the substrate and covers the substrate and the third conductive block.
Optionally, in some embodiments of the present application, a cross-sectional area of the second conductive block is larger than a cross-sectional area of the first conductive block, and the second conductive block covers the substrate.
Optionally, in some embodiments of the present application, a cross-sectional area of the third conductive block is larger than a cross-sectional area of the first conductive block, and the third conductive block covers the substrate.
Optionally, in some embodiments of the present application, the aperture of the via is greater than or equal to 20 microns.
Optionally, in some embodiments of the present application, the substrate is further provided with a diversion trench, and the diversion trench is communicated with the corresponding via hole.
According to the manufacturing method of the array substrate and the array substrate, the conductive paste is filled in the via hole to form the connecting electrode, compared with a mode that the whole surface is coated with copper, the conductive paste has fluidity and is easier to fill the via hole, so that a first wire formed subsequently is electrically connected with a second wire through the connecting electrode, and the reliability of the array substrate is effectively improved; in addition, the connection electrode is including locating the first conducting block in the downthehole, overlap joint in the second conducting block of the one end of first conducting block and overlap joint in the third conducting block of the other end of first conducting block, second conducting block and third conducting block locate outside the via hole, the surface area that the connection electrode exposes outside promptly is big, can increase the area of contact of the line of walking of the relative both sides of connection electrode and array substrate, make the contact of the line of walking of the relative both sides of connection electrode and array substrate inseparabler, be difficult to break away from.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic top view of a first substrate according to an embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional view taken along line A-A of FIG. 2;
fig. 4 is a schematic diagram of forming a connection electrode on a first substrate according to an embodiment of the present disclosure;
fig. 5 is a schematic top view of a first substrate with a connection electrode formed thereon according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of forming a first conductive layer and a second conductive layer on a first substrate according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram illustrating a first conductive layer and a second conductive layer on a first substrate after patterning according to an embodiment of the present disclosure;
fig. 8 is a schematic top view of a second substrate according to an embodiment of the present disclosure;
FIG. 9 is a schematic cross-sectional view taken along line B-B of FIG. 8;
fig. 10 is a schematic diagram of forming a connection electrode on a second substrate according to an embodiment of the present disclosure;
fig. 11 is a schematic top view of a second substrate with a connection electrode formed thereon according to an embodiment of the present disclosure;
fig. 12 is a schematic diagram of forming a first conductive layer and a second conductive layer on a second substrate according to an embodiment of the present disclosure;
fig. 13 is a schematic diagram of a first conductive layer and a second conductive layer on a second substrate after patterning according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the application provides a manufacturing method of an array substrate and the array substrate. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
Referring to fig. 1, an embodiment of the present application provides a method for manufacturing an array substrate, including:
step B1, as shown in fig. 2 and 3, forming a via hole 110 on the substrate 100;
step B2, as shown in fig. 4 and 5, filling conductive paste in the via hole 110 to form a connection electrode 200, where the connection electrode 200 includes a first conductive block 210 disposed in the via hole 110, a second conductive block 220 overlapping one end of the first conductive block 210, and a third conductive block 230 overlapping the other end of the first conductive block 210, and the second conductive block 220 and the third conductive block 230 are disposed outside the via hole 110;
step B3, as shown in fig. 6 and 7, forming a first trace 310 on one side of the substrate 100, forming a second trace 410 on the other side of the substrate 100, wherein the first trace 310 covers the substrate 100 and the second conductive block 220, and the second trace 410 covers the substrate 100 and the third conductive block 230, thereby manufacturing the array substrate.
In the embodiment of the application, the conductive paste is filled in the via hole 110 to form the connection electrode 200, and compared with a mode of covering copper on the whole surface, the conductive paste has fluidity and is easier to fill the via hole 110, so that the first trace 310 formed subsequently is electrically connected with the second trace 410 through the connection electrode 200, and the reliability of the array substrate is effectively improved; in addition, the connection electrode 200 includes a first conductive block 210 disposed in the via hole 110, a second conductive block 220 overlapping one end of the first conductive block 210, and a third conductive block 230 overlapping the other end of the first conductive block 210, the second conductive block 220 and the third conductive block 230 are disposed outside the via hole 110, that is, the exposed surface area of the connection electrode 200 is large, which can increase the contact area between the connection electrode 200 and the traces on the two opposite sides of the array substrate, so that the connection electrode 200 and the traces on the two opposite sides of the array substrate are in closer contact and are not easy to be separated.
Specifically, in step B1, the number of the vias 110 may be multiple; in the step B3, the number of the first traces 310 and the second traces 410 may be multiple, and each of the first traces 310 corresponds to one via 110 and one second trace 410. Of course, the number of the vias 110, the first traces 310 and the second traces 410 may be adjusted appropriately according to the selection and specific requirements of the actual situation, and is not limited herein.
Specifically, the manufactured array substrate comprises a display area AA and a non-display area NA, the via hole 110, the connecting electrode 200, the first wire 310 and the second wire 410 are arranged on the non-display area NA and are mainly used for achieving back binding of the driving IC, the driving IC can be directly bound on the second wire 410 and can also be bound on the second wire 410 through the flexible circuit board, and the narrow-frame or frameless design is facilitated.
Specifically, in the step B1, the via hole 110 may be formed on the substrate 100 by laser drilling, which has the advantages of high speed and high efficiency compared to other drilling methods, and can improve the production capacity; in addition, laser drilling can obtain a large depth-diameter ratio, and the aperture of the via hole 110 manufactured by adopting the laser drilling mode is small, so that the design of a narrow frame or no frame is favorably realized.
Specifically, the aperture of the via 110 is greater than or equal to 20 microns, for example, the aperture of the via 110 may be 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns, 100 microns, or more. Of course, the aperture of the via hole 110 can be adjusted in the same year according to the selection of the actual situation and the specific requirement, and is not limited herein.
Specifically, in the embodiment of the present application, the material of the substrate 100 may be glass or polyimide, and of course, the material of the substrate 100 may be modified appropriately according to the selection of the actual situation and the specific requirement, and is not limited herein.
Specifically, in the step B2, the conductive paste may be filled in the via hole 110 by using an inkjet printing method, compared with other processes, the inkjet printing process may achieve an accuracy of less than 10 micrometers, and the conductive paste may be accurately filled in the via hole 110 by aligning the nozzle 500 with the via hole 110.
Specifically, in the embodiment of the present application, the conductive paste includes an organic vehicle and nano conductive particles, the nano conductive particles are dispersed in the organic vehicle, and the conductive paste has a fluid property. When the conductive paste is filled in the via hole 110, since the conductive paste has a certain viscosity and the aperture of the via hole 110 is small, the via hole 110 is a capillary hole, the via hole 110 is beneficial to the conductive paste to generate a capillary phenomenon, and the conductive paste cannot flow out of the via hole 110. In this embodiment, the spray head 500 sprays the excessive conductive paste toward the via hole 110 such that the conductive paste overflows from both ends of the via hole 110, thereby forming the second and third conductive blocks 220 and 230.
Specifically, in the present embodiment, since the conductive paste has fluid characteristics and is influenced by gravity, the volume of the third conductive bump 230 is greater than the volume of the second conductive bump 220 in the connecting electrode 200.
Specifically, the organic carrier comprises a high polymer resin and a solvent, wherein the high polymer resin is selected from one or more of cellulose acetate butyrate, acrylic resin, melamine formaldehyde resin, polyamino resin, vinyl chloride-vinyl acetate copolymer resin, polyoxyl resin and polyurethane resin, and the solvent is selected from one or more of diethylene glycol butyl ether acetate, isophorone, dipropylene glycol methyl ether, dimethyl glutarate, dimethyl succinate and dimethyl adipate. It is understood that the specific materials of the polymer resin and the solvent may be modified as appropriate according to the choice of actual conditions and the specific requirements, and are not limited thereto.
Specifically, the nano conductive particles are selected from one or more of gold powder, silver powder, aluminum powder, copper powder, nickel powder, carbon nanotubes, graphite, graphene, carbon fibers and carbon black. It is understood that the specific material of the nano conductive particles can be modified appropriately according to the selection of the actual situation and the specific requirement, and is not limited thereto.
Specifically, in the step B2, the material of the connection electrode 200 prepared by using the conductive paste includes the above-mentioned high polymer resin and the nano conductive particles.
Specifically, in step B2, as shown in fig. 4, 5 and 7, the cross-sectional area of the second conductive bump 220 is larger than that of the first conductive bump 210, and the second conductive bump 220 is covered on the substrate 100. Under this structure, the exposed surface area of the connection electrode 200 is large, which can increase the contact area between the connection electrode 200 and the first trace 310, so that the connection electrode 200 is in closer contact with the first trace 310 and is not easy to separate.
Specifically, in step B2, the cross-sectional area of the third conductive bump 230 is larger than that of the first conductive bump 210, and the third conductive bump 230 is covered on the substrate 100. Under this structure, the exposed surface area of the connection electrode 200 is large, which can increase the contact area between the connection electrode 200 and the second trace 410, so that the connection electrode 200 is in closer contact with the second trace 410 and is not easy to separate.
Specifically, in the embodiment of the present application, the shape of the via hole 110 may be a circle, and of course, according to the selection of the actual situation and the specific requirement, the shape of the via hole 110 may also be a polygon (triangle, quadrangle, pentagon, etc.), an arc or other irregular figures, which is not limited herein.
Specifically, when the conductive paste is injected into the via hole 110, the via hole 110 is not easily filled with the conductive paste due to the small aperture of the via hole 110, and the prepared connection electrode 200 contains bubbles, resulting in poor contact between the first trace 310 and the second trace 410. In order to solve the above problem, as shown in fig. 8 and 9, the step B1 further includes: a guide channel 120 is formed on the substrate 100, and the guide channel 120 communicates with the corresponding via hole 110. With this structure, in the subsequent step B2, as shown in fig. 10 and 11, when the conductive paste is injected into the via hole 110, air in the via hole 110 may be discharged from the flow guide groove 120, which is beneficial to filling the via hole 110 with the conductive paste, so as to eliminate air bubbles in the connection electrode 200, and thus, the first trace 310 and the second trace 410 are beneficial to electrically connect, and reliability is improved.
Specifically, the guiding trench 120 penetrates through the substrate 100, and the aperture of the guiding trench 120 is smaller than that of the via hole 110. In the step B2, as shown in fig. 10 and 11, the via hole 110 is filled with the conductive paste by inkjet printing, the nozzle 500 sprays the conductive paste toward the via hole 110, and due to the gravity, the conductive paste overflows from the lower end of the via hole 110 and covers the lower end of the diversion trench 120, so that the lower end of the diversion trench 120 is closed; after the via hole 110 is filled with the conductive paste, the conductive paste may overflow from the upper end of the via hole 110, and the conductive paste overflowing from the upper end of the via hole 110 may cover the upper end of the guiding gutter 120, and since the aperture of the guiding gutter 120 is small, the conductive paste overflowing from the upper end of the via hole 110 may not fill the guiding gutter 120. In this embodiment, the conductive paste overflowing from the upper end of the via hole 110 forms the second conductive block 220, and the conductive paste overflowing from the lower end of the via hole 110 forms the third conductive block 230. In this embodiment, a portion of the conductive paste overflows from the via hole 110 to the guiding trench 120, so that a portion of the first conductive bump 210 connected to the electrode 200 is disposed in the guiding trench 120.
Specifically, as shown in fig. 6, 7, 12 and 13, the step B3 includes:
step B31, forming a first conductive layer 300 covering the substrate 100 and the second conductive bump 220 on one side of the substrate 100;
step B32, forming a second conductive layer 400 covering the substrate 100 and the third conductive block 230 on the other side of the substrate 100;
step B33, performing patterning on the first conductive layer 300 to obtain a first trace 310;
step B34, performing patterning process on the second conductive layer 400 to obtain the second trace 410. In this embodiment, the sequence of step B31, step B32, step B33 and step B34 may be adjusted as appropriate, as long as it is ensured that step B33 is after step B31, and step B34 is after step B32, which is not limited herein.
Specifically, in the steps B31 and B33, the first conductive layer 300 and the second conductive layer 400 may be formed by physical vapor deposition, and of course, the manufacturing process of the first conductive layer 300 and the second conductive layer 400 may be modified according to the selection of the actual situation and the specific requirement, and is not limited herein.
Specifically, the material of the first trace 310 (the first conductive layer 300) and the second trace 410 (the second conductive layer 400) may be selected from one or more materials of copper, molybdenum, aluminum, and titanium. It is understood that, according to the selection of actual situations and the specific requirement, the specific materials of the first trace 310 and the second trace 410 may be modified appropriately, and are not limited herein.
Referring to fig. 7 and 13, an embodiment of the present application further provides an array substrate manufactured by the above manufacturing method, where the array substrate includes a substrate 100, a connection electrode 200, a first trace 310 and a second trace 410, the substrate 100 is provided with a via hole 110, the connection electrode 200 includes a first conductive block 210 disposed in the via hole 110, a second conductive block 220 overlapping one end of the first conductive block 210, and a third conductive block 230 overlapping the other end of the first conductive block 210, and the second conductive block 220 and the third conductive block 230 are disposed outside the via hole 110; the first trace 310 is disposed on one side of the substrate 100, and the first trace 310 covers the substrate 100 and the second conductive bump 220; the second trace 410 is disposed on the other side of the substrate 100, and the second trace 410 covers the substrate 100 and the third conductive bump 230.
Specifically, in the array substrate according to the embodiment of the present application, the number of the vias 110 may be multiple, the number of the first traces 310 and the number of the second traces 410 may be multiple, and each first trace 310 corresponds to one via 110 and one second trace 410. Of course, the number of the vias 110, the first traces 310 and the second traces 410 may be appropriately adjusted according to the selection and the specific requirement of the actual situation, and is not limited herein.
Specifically, the array substrate includes a display area AA and a non-display area NA, and the via hole 110, the connection electrode 200, the first wire 310 and the second wire 410 are disposed on the non-display area NA, and are mainly used for achieving back binding of the driver IC, and the driver IC may be directly bound to the second wire 410, or bound to the second wire 410 through the flexible circuit board, which is beneficial to achieving narrow-frame or frameless design.
Specifically, the aperture of the via 110 is greater than or equal to 20 microns, for example, the aperture of the via 110 may be 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns, 100 microns, or more. Of course, the aperture of the via hole 110 can be adjusted in the same year according to the selection of the actual situation and the specific requirement, and is not limited herein.
Specifically, in the array substrate according to the embodiment of the present application, the material of the substrate 100 may be glass or polyimide, and certainly, the material of the substrate 100 may be modified appropriately according to the selection of the actual situation and the specific requirement, which is not limited herein.
Specifically, in the embodiment of the present application, since the aperture of the via hole 110 is small, and the via hole 110 is a capillary hole, in the process of forming the connection electrode 200, the via hole 110 is beneficial to the conductive paste to generate a capillary phenomenon, and the conductive paste cannot flow out from the via hole 110, so that the connection electrode 200 is stably adsorbed in the via hole 110.
Specifically, in the present embodiment, since the conductive paste has fluid characteristics and is influenced by gravity, the volume of the third conductive bump 230 is greater than the volume of the second conductive bump 220 in the connecting electrode 200.
Specifically, in the array substrate according to the embodiment of the present application, the material of the connection electrode 200 includes a polymer resin and nano conductive particles, and the nano conductive particles are dispersed in the polymer resin.
Specifically, in the array substrate of the embodiment of the present application, the high polymer resin is selected from one or more of cellulose acetate butyrate, acrylic resin, melamine formaldehyde resin, polyamino resin, vinyl chloride-vinyl acetate copolymer resin, polyoxyl resin, and polyurethane resin. It is understood that the specific material of the high polymer resin may be modified as appropriate according to the choice of actual conditions and the specific requirement, and is not limited thereto.
Specifically, the nano conductive particles are selected from one or more of gold powder, silver powder, aluminum powder, copper powder, nickel powder, carbon nanotubes, graphite, graphene, carbon fibers and carbon black. It is understood that the specific material of the nano conductive particles can be modified appropriately according to the selection of the actual situation and the specific requirement, and is not limited thereto.
Specifically, as shown in fig. 4, 5 and 7, the cross-sectional area of the second conductive block 220 is larger than that of the first conductive block 210, and the second conductive block 220 covers the substrate 100. Under this structure, the exposed surface area of the connection electrode 200 is large, which can increase the contact area between the connection electrode 200 and the first trace 310, so that the connection electrode 200 is in closer contact with the first trace 310 and is not easy to separate.
Specifically, the cross-sectional area of the third conductive block 230 is larger than that of the first conductive block 210, and the third conductive block 230 covers the substrate 100. Under this structure, the exposed surface area of the connection electrode 200 is large, which can increase the contact area between the connection electrode 200 and the second trace 410, so that the connection electrode 200 is in closer contact with the second trace 410 and is not easy to separate.
Specifically, in the array substrate according to the embodiment of the present application, the shape of the via hole 110 may be a circle, and of course, the shape of the via hole 110 may also be a polygon (triangle, quadrangle, pentagon, etc.), an arc or other irregular figures according to selection of actual situations and specific requirements, which is not limited herein.
Specifically, as shown in fig. 8 and 9, the substrate 100 is further provided with a guiding trench 120, and the guiding trench 120 is communicated with the corresponding via hole 110. Under this structure, as shown in fig. 10 and 11, when the conductive paste is injected into the via hole 110, the air in the via hole 110 may be discharged from the guiding gutter 120, which is beneficial to filling the conductive paste into the via hole 110, thereby eliminating the air bubbles in the connection electrode 200, being beneficial to electrically connecting the first trace 310 and the second trace 410, and improving the reliability.
Specifically, the guiding trench 120 penetrates through the substrate 100, and the aperture of the guiding trench 120 is smaller than that of the via hole 110. As shown in fig. 10 and 11, the via hole 110 is filled with the conductive paste by an inkjet printing method, the nozzle 500 sprays the conductive paste toward the via hole 110, and due to the gravity, the conductive paste overflows from the lower end of the via hole 110 and covers the lower end of the diversion trench 120, so that the lower end of the diversion trench 120 is closed; after the via hole 110 is filled with the conductive paste, the conductive paste may overflow from the upper end of the via hole 110, and the conductive paste overflowing from the upper end of the via hole 110 may cover the upper end of the guiding gutter 120, and since the aperture of the guiding gutter 120 is small, the conductive paste overflowing from the upper end of the via hole 110 may not fill the guiding gutter 120. In this embodiment, the conductive paste overflowing from the upper end of the via hole 110 forms the second conductive block 220, and the conductive paste overflowing from the lower end of the via hole 110 forms the third conductive block 230. In this embodiment, a portion of the conductive paste overflows from the via hole 110 to the guiding trench 120, so that a portion of the first conductive bump 210 connected to the electrode 200 is disposed in the guiding trench 120.
Specifically, the material of the first trace 310 and the second trace 410 may be selected from one or more of copper, molybdenum, aluminum, and titanium. It is understood that, according to the selection of actual situations and the specific requirement, the specific materials of the first trace 310 and the second trace 410 may be modified appropriately, and are not limited herein.
The above detailed description is made on the manufacturing method of the array substrate and the array substrate provided in the embodiments of the present application, and specific examples are applied in the present application to explain the principle and the implementation of the present application, and the description of the above embodiments is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A manufacturing method of an array substrate is characterized by comprising the following steps:
step B1, forming a via hole on the substrate;
step B2, filling conductive paste in the via hole to form a connection electrode, wherein the connection electrode comprises a first conductive block arranged in the via hole, a second conductive block lapped at one end of the first conductive block and a third conductive block lapped at the other end of the first conductive block, and the second conductive block and the third conductive block are arranged outside the via hole;
step B3, forming a first trace on one side of the substrate, forming a second trace on the other side of the substrate, wherein the first trace covers the substrate and the second conductive block, and the second trace covers the substrate and the third conductive block.
2. The method for manufacturing an array substrate according to claim 1, wherein in the step B2, the cross-sectional area of the second conductive block is larger than that of the first conductive block, and the second conductive block covers the substrate; and/or the presence of a gas in the gas,
the cross sectional area of the third conductive block is larger than that of the first conductive block, and the third conductive block covers the substrate.
3. The method for manufacturing the array substrate according to claim 1, wherein the aperture of the via hole is greater than or equal to 20 μm.
4. The method for manufacturing an array substrate according to claim 1, wherein in the step B1, the via hole is formed on the substrate by laser drilling;
in the step B2, the conductive paste is filled in the via hole by using an inkjet printing method.
5. The method for manufacturing an array substrate according to any one of claims 1 to 4, wherein the step B1 further comprises: and forming a flow guide groove on the substrate, wherein the flow guide groove is communicated with the corresponding through hole.
6. An array substrate, comprising:
a substrate provided with a via hole;
the connection electrode comprises a first conductive block arranged in the through hole, a second conductive block lapped at one end of the first conductive block and a third conductive block lapped at the other end of the first conductive block, and the second conductive block and the third conductive block are arranged outside the through hole;
the first routing is arranged on one side of the substrate and covers the substrate and the second conductive blocks; and
and the second wire is arranged on the other side of the substrate and covers the substrate and the third conductive block.
7. The array substrate of claim 6, wherein the cross-sectional area of the second conductive block is larger than the cross-sectional area of the first conductive block, and the second conductive block covers the substrate.
8. The array substrate of claim 6, wherein the cross-sectional area of the third conductive block is larger than the cross-sectional area of the first conductive block, and the third conductive block covers the substrate.
9. The array substrate of claim 6, wherein the via has an aperture of greater than or equal to 20 microns.
10. The array substrate according to any one of claims 6 to 9, wherein the substrate is further provided with a flow guide groove, and the flow guide groove is communicated with the corresponding via hole.
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| CN118946063A (en) * | 2024-08-20 | 2024-11-12 | 华为技术有限公司 | Back cover and electronic equipment |
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