CN114428639A - Instruction reduction method and system for bytecode instruction set - Google Patents

Abstract

The invention relates to an instruction compaction method and system of a byte code instruction set. The method can optimize the instruction of assigning the constant to the register and the instruction using the register as the operand in the initial instruction into the instruction with the constant operand, or directly generate the instruction with the constant operand, convert the instruction accessing the example domain of the current example or generate the special instruction accessing the example domain of the current example, encode the index operand of the sub-constant pool in the instruction into the operation code adjacent to the instruction, determine the type of the sub-constant pool through the operation code, separate the operand with variable length in the instruction with variable length from the instruction code, generate the pseudo instruction initialized in the static domain, replace the traditional static domain component, optimize the instruction repeatedly using the register into the instruction multiplexing the register, and compound a group of instructions with similar functions and unusual functions into one instruction. The method of the invention can reduce the length of the byte code and improve the execution performance of the byte code.

Description

Instruction reduction method and system for bytecode instruction set

technical field

The invention belongs to the technical field of instruction set simplification, and in particular relates to an instruction simplification method and system for a bytecode instruction set.

Background technique

A virtual machine is an abstract computer generated by a software application program or instruction sequence executed by a processor. The virtual machine can execute the instruction set supported by the virtual machine. The instruction set includes two types of instruction sets, operand stack-based and register-based. The instruction set based on the operand stack, compared with the instruction set based on the register, adopts the stack frame structure. The method call process involves pushing and popping from the stack, and the bytecode execution process also involves the stacking and popping of the operand stack. , although the RAM overhead is small, the execution efficiency is low.

SUMMARY OF THE INVENTION

In view of the defects existing in the prior art, the purpose of the present invention is to provide a method and system for reducing the instruction of a register-based bytecode instruction set. The method of the present invention can optimize the instructions that assign constants to registers and the instructions that use registers as operands in the initial instructions into reduced instructions, or directly generate reduced instructions with constants, and convert the instructions that access the current instance domain into accessing the current instance. Domain-specific instructions, encode the constant pool index operand in the instruction to the opcode position next to the instruction, separate the variable-length operand in each instruction from the instruction code, and generate a pseudo-instruction for static domain initialization, which can be replaced by the pseudo-instruction The traditional static domain component optimizes the instruction that reuses the register into the instruction that reuses the register, and combines a group of similar functions and less commonly used instructions into one instruction. Through the above steps, the length of the bytecode can be reduced, and the execution performance of the bytecode can be improved.

In order to achieve the above purpose, the technical solution adopted in the present invention is: in the initial instruction, the instruction that assigns a constant to a register and the instruction that uses the register as an operand are optimized to obtain a simplified instruction that directly uses the constant operand, or Directly generate a simplified instruction using constant operands; convert the instruction of the register corresponding to the this parameter of the method in the initial instruction that accesses the instance domain of the method according to the preset instruction format, and obtain the instance domain-specific instruction for accessing the current instance; The constant pool is divided into a plurality of sub-constant pools, the constant pool index in the instruction is the sub-constant pool index, and the sub-constant pool index helps the instruction to use the encoding method of the shorter sub-constant pool index; the constant pool of the initial instruction is The index operand is encoded to the position of the opcode next to the instruction; thus, the opcode of the instruction using the constant pool index is obtained through the position of the constant pool index, and the type of the sub-constant pool is determined by the opcode; the initial instruction The variable-length operand is separated from the instruction code; the static field type and initial configuration value of the static field in the initial instruction are obtained, and a pseudo-instruction corresponding to each static field is generated, and the pseudo-instruction can replace the traditional static field component; Optimize the instructions that reuse registers to obtain instructions that multiplex registers; combine a group of instructions with similar functions into one instruction, and use the operation type operand in the instruction to specify the operation type of the combined instruction to obtain the corresponding compound multi-operation instruction.

Further, the instructions for assigning constants to registers include arithmetic operation and logical operation instructions, jump instructions after comparison with literal constants, and array member access instructions.

Further, converting the object of accessing the instance domain in the initial instruction to the instruction corresponding to the register of the this parameter of the method is converted according to the preset instruction format to obtain the instance domain-specific instruction for accessing the current instance, including: The instruction of the register corresponding to the this parameter of the method deletes the operand of the specified instance according to the preset instruction format, and obtains the instance domain-specific instruction for accessing the current instance; the instance domain-specific instruction for accessing the current instance can be further optimized and can be specified by default. The register to set or return the result to.

Further, the encoding the constant pool index operand in each instruction of the initial instruction to the opcode immediately adjacent to the instruction includes: uniformly encoding the constant pool index operand in each instruction to the back of the specified code; or, The constant pool index operand in each instruction is uniformly encoded to the front of the instruction code.

An instruction reduction system of a bytecode instruction set, comprising the following devices: a first merging processing device for performing optimization processing on an instruction that assigns a constant to a register and an instruction that uses a register as an operand in the initial instruction, to obtain Directly using a reduced instruction of constant operands, or directly generating a reduced instruction using constant operands; an instruction conversion device for converting the object accessing the instance domain in the initial instruction to the instruction corresponding to the register of the this parameter of the method according to the preset instruction The format is converted to obtain the instance domain-specific instruction for accessing the current instance; the constant pool splitting device is used to split the constant pool into multiple sub-constant pools, and the constant pool index in the instruction is the sub-constant pool index; constant pool index operation A number encoding device for encoding the operand of the constant pool index in each instruction of the initial instruction to the opcode of the next instruction; thereby obtaining the opcode of the instruction using the constant pool index through the position of the constant pool index, and by The operation code determines the type of the sub-constant pool; the operand separation device is used to separate the variable-length operand in each instruction in the initial instruction from the instruction code; the pseudo-instruction generation device is used to obtain the initial instruction The static field type and initial configuration value of the static field instruction in the instruction generate pseudo-instructions corresponding to each static field; the second merging processing device is used to optimize the instruction of the repeated use of the register, and obtain the instruction of the multiplexed register; The compound multi-operation instruction obtaining device is used for compounding a group of instructions with similar functions into one instruction, and using the operation type operand in the instruction to specify the operation type of the compounded instruction to obtain the corresponding compound multi-operation instruction.

Further, the instructions for assigning constants to registers include arithmetic operation and logical operation instructions, jump instructions after comparison with literal constants, and array member access instructions.

Further, the instruction conversion device includes a unit: a register operand deletion unit, which is used to delete the instruction of the corresponding register of the this parameter of the method for the object of the access instance domain to delete the operand of the specified instance by the preset instruction format, and obtain the access to the current instance. Instance domain-specific instructions; accessing the instance-specific instructions of the current instance can be further optimized, and the register to be set or the result returned can be specified by default.

Further, the constant pool index operand encoding device includes a first encoding unit or a second encoding unit: the first encoding unit is used to uniformly encode the constant pool index operand in each instruction to the back of the specified code; The second encoding unit is used for uniformly encoding the constant pool index operand in each instruction to the front of the instruction code.

The effect of the present invention is: by adopting the method of the present invention, the instruction of assigning a constant to the register in the initial instruction and the instruction of using the register as an operand can be optimized into a reduced instruction, or a reduced instruction with a constant can be directly generated, and the access The instruction of the current instance domain is converted into a specific instruction to access the current instance domain, the constant pool index operand in the instruction is encoded into the opcode of the next instruction, the variable-length operand in each instruction is separated from the instruction code, and a static domain is generated. The initialized pseudo-instruction adjusts the instruction length according to the configuration item, optimizes the instruction that reuses the register into the instruction of multiplexing the register, and combines a group of instructions with similar functions into one instruction. Through the above steps, the initial instruction is simplified and then the instruction is simplified, so that the length of the bytecode can be reduced, and the execution performance of the bytecode can be improved.

Description of drawings

Fig. 1 is the flow chart of the method of the present invention;

Fig. 2 is the structure diagram of the system of the present invention;

Detailed ways

The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

As shown in FIG. 1, an instruction reduction method of a bytecode instruction set, the instruction reduction method of the bytecode instruction set is applied in a user terminal, and the instruction reduction method of the bytecode instruction set is installed in the user terminal by The user terminal is a terminal device used to execute the instruction reduction method of the bytecode instruction set to convert the initial code instruction, such as a desktop computer, a laptop computer, a tablet computer or a mobile phone, etc., including the following steps:

S110. Perform optimization processing on the instruction that assigns the constant to the register and the instruction that uses the register as an operand to obtain a reduced instruction that directly uses the constant operand, or directly generates a reduced instruction that uses the constant operand.

The initial instruction consists of multiple instructions. Each instruction consists of an opcode and an operand. The opcode specifies the operation to be performed. The instruction may contain one or more operands or no operands. The operands are Indicates the value of the operation required by this instruction.

The above-mentioned rules for performing instruction optimization processing in this embodiment may be configured in the above-mentioned bytecode instruction set, and the bytecode instruction set may be a register-based virtual machine instruction set, and the instruction set is used for intelligent SE and security MCU chips. Class resource-constrained devices, object-oriented, architecture-neutral programs, specially designed for virtual machines of resource-constrained devices such as intelligent SE and secure MCU chips, reducing the size of bytecodes as much as possible, not only It can reduce the demand for persistent storage of the chip, and can improve the execution efficiency of the code.

Specifically, the register in this embodiment is 16 bits, and a basic data unit in the instruction represents a 16-bit binary register. For example, the bytecodes of boolean, byte, short, reference type and returnAddress type all occupy a basic data unit , that is, only one register is required; if the bytecode of the int type needs to occupy two basic data units, it needs two consecutively numbered register pairs to represent.

An instruction that assigns a constant to a specified register and an instruction that uses the register as an operand can be optimized to an instruction that directly uses a constant operand, or directly generate a reduced instruction that uses a constant operand. In one embodiment, the instructions for assigning constants to registers include arithmetic and logical operation instructions, jump after comparison instructions with literal constants, and access array member instructions.

Taking the addition operation as an example, the above merging process will be described. The following two unoptimized instructions can optimize a reduced instruction.

const-c4 rC C assigns the constant C to the register rC (the instruction to assign the constant to the specified register);

add rA rA rC Add the values in registers rA and rC, and assign the result to register rA (instructions that use registers as operands)

After the merging process, it can be reduced to add-c4 rA C Add the value of the constant C and the register rA, and assign the result to the register rA (instructions that directly use the constant operand). The method of performing similar merging operations for other instructions to simplify will not be described one by one.

Arithmetic and logical operation instructions are shown in Table 1.

Table 1

instruction notation code Instruction encoding type Instruction function description add-c4 rA B op A|B rA=rA+B add-c8 rAA rBB CC op AA BB CC rAA=rBB+CC sub-c8 rAA rBB CC op AA BB CC rAA=rBB-CC and-c8 rAA rBB CC op AA BB CC rAA=rBB&CC or-c8 rAA, rBB, CC op AA BB CC rAA=rBB|CC xor-c8 rAA, rBB, CC op AA BB CC rAA=rBB^CC

The jump instructions after comparison with literals are shown in Table 2.

Table 2

The access array member instructions are shown in Table 3.

table 3

Specify the constant value index or specify the constant value index and assign the specified constant value. Since the simplified instruction obtained after the simplification processing in the above manner does not require the instruction of assigning constants to the register, the length of the bytecode is reduced, and the execution performance of the instruction can be improved without reading the constant from the register.

S120: Convert the instruction in the initial instruction that accesses the instance domain to the register corresponding to the this parameter of the method according to the preset instruction format, to obtain an instance domain-specific instruction for accessing the current instance.

Specifically, the object accessing the instance domain is the instruction of the register corresponding to the this parameter of the method, and the operand of the specified instance is deleted according to the preset instruction format, and the instance domain-specific instruction for accessing the current instance is obtained; the instance domain-specific instruction of the current instance can be For further optimization, the register to be set or the result to be returned can be specified by default.

The instruction to access the general format of the instance field, take the instance field of the object type as an example to illustrate: the code of the getfield-o rAArBB CCcpi instruction is op AA BB CC, the length of the instruction is 4 bytes, and rAA saves the returned instance field. value, rBB is the object to access the instance domain, CC is the constant pool index of the instance domain, and the specific instance domain in the object is specified. If the object accessing the instance domain is the register corresponding to the this parameter, that is, the register corresponding to the first parameter of the method, by designing a new instruction format, the operand rBB is not included (that is, it is implicitly the current instance specified by the this parameter of the method). ), so that the instruction can reduce one register operand, the byte code is reduced by one byte length, and the execution performance can be improved by reducing one read register when executing the instruction. The instruction code specifies the result register by default, and one register can also be reduced, further reducing the length of the bytecode.

The instance domain-specific instructions for accessing the current instance are shown in Table 4.

Table 4

S130. Split the constant pool into multiple sub-constant pools, and the constant pool index in the instruction is the sub-constant pool index.

The constant pool mentioned in the JavaCard virtual machine specification includes 6 reference types: class reference type, instance field reference type, static field reference type, virtual method reference type, Super method reference type, and static method reference type. These 6 reference types are unified In a constant pool, that is, the constant pool is divided into 6 sub-constant pools, each sub-constant pool corresponds to the corresponding sub-constant pool index.

In order to use a single-byte constant pool index in an instruction, the present invention proposes the concept of sub-constant pools, that is, each reference type is placed in a sub-constant pool separately, six sub-constant pools form a large constant pool, and each sub-constant pool The order of positions is not important, so that the constant pool index in each type of instruction is the index of the corresponding sub-constant pool.

S140: Encode the constant pool index operand in each instruction of the initial instruction to the opcode of the next instruction; thereby obtain the opcode of the instruction using the constant pool index through the position of the constant pool index, and obtain the opcode of the instruction using the constant pool index through the operation code Determines the type of the child constant pool.

Specifies the encoding position of the constant pool index, from which the opcode of the instruction can be determined, which further determines the type of the constant pool. Instructions such as creating instances, instance type conversions, static fields, instance fields, and method calls all include constant pool index operands by encoding the constant pool index operand into the opcode immediately following the instruction (behind or before, and the instruction-encoded operand). The position of the instruction code can be determined by the position of the constant pool index, the specific operation type of the instruction can be determined by analyzing the instruction code, and finally the type of the sub-constant pool to be accessed can be determined.

Since the constant pool is divided into multiple sub-constant pools in this embodiment, during the application installation process, there will be problems when linking the bytecode of the method. If only the index position of the constant pool of the instruction is known, it is impossible to determine which An index into a subconstant pool. If it is stipulated that the index of the sub-constant pool must be placed after the instruction code (or in front of it), the location of the instruction code can be easily determined. By analyzing the instruction code, the specific operation type of the instruction can be determined, and finally the access code can be determined. Child constant pool type. That is, in the present application, the constant pool index operands in each instruction can be uniformly encoded to the back of the specified code, and the constant pool index operands of each instruction can also be uniformly encoded to the front of the instruction code.

The following is an example of accessing the static field instruction: putfield-b rAA rBB CC must be encoded in the form of op CCAA BB, where CC is the constant pool index and must be placed after the op. The relative position of AA and BB is irrelevant.

S150. Separate the variable-length operand in each instruction in the initial instruction from the instruction code.

Specifically, the variable-length operands can be separated from the instruction code, and the variable-length operands can be placed at the end of the method (or other suitable positions), and the instruction only needs to contain a fixed-length offset, so that There is no need to consider the problem of instruction alignment, and the reading efficiency and execution efficiency of instructions are improved.

The corresponding instructions are shown in Table 5.

table 5

The data format corresponding to the packedswitch instruction is shown in Table 6.

Table 6

The data format corresponding to the sparseswitch instruction is shown in Table 7.

Table 7

S160. Obtain the static field type and initial configuration value of the static field in the initial instruction, and generate a pseudo-instruction corresponding to each static field.

In the high-level language, the class defines the static field, which sets the initialization value, and the compiler generates a special <clinit> method to handle the initialization operation of the static field. High-level languages can define static fields of array types, in which arrays can specify initial values; compilers in high-level languages generally need to generate new array instructions and instructions for assigning initial values to array members; high-level languages can define basic type static fields with initial values, Compilers of high-level languages generally need to generate instructions for assigning static fields; currently, the mechanism of JavaCard processing the <clinit> method, the code conversion tool simulates and executes the instructions in the <clinit> method, extracts the static type and the corresponding initial value and saves it. For use in subsequent conversion steps.

The present invention is designed to generate a special pseudo-instruction based on the static field type and initial configuration value of the static field. First, the type of each static field and the set initial value are recorded, and then a uniform format pseudo-instruction is generated based on the information corresponding to each static field. instruction. The pseudo-instruction refers to an instruction that does not need to be executed by the virtual machine, but when the application is installed, the installation program obtains the initialization data of the corresponding instance domain, and the virtual machine can create the static domain data area required for the execution of the application program. The corresponding pseudo-instruction can simplify the processing flow of the <clinit> method by the subsequent conversion tool, and remove the static domain component in the traditional executable program. The function of this component is to record the initialization information of all static domains in the application package.

The static domain initialization instructions are shown in Table 8.

Table 8

S170 , performing optimization processing on the instruction that reuses the register to obtain the instruction for multiplexing the register.

For example, you can operate on operands in two registers and assign the result to another register. Take the addition operation as an example: the function of the add rAA rBB rCC instruction is rAA=rBB+rCC; if the compiler can determine that the current value of an operand register will not be used in the future, if the current value of the rBB register is no longer used, use Taking the addition operation as an example, the following instructions can be generated: the function of the add rBB rCC instruction is rBB=BB+rCC; the length of the add rAA rBB rCC instruction is 4 bytes, and the length of the add rBB rCC instruction is 3 bytes. Multiplexing registers can reduce the length of bytecodes, reduce the time to read instructions when executing instructions, improve execution performance, and reduce the need for registers. The instructions for the multiplexed registers are shown in Table 9.

Table 9

instruction notation code instruction code Instruction function description add-2r rAA rBB op AA BB rAA=rAA+rBB and-2r rAA rBB op AA BB rAA=rAA&rBB

S180. Combine a group of instructions with similar functions into one instruction, and use the operation type operand in the instruction to specify the operation type of the combined instruction to obtain a corresponding compound multi-operation instruction.

After the above-mentioned instructions are obtained, a group of instructions with similar functions can be compounded and simplified to obtain corresponding compound multi-operation instructions. In devices with limited resources, such as smart cards, secure elements, etc., their applications mainly use operations of the short data type, and operations of the int data type are rarely used; the design of the instruction set generally uses only the range that can be represented by one byte ( 0 to 255), if each int operation uses a separate opcode, reducing the likelihood of subsequent instructions extending common operations. Therefore, some uncommon instructions are compounded into one instruction, and the specific operation type is specified by the operation type operand in the instruction, thereby reducing the use of instruction codes in the instruction set, and reserving usable opcodes for subsequent extended instructions. Among them, The rules for performing compound instruction reduction processing can be configured in the above-mentioned bytecode instruction set. Specifically, the instructions for compound multi-operation are shown in Table 10.

Table 10

In this embodiment, the instruction that assigns a constant to a register and an instruction that uses a register as an operand in the initial instruction can be optimized into reduced instructions, or a reduced instruction with constants can be directly generated, and the instruction accessing the current instance domain can be converted into accessing the current instance domain. Instance domain-specific instructions, encode the constant pool index operand in the instruction to the opcode next to the instruction, separate the variable-length operand in each instruction from the instruction code, generate a pseudo-instruction for static domain initialization, and reuse the register The instructions are optimized to multiplexed register instructions, which combine a group of instructions with similar functions into a single instruction. Through the above steps, the initial instruction is simplified and then the instruction is simplified, so that the length of the bytecode can be reduced, and the execution performance of the bytecode can be improved.

As shown in FIG. 2 , an instruction reduction system 100 of a bytecode instruction set, the system can be configured in a user terminal, and the system is used to execute any embodiment of the foregoing instruction reduction method of a bytecode instruction set, It includes the following devices: a first merging processing device 110, an instruction converting device 120, a constant pool splitting device 130, a constant pool index operand encoding device 140, an operand separating device 150, a pseudo-instruction generating device 160, and a second merging processing device 170 and a composite multi-operation instruction acquisition device 180 .

The first merging processing device 110 is configured to perform optimization processing on an instruction that assigns a constant to a register and an instruction that uses a register as an operand in the initial instruction to obtain a simplified instruction that directly uses a constant operand, or directly generates an operation that uses a constant. Number of reduced instructions.

The instructions for assigning constants to registers include arithmetic operation and logical operation instructions, jump instructions after comparison with literal constants, and array member access instructions.

The instruction conversion device 120 is configured to convert the instruction of the register corresponding to the this parameter of the method as the object accessing the instance domain in the initial instruction according to the preset instruction format to obtain the instance domain-specific instruction for accessing the current instance.

In a specific embodiment, the instruction conversion device 120 includes a unit: a register operand deletion unit, which is used to delete the instruction of the register corresponding to the this parameter of the method as the object of the access instance field according to the preset instruction format to delete the operand of the specified instance. , to obtain the instance domain-specific instruction for accessing the current instance; the instance-domain-specific instruction of the current instance can specify the register to be set or return the result by default.

The constant pool splitting device 130 is configured to split the constant pool into multiple sub-constant pools, and the constant pool index in the instruction is the sub-constant pool index.

The constant pool index operand encoding device 140 is used for encoding the constant pool index operand in each instruction of the initial instruction to the opcode of the next instruction; thereby obtaining the instruction using the constant pool index through the position of the constant pool index The opcode by which the type of the sub-constant pool is determined.

In a specific embodiment, the constant pool index operand encoding device 140 includes a first encoding unit or a second encoding unit.

The first encoding unit is used to uniformly encode the constant pool index operand in each instruction to the back of the specified code; the second encoding unit is used to uniformly encode the constant pool index operand in each instruction to the instruction the front of the code.

The operand separating device 150 is used for separating variable-length operands in each instruction in the initial instruction from the instruction code.

The pseudo-instruction generating device 160 is configured to obtain the static field type and initial configuration value of the static field instructions in the initial instruction, and generate a pseudo-instruction corresponding to each static field.

The second merging processing device 170 is configured to perform optimization processing on the instruction of multiplexing registers to obtain the instruction of multiplexing registers.

The compound multi-operation instruction obtaining device 180 is configured to compound a group of instructions with similar functions into one instruction, and use the operation type operand in the instruction to specify the operation type of the compounded instruction to obtain the corresponding compound multi-operation instruction.

In this embodiment, the instruction that assigns a constant to a register and an instruction that uses a register as an operand in the initial instruction can be optimized into reduced instructions, or a reduced instruction with constants can be directly generated, and the instruction accessing the current instance domain can be converted into accessing the current instance domain. Instance domain-specific instructions, encode the constant pool index operand in the instruction to the opcode next to the instruction, separate the variable-length operand in each instruction from the instruction code, generate pseudo-instructions for static domain initialization, and adjust according to configuration items The length of the instruction, which optimizes the instruction that reuses the register into the instruction that reuses the register, and combines a group of instructions with similar functions into one instruction. Through the above steps, the initial instruction is simplified and then the instruction is simplified, so that the length of the bytecode can be reduced, and the execution performance of the bytecode can be improved.

Those skilled in the art should understand that the method and system described in the present invention are not limited to the embodiments described in the specific implementation manner, and the above specific description is only for the purpose of explaining the present invention, not for limiting the present invention. Those skilled in the art can obtain other embodiments according to the technical solutions of the present invention, which also belong to the technical innovation scope of the present invention, and the protection scope of the present invention is defined by the claims and their equivalents.

Claims (8)

1. an instruction reduction method of a bytecode instruction set, is characterized in that, comprises the following steps: Optimizing the instruction that assigns a constant to a register and the instruction that uses the register as an operand in the initial instruction to obtain an instruction that directly uses a constant operand, or directly generates an instruction that uses a constant operand; Convert the instruction of the register corresponding to the this parameter of the method whose instance of the access instance domain in the initial instruction is the method according to the preset instruction format, and obtain the instance domain exclusive instruction for accessing the current instance; Split the constant pool into multiple sub-constant pools, and the constant pool index in the instruction is the sub-constant pool index; Encode the constant pool index operand in each instruction of the initial instruction to the opcode position next to the instruction; thus obtain the opcode of the instruction using the constant pool index through the position of the constant pool index, and the opcode can Type of stator constant pool; Separating the variable-length operand and the instruction code in the variable-length instruction; Obtain the static domain type and initial configuration value of the static domain, and generate a pseudo-instruction corresponding to each static domain declaration, and the pseudo-instruction can replace the traditional static domain component; Optimizing the instructions for reusing registers to obtain instructions for multiplexing registers; Combine a group of instructions with similar functions and are not commonly used into one instruction, use the operation type operand in the instruction to specify the operation type of the combined instruction, and obtain the corresponding compound multi-operation instruction. 2. the instruction reduction method of a kind of bytecode instruction set as claimed in claim 1, it is characterized in that, the described instruction that constant is assigned to register comprises arithmetic operation and logical operation instruction, and jump after the comparison of literal constant instruction, access array member instruction. 3. the instruction reduction method of a kind of bytecode instruction set as claimed in claim 1, it is characterised in that described by the instance of the instance domain visited as the instruction of the this parameter corresponding register of the method is converted according to the preset instruction format , get instance domain-specific instructions for accessing the current instance, including: Delete the operand of the specified instance according to the preset instruction format by deleting the instruction corresponding to the register corresponding to the this parameter of the method whose instance of the instance domain is the instance of the method, and obtain the instance domain-specific instruction for accessing the current instance; the instance domain-specific instruction of the current instance can be further optimized. The register to be set or the result to be returned can be specified by default. 4. The instruction reduction method of a bytecode instruction set as claimed in claim 1, wherein the constant pool index operand in each instruction with a constant pool index is encoded to the position of the opcode next to the instruction ,include: The constant pool index operand in the instruction is uniformly encoded to the back of the specified code; Or, uniformly encode the constant pool index operand in the instruction to the front of the instruction code. 5. An instruction reduction system of a bytecode instruction set, characterized in that, comprising the following devices: The first merging processing device is configured to perform optimization processing on the instruction that assigns a constant to the register and the instruction that uses the register as an operand in the initial instruction to obtain an instruction that directly uses the constant operand, or directly generates an instruction that uses the constant operand instructions; An instruction conversion device, used for converting the instruction of the register corresponding to the this parameter of the method whose instance of the access instance domain in the initial instruction is a method, according to the preset instruction format, and obtains the instance domain exclusive instruction for accessing the current instance; The constant pool splitting device is used to split the constant pool into multiple sub-constant pools. The constant pool index in the instruction is the index of the sub-constant pool, and the sub-constant pool index helps the instruction to use a shorter sub-constant pool index for encoding. Way; A constant pool index operand encoding device, for encoding the constant pool index operand in the instruction to the position of the operation code next to the instruction; thereby obtaining the operation code of the instruction using the constant pool index through the position of the constant pool index, The type of the sub-constant pool can be determined by the operation code; an operand separation device, used for separating the variable-length operand in the instruction from the instruction code; A pseudo-instruction generating device, configured to obtain the static domain type and initial configuration value of the static domain instruction, and generate pseudo-instructions corresponding to each static domain declaration, and the pseudo-instructions can replace traditional static domain components; The second merging processing device is used to optimize the instruction of the multiplexed register to obtain the instruction of the multiplexed register; The compound multi-operation instruction obtaining device is used for compounding a group of instructions with similar functions and not commonly used into one instruction, and using the operation type operand in the instruction to specify the operation type of the compounded instruction to obtain the corresponding compound multi-operation instruction. 6. the instruction reduction system of a kind of bytecode instruction set as claimed in claim 5, it is characterized in that, the described instruction that assigns constant to register comprises arithmetic operation and logical operation instruction, and jump after the comparison of literal constant instruction, access array member instruction. 7. The instruction reduction system of a bytecode instruction set according to claim 5, wherein the instruction conversion device comprises a unit: The register operand deletion unit is used to delete the instruction of the register corresponding to the this parameter of the method that accesses the instance field of the method according to the preset instruction format to delete the operand of the specified instance, and obtain the instance field-specific instruction to access the current instance; the instance of the current instance Domain-specific instructions can be further optimized to specify registers to be set or return results by default. 8. The instruction reduction system of a bytecode instruction set according to claim 5, wherein the constant pool index operand encoding device comprises a first encoding unit or a second encoding unit: The first encoding unit is used to uniformly encode the constant pool index operand in each instruction to the back of the specified code; The second encoding unit is used for uniformly encoding the constant pool index operand in each instruction to the front of the instruction code.

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