CN114400876A - Drive control circuit and drive control method - Google Patents

Abstract

The invention provides a drive control circuit and a drive control method, wherein the drive control circuit comprises a PMOS (P-channel metal oxide semiconductor) switching tube and a discharge regulation module, wherein the grid electrode of the PMOS switching tube is connected with a PWM (pulse-width modulation) signal, the source electrode of the PMOS switching tube is connected with a power supply voltage, and the drain electrode of the PMOS switching tube is connected with the grid electrode of an NMOS (N-channel metal oxide semiconductor) power tube; the discharging adjusting module is connected between the grid of the NMOS power tube and the ground, is controlled by the PWM signal, and is used for carrying out stage discharging on the grid parasitic capacitance of the NMOS power tube based on different discharging paths along with the change of the grid voltage of the NMOS power tube when the PWM signal is changed from a low level to a high level. The drive control circuit and the drive control method provided by the invention are used for improving the problems of electromagnetic interference and overvoltage breakdown in the prior art.

Description

Drive control circuit and drive control method

Technical Field

The present invention relates to the field of integrated circuit design and application, and in particular, to a driving control circuit and a driving control method.

Background

The NMOS power transistor has high reliability and high performance-to-price ratio, and is often applied to various switching power supply circuits in a large amount, and when the NMOS power transistor works, if the drain voltage of the NMOS power transistor changes rapidly, electromagnetic interference (EMI) may be generated.

Fig. 1 is a conventional NMOS power transistor driving control circuit, which adopts a totem-pole structure, wherein a PMOS switching transistor PM10 is an upper driving transistor, an NMOS switching transistor NM11 is a lower driving transistor, specifically, a source of the PMOS switching transistor PM10 is connected to a power supply voltage VDD, a gate is connected to a PWM signal, and a drain is connected to a gate of the NMOS power transistor NM 10; the grid electrode of the NMOS switch tube NM11 is connected with the PWM signal, the drain electrode is connected with the grid electrode of the NMOS power tube NM10, and the source electrode is grounded.

The gate parasitic capacitance of the NMOS power transistor NM10 includes a parasitic capacitance Cgd between the gate and the drain thereof and a parasitic capacitance Cgs between the gate and the source thereof. When the PWM signal changes from high level to low level, the PMOS switch transistor PM10 changes from off state to on state, which charges the gate parasitic capacitance of the NMOS power transistor NM10 with the maximum current, so that the NMOS power transistor NM10 is turned on; when the PWM signal changes from low level to high level, the NMOS switch NM11 changes from off state to on state, which discharges the gate parasitic capacitance of the NMOS power transistor NM10 with the maximum current, so that the NMOS power transistor NM10 is turned off.

As shown in fig. 2, after the NMOS switch tube NM11 is turned on, the NMOS switch tube NM11 discharges the gate parasitic capacitance of the NMOS power tube NM10, so that the gate voltage of the NMOS power tube NM10 passes through four variation stages, and then the NMOS power tube NM10 is turned off, where the four variation stages are respectively: a first variation phase Ta0-Ta1, a second variation phase Ta1-Ta2, a third variation phase Ta2-Ta3, a fourth variation phase Ta3-Ta4, while the first variation phase Ta0-Ta1, the second variation phase Ta3-Ta4Duration t of the variation phases Ta1-Ta2 and of the third variation phases Ta2-Ta3_Ta0-Ta1、t_Ta1-Ta2、t_Ta2-Ta3Respectively as follows:

wherein R is_NM11Is the on-resistance g of the NMOS switch tube NM11 when it is turned on_NM10For transconductance of the NMOS power tube NM10 in the miller plateau stage, Vthn10 is a threshold voltage of the NMOS power tube NM10, Ids-max is a maximum value of a drain current of the NMOS power tube NM10, and Vsw is a drain voltage of the NMOS power tube NM10 before being turned off.

Since the shorter the time that the gate voltage of the NMOS power transistor NM10 is in the miller plateau stage, the greater the rising rate dv/dt of the drain voltage thereof is, the stronger the electromagnetic interference signal generated by the NMOS power transistor NM10 is, the greater the overshoot amplitude is, and the greater the overshoot amplitude may cause the NMOS power transistor to have the risk of overvoltage breakdown. Therefore, in order to improve the above-mentioned problems of electromagnetic interference and over-voltage breakdown of the NMOS power transistor driving control circuit, a method of increasing the on-resistance of the NMOS switch transistor is generally adopted. However, as can be seen from the above formula, if the on-resistance of the NMOS switch tube is increased, the durations t of the first variation phase Ta0-Ta1 and the third variation phase Ta2-Ta3 are increased_Ta0-Ta1、t_Ta2-Ta3Will also increase, and t_Ta0-Ta1And t_Ta2-Ta3The increase of the NMOS power tube increases the conduction loss and the heat productivity of the NMOS power tube, and further causes the thermal breakdown of the NMOS power tube, so that when the NMOS power tube is used for driving a control circuit, an NMOS switch with a proper conduction resistance value is difficult to selectTherefore, the NMOS power tube driving control circuit has electromagnetic interference and overvoltage breakdown problems, and the performance of the system is poor.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides a driving control circuit and a driving control method for improving the problems of electromagnetic interference and over-voltage breakdown in the prior art.

To achieve the above and other related objects, the present invention provides a driving control circuit for driving and controlling an NMOS power transistor having a gate parasitic capacitance, the driving control circuit comprising: a PMOS switch tube and a discharge regulating module, wherein,

the grid electrode of the PMOS switching tube is connected with a PWM signal, the source electrode of the PMOS switching tube is connected with power supply voltage, and the drain electrode of the PMOS switching tube is connected with the grid electrode of the NMOS power tube;

the discharging adjusting module is connected between the grid of the NMOS power tube and the ground, is controlled by the PWM signal, and is used for carrying out stage discharging on the grid parasitic capacitance of the NMOS power tube based on different discharging paths along with the change of the grid voltage of the NMOS power tube when the PWM signal is changed from a low level to a high level.

Optionally, the discharge regulation module comprises: a first discharge regulating unit, a second discharge regulating unit and a third discharge regulating unit which are connected between the grid of the NMOS power tube and the ground and controlled by the PWM signal,

the first discharge adjusting unit is used for forming a discharge path from the grid parasitic capacitance of the NMOS power tube to the ground in a first change stage of the grid voltage of the NMOS power tube;

the second discharge adjusting unit is used for forming a discharge path from the grid parasitic capacitance of the NMOS power tube to the ground in a first change stage to a sixth change stage of the grid voltage of the NMOS power tube;

the third discharge adjusting unit is used for forming a discharge path from the grid parasitic capacitance of the NMOS power tube to the ground in a fifth change stage and a sixth change stage of the grid voltage of the NMOS power tube.

Optionally, the first discharge adjustment unit includes: a first NMOS transistor and a driving portion, wherein,

the grid electrode of the first NMOS tube is connected with the output end of the driving part, the drain electrode of the first NMOS tube is connected with the grid electrode of the NMOS power tube, and the source electrode of the first NMOS tube is grounded;

the drive part is connected between the grid electrode of the NMOS power tube and the ground, is controlled by the PWM signal, and is used for generating and outputting a drive signal in a first change stage of the grid electrode voltage of the NMOS power tube so as to control the first NMOS tube to be conducted.

Optionally, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a first resistor; the grid electrode of the second NMOS tube is connected to the PWM signal, the drain electrode of the second NMOS tube is connected with the drain electrode and the grid electrode of the first PMOS tube, and the source electrode of the second NMOS tube is grounded; the source electrode of the first PMOS tube is connected with the drain electrode and the grid electrode of the second PMOS tube; the source electrode of the second PMOS tube is connected with the grid electrode of the NMOS power tube, and the grid electrode of the second PMOS tube is connected with the grid electrode of the third PMOS tube; and the source electrode of the third PMOS tube is connected with the grid electrode of the NMOS power tube, and the drain electrode of the third PMOS tube is grounded through the first resistor and is used as the output end of the driving part.

Optionally, the second discharge regulation unit includes: a third NMOS transistor and a current limiting resistor; and the grid electrode of the third NMOS tube is connected with the PWM signal, the drain electrode of the third NMOS tube is connected with the grid electrode of the NMOS power tube, and the source electrode of the third NMOS tube is grounded through the current-limiting resistor.

Optionally, the third discharge regulation unit includes: a control portion and a discharge portion, wherein,

the control part is connected between a power supply voltage and the ground, is controlled by the grid voltage of the NMOS power tube and is used for generating and outputting an effective control signal in a fifth change stage and a sixth change stage of the grid voltage of the NMOS power tube;

the discharge part is connected between the grid of the NMOS power tube and the ground, is controlled by the PWM signal and the control signal, and is used for forming a discharge path from the grid parasitic capacitance of the NMOS power tube to the ground when the control signal is effective.

Optionally, the control section includes: the fourth NMOS tube, the first triode and the second resistor; the grid electrode of the fourth NMOS tube is connected with the grid electrode of the NMOS power tube, the drain electrode of the fourth NMOS tube is connected with the power supply voltage through the second resistor and outputs a control signal, and the source electrode of the fourth NMOS tube is connected with the base electrode of the first triode; and the collector electrode of the first triode is connected with the drain electrode of the fourth NMOS tube, and the emitter electrode of the first triode is grounded.

Optionally, the discharge portion comprises: a fifth NMOS transistor and a sixth NMOS transistor; the grid electrode of the fifth NMOS tube is connected to the control signal, the drain electrode of the fifth NMOS tube is connected with the grid electrode of the NMOS power tube, and the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube; and the grid electrode of the sixth NMOS tube is connected to the PWM signal, and the source electrode of the sixth NMOS tube is grounded.

Optionally, when the second discharge unit includes the third NMOS transistor and a current-limiting resistor, a sum of an on-resistance of the fifth NMOS transistor and an on-resistance of the sixth NMOS transistor is smaller than a sum of an on-resistance of the third NMOS transistor and a resistance of the current-limiting resistor.

The invention also provides a drive control method for driving and controlling the NMOS power tube with the grid parasitic capacitance, which comprises the following steps:

when the PWM signal is changed from high level to low level, the grid parasitic capacitance of the NMOS power tube is charged to power voltage, and the NMOS power tube is changed from off state to on state;

when the PWM signal is changed from a low level to a high level, the grid parasitic capacitance of the NMOS power tube is discharged in stages based on different discharging paths along with the change of the grid voltage of the NMOS power tube, and the NMOS power tube is changed from a conducting state to a cutting-off state.

Optionally, the step of discharging the gate parasitic capacitance of the NMOS power transistor based on three different discharge paths specifically includes:

discharging the grid parasitic capacitance of the NMOS power tube based on a first discharging path and a second discharging path in a first change stage of the grid voltage of the NMOS power tube;

discharging the grid parasitic capacitance of the NMOS power tube based on a second discharge path at a second change stage, a third change stage and a fourth change stage of the grid voltage of the NMOS power tube;

and discharging the grid parasitic capacitance of the NMOS power tube based on a second discharge path and a third discharge path in a fifth change stage and a sixth change stage of the grid voltage of the NMOS power tube.

As described above, the drive control circuit and the drive control method according to the present invention have the following advantageous effects: the drive control circuit can improve the problems of overvoltage breakdown of drain voltage and electromagnetic interference of the NMOS power tube by prolonging the duration time of a Miller platform stage in the process of turning off the NMOS power tube; meanwhile, the falling time of the grid voltage in the turn-off process of the NMOS power tube can be reduced, so that the conduction loss is reduced.

Drawings

Fig. 1 is a schematic diagram of a conventional NMOS power transistor driving control circuit.

Fig. 2 is a schematic diagram showing the variations of the drain current, the drain voltage and the gate voltage waveform in the discharge process of the conventional NMOS power transistor.

FIG. 3 is a schematic diagram of a driving control circuit according to the present invention.

FIG. 4 is a schematic diagram showing the variations of the drain current, the drain voltage and the gate voltage waveforms during the discharging process of the NMOS power transistor according to the present invention.

Description of the element reference numerals

1 discharge regulation module

11 first discharge regulating unit

111 drive section

12 second discharge regulating unit

13 third discharge regulating unit

131 control part

132 discharge part

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 3-4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 3, the present embodiment provides a driving control circuit for driving and controlling an NMOS power transistor NM20 having a gate parasitic capacitance, the driving control circuit including: a PMOS switching tube PM20 and a discharge regulation module 1.

The gate parasitic capacitance of the NMOS power transistor NM20 includes a parasitic capacitance Cgd between the gate and the drain of the NMOS power transistor NM20 and a parasitic capacitance Cgs between the gate and the source of the NMOS power transistor NM20, and the driving control circuit of the present embodiment charges and discharges the gate parasitic capacitance of the NMOS power transistor NM20, so that the NMOS power transistor NM20 is turned on and off.

The grid electrode of the PMOS switching tube PM20 is connected with a PWM signal, the source electrode is connected with a power supply voltage VDD, and the drain electrode is connected with the grid electrode of the NMOS power tube NM 20. In this embodiment, when the PWM signal changes from high level to low level, the PMOS switch transistor PM20 is turned on, and charges the gate parasitic capacitance of the NMOS power transistor NM20 to the power supply voltage VDD, so that the NMOS power transistor NM20 is turned on.

The discharge regulation module 1 is connected between the gate of the NMOS power tube NM20 and the ground, is controlled by the PWM signal, and is configured to perform a stepwise discharge on the gate parasitic capacitance of the NMOS power tube NM20 based on different discharge paths, following the change of the gate voltage of the NMOS power tube NM20 when the PWM signal changes from a low level to a high level, so that the NMOS power tube NM20 is turned off.

Specifically, the discharge regulation module 1 includes: the first discharge regulation unit 11, the second discharge regulation unit 12, and the third discharge regulation unit 13 are connected between the gate of the NMOS power transistor NM20 and ground, and controlled by the PWM signal.

The first discharge regulation unit 11 is configured to regulate a gate voltage V of the NMOS power transistor NM20_GATEForming a discharge path from the gate parasitic capacitance of the NMOS power transistor NM20 to ground.

More specifically, the first discharge regulation unit includes a first NMOS transistor NM21 and a driving part 111, wherein a gate of the first NMOS transistor NM21 is connected to an output terminal of the driving part 111, a drain is connected to a gate of the NMOS power transistor NM20, and a source is grounded; the driving part 111 is connected between the gate of the NMOS power transistor NM20 and ground, and is controlled by the PWM signal to generate and output a driving signal in a first variation phase of the gate voltage of the NMOS power transistor NM20 to control the first NMOS transistor NM21 to be turned on.

As an example, the driving part 111 includes a second NMOS transistor NM22, a first PMOS transistor PM21, a second PMOS transistor PM22, a third PMOS transistor PM23, and a first resistor R21; the grid electrode of the second NMOS tube NM22 is connected with the PWM signal, the drain electrode of the second NMOS tube NM22 is connected with the drain electrode and the grid electrode of the first PMOS tube PM11, and the source electrode of the second NMOS tube NM22 is grounded; the source electrode of the first PMOS transistor PM21 is connected with the drain electrode and the gate electrode of the second PMOS transistor PM 22; the source electrode of the second PMOS transistor PM22 is connected with the grid electrode of the NMOS power transistor NM20, and the grid electrode of the second PMOS transistor PM22 is connected with the grid electrode of the third PMOS transistor PM 23; the source of the third PMOS transistor is connected to the gate of the NMOS power transistor NM20, and the drain is grounded through the first resistor R21 and serves as the output terminal of the driving part 111.

In this embodiment, when the PWM signal changes from low level to high level, the second NMOS transistor NM22 is turned on, and the gate of the NMOS power transistor NM20 is electrically connectedPressure V_GATEWhen the voltage is > (Vthp1+ Vthp2), the first PMOS transistor PM21 and the second PMOS transistor PM22 are connected, the second PMOS transistor PM22 generates a drain current, and the second PMOS transistor PM22 and the third PMOS transistor PM23 form a current mirror, and the drain current of the third PMOS transistor PM23 and the drain current of the second PMOS transistor PM22 form a proportional relation, so the third PMOS transistor PM23 generates a drain current. The drain current of the third PMOS transistor PM23 passes through the first resistor R21, so that the gate voltage of the first NMOS transistor NM21 is higher than the threshold voltage thereof (i.e. the third PMOS transistor PM23 generates the active driving signal), and the first NMOS transistor NM21 is turned on, thereby discharging the gate parasitic capacitance of the NMOS power transistor NM20 through the first NMOS transistor NM 21. The discharge is continued until the gate voltage V of the NMOS power tube NM20_GATE< (Vthp1+ Vthp2), at this time, the first PMOS transistor PM21 and the second PMOS transistor PM22 are turned off, the drain current of the third PMOS transistor PM23 is reduced to 0, the gate voltage of the first NMOS transistor NM21 is dropped to 0 (i.e. the driving signal generated by the third PMOS transistor PM23 is inactive), and the first NMOS transistor NM21 is turned off. Since only the gate voltage V of the NMOS power tube NM20 is detected_GATEIn the first variation phase, the gate voltage V of the NMOS power transistor NM20_GATE> (Vthp1+ Vthp2), therefore, the first NMOS transistor NM21 is only at the gate voltage V of the NMOS power transistor NM20_GATEDischarges the gate parasitic capacitance of the NMOS power transistor NM 20. Wherein Vthp1 is a threshold voltage of the first PMOS transistor PM21, Vthp2 is a threshold voltage of the second PMOS transistor, optionally, the threshold voltages of the first PMOS transistor PM21 and the second PMOS transistor PM22 are the same and are both Vthp, and at this time, V is_GATE> (Vthp1+ Vthp2) can be expressed as V_GATE＞2*Vthp，V_GATE< (Vthp1+ Vthp2) may be expressed as V_GATE< 2 × Vthp. It should be noted that the gate voltage V of the NMOS power transistor NM20_GATEIn the first variation stage, besides the first NMOS transistor NM21 discharging the gate parasitic capacitance of the NMOS power transistor NM20, the branch of the second NMOS transistor NM22 also discharges the gate parasitic capacitance of the NMOS power transistor NM20, and the second NMOS transistor NM is used as the gate parasitic capacitance of the NMOS power transistor NM20The branch 22 includes the first PMOS transistor PM21 and the second PMOS transistor PM22, so that the discharge current of the branch is small, and therefore, the drain current of the second NMOS transistor NM22 is negligible compared with the drain current of the first NMOS transistor NM 21.

The second discharge regulating unit 12 is used for regulating the gate voltage V of the NMOS power tube NM20_GATEThe discharge path from the gate parasitic capacitance of the NMOS power transistor NM20 to the ground is formed in the first to sixth variation stages.

More specifically, the second discharge regulation unit 12 includes: a third NMOS transistor NM23 and a current limiting resistor Rc; the grid electrode of the third NMOS transistor NM23 is connected to the PWM signal, the drain electrode is connected to the grid electrode of the NMOS power transistor NM20, and the source electrode is grounded through the current limiting resistor Rc.

In this embodiment, when the PWM signal changes from low level to high level, the third NMOS transistor NM23 is turned on, and discharges the gate parasitic capacitance of the NMOS power transistor NM 20; due to the gate voltage V of the NMOS power tube NM20_GATEThe PWM signal is always high in the first to sixth variation stages, and therefore, the third NMOS transistor NM23 has a gate voltage V at the NMOS power transistor NM20_GATETurn on and discharge the gate parasitic capacitance of the NMOS power transistor NM20 in all of the first to sixth variation stages. In addition, since the source of the third NMOS transistor NM23 is connected to a current limiting resistor Rc, the drain current of the third NMOS transistor NM23 is limited by the current limiting resistor Rc, and therefore, the gate voltage V of the NMOS power transistor NM20 is set_GATEIn the first variation stage of (3), when the on-resistance of the first NMOS transistor NM21 is much smaller than the on-resistance of the third NMOS transistor, the drain current of the third NMOS transistor NM23 is negligible compared to the drain current of the first NMOS transistor NM 21.

The third discharge regulation unit 13 is used for regulating the gate voltage V of the NMOS power transistor NM20_GATEThe fifth and sixth variation stages of the NMOS power transistor NM20, a discharge path from the gate parasitic capacitance of the NMOS power transistor NM20 to ground is formed.

More particularly, theThe third discharge adjustment unit 13 includes: a control portion 131 and a discharge portion 132, wherein the control portion 131 is connected between a power voltage VDD and ground and controlled by a gate voltage V of the NMOS power transistor NM20_GATEFor applying a gate voltage V to the NMOS power transistor NM20_GATEThe fifth change stage and the sixth change stage of the control circuit, and generating and outputting effective control signals; the discharging part 132 is connected between the gate of the NMOS power transistor NM20 and ground, and is controlled by the PWM signal and the control signal, so as to form a discharging path from the gate parasitic capacitance of the NMOS power transistor NM20 to ground when the control signal is active.

As an example, the control portion 131 includes: a fourth NMOS transistor NM24, a first transistor Q21, and a second resistor R22; the gate of the fourth NMOS transistor NM24 is connected to the gate of the NMOS power transistor NM20, the drain is connected to the power voltage VDD through the second resistor R22 and outputs a control signal, and the source is connected to the base of the first transistor Q21; the collector of the first triode Q21 is connected to the drain of the fourth NMOS transistor NM24, and the emitter is grounded. The discharge portion 132 includes: a fifth NMOS transistor NM25 and a sixth NMOS transistor NM 26; the gate of the NM25 of the fifth NMOS transistor is connected to the control signal, the drain is connected to the gate of the NMOS power transistor NM20, and the source is connected to the drain of the sixth NMOS transistor NM 26; the gate of the sixth NMOS transistor NM26 is connected to the PWM signal, and the source of the sixth NMOS transistor NM26 is grounded.

In this embodiment, when the gate voltage V of the NMOS power transistor NM20_GATEWhen > (Vthn4+ Vbe1), the fourth NMOS tube NM24 and the first transistor Q21 are turned on, where Vthn4 is the threshold voltage of the fourth NMOS tube NM24, and Vbe1 is the voltage difference between the base and the emitter of the first transistor Q21. When the fourth NMOS transistor NM24 and the first transistor Q21 are turned on, the gate voltage of the fifth NMOS transistor NM25 is pulled down to ground (the control signal generated by the fourth NMOS transistor NM24 is inactive), so that the fifth NMOS transistor NM25 is turned off, and the third discharge unit 13 cannot form a discharge path; when the gate voltage V of the NMOS power transistor NM20_GATEWhen < (Vthn4+ Vbe1), the fourth NMOS tubeNM24 and the transistor Q21 are both turned off, the gate voltage of the fifth NMOS transistor NM25 is pulled up to VDD by the second resistor R22 (the fourth NMOS transistor NM24 generates the active control signal), the fifth NMOS transistor NM25 is turned on, at this time, if the PWM signal is high level, the sixth NMOS transistor NM26 is turned on, and the fifth NMOS transistor NM25 and the sixth NMOS transistor NM26 discharge the gate parasitic capacitance of the power transistor NM 20. Due to the gate voltage V of the NMOS power tube NM20_GATEThe control part 131 generates the active control signal during the fifth and sixth variation phases, so that the fifth and sixth NMOS transistors generate the gate voltage V at the NMOS power transistor NM20_GATEThe fifth and sixth variation stages of (a) discharge the gate capacitance of the NMOS power transistor NM 20.

Further, when the second discharge unit 12 includes the third NMOS tube NM23 and a current limiting resistor, a sum of an on-resistance of the fifth NMOS tube NM25 and an on-resistance of the sixth NMOS tube NM26 is smaller than a sum of an on-resistance of the third NMOS tube NM23 and a resistance of the current limiting resistor Rc. In this embodiment, the on-resistances of the fifth NMOS transistor NM25 and the sixth NMOS transistor NM26 are designed to be very small, so that the sum of the on-resistances of the fifth NMOS transistor NM25 and the sixth NMOS transistor NM26 is much smaller than the sum of the resistances of the third NMOS transistor NM23 and the current limiting resistor Rc, and therefore, the drain current flowing through the third NMOS transistor NM23 is negligible compared with the drain currents flowing through the fifth NMOS transistor NM25 and the sixth NMOS transistor NM 26.

Accordingly, the present embodiment also provides a driving control method for driving and controlling an NMOS power transistor NM20 having a gate parasitic capacitance, the driving control method including:

1) when the PWM signal changes from high level to low level, the gate parasitic capacitance of the NMOS power transistor NM20 is charged to the power supply voltage VDD, and the NMOS power transistor NM20 changes from off state to on state.

In this embodiment, the gate parasitic capacitance of the NMOS power transistor NM20 is charged and discharged by using the above driving control circuit, and when the PWM signal changes from a high level to a low level, the PMOS switch transistor PM20 is turned on, so that the gate parasitic capacitance of the NMOS power transistor NM20 is charged to the power supply voltage VDD, and the NMOS power transistor NM20 is turned on.

2) When the PWM signal changes from low level to high level, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged in stages based on different discharge paths following the change of the gate voltage of the NMOS power transistor NM20, and the NMOS power transistor NM20 changes from on state to off state.

Specifically, the gate parasitic capacitance of the NMOS power tube NM20 is discharged in stages based on three different discharge paths (a first discharge path, a second discharge path, and a third discharge path) (as shown in fig. 4), specifically:

21) at the gate voltage V of the NMOS power tube NM20_GATEThe gate parasitic capacitance of the NMOS power tube is discharged based on the first discharge path and the second discharge path.

At the gate voltage V of the NMOS power tube NM20_GATEThe first change stage Tb 0-Tb 1, the gate voltage V of the NMOS power transistor NM20_GATEFrom VDD to (VDD-2 × Vthp), where Vthp is the threshold voltage of the first and second PMOS transistors PM21 and PM 22. In the first variation phase, the gate voltage V of the NMOS power transistor NM20 is applied_GATE>2 Vthp, and V_GATE>Vthn3，V_GATE>(Vthn4+ Vbe1), wherein Vthn3 is a threshold voltage of the third NMOS NM23, Vthn4 is a threshold voltage of the fourth NMOS NM24, and Vbe1 is a voltage difference between a base and an emitter of the first transistor Q21, so that the first discharge path formed by the first discharge adjustment unit 11 and the second discharge path formed by the second discharge adjustment unit 12 discharge the gate parasitic capacitance of the NMOS power tube NM20, that is, the parasitic capacitance of the NMOS power tube NM20 is discharged through the branch where the first NMOS NM21 is located, the branch where the second NMOS NM22 is located, and the branch where the third NMOS NM23 is located. Since the drain current of the third NMOS transistor NM23 is negligible compared to the drain current of the first NMOS transistor NM 21; the second NMOSThe drain current of the transistor NM22 is also negligible compared to the drain current of the first NMOS transistor, and therefore, it is equivalent to discharging the parasitic capacitance of the NMOS power transistor NM20 only through the branch of the first NMOS transistor NM 21. In this case, the duration t of the first variation phases Tb0 to Tb1_Tb0-Tb1The estimation can be done by the following equation:

wherein R is_NM21The on-resistance of the first NMOS transistor NM21, Vthp is the threshold voltage of the first PMOS transistor PM21 and the second PMOS transistor PM22, Cgs is the parasitic capacitance between the gate and the source of the NMOS power transistor NM20, Cgd is the parasitic capacitance between the gate and the drain of the NMOS power transistor NM20, and VDD is the power supply voltage value.

22) At the gate voltage V of the NMOS power tube NM20_GATEBased on a second discharge path, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged.

At the gate voltage V of the NMOS power tube NM20_GATEThe second change stage Tb 1-Tb 2, the gate voltage V of the NMOS power transistor NM20_GATEFrom (VDD-2 × Vthp) down to the miller plateau voltage Vmiller. In the second variation phase, the gate voltage V of the NMOS power transistor NM20_GATE< 2 × Vthp, and V_GATE> (Vthn4+ Vbe1), where Vthp is the threshold voltage of the first PMOS transistor PM21 and the second PMOS transistor PM22, Vthn4 is the threshold voltage of the fourth NMOS transistor NM24, and Vbe1 is the voltage difference between the base and the emitter of the first transistor Q21, so that the second discharge path formed by the second discharge adjustment unit 12 discharges the gate parasitic capacitance of the NMOS power transistor NM20, that is, the gate parasitic capacitance of the NMOS power transistor NM20 through the branch where the third NMOS transistor NM23 is located, and the discharge current is determined by the on-resistance of the third NMOS transistor NM23 and the resistance value of the current limiting resistor Rc. The duration t of the second phase of change Tb 1-Tb 2_Tb1-Tb2Can be obtained byThe formula estimates:

wherein R is_NM23Vthp is the threshold voltage of the first PMOS transistor PM21 and the second PMOS transistor PM22, R is the on-resistance of the third NMOS transistor NM23_cFor the resistance value of the current-limiting resistor, Cgs is a parasitic capacitance value between the gate and the source of the NMOS power tube NM20, Cgd is a parasitic capacitance value between the gate and the drain of the NMOS power tube NM20, VDD is the power supply voltage value, and Vmiller is the miller plateau voltage value.

23) At the gate voltage V of the NMOS power tube NM20_GATEBased on the second discharge path, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged.

The NMOS power tube NM20 grid voltage V_GATEThe third variation stages Tb 2-Tb 3 correspond to the Miller plateau stage, in which the gate voltage V of the NMOS power transistor NM20_GATEThe drain current Ids of the NMOS power transistor NM20 is substantially constant, and the drain voltage Vsw thereof rises from 0 to the maximum value Vsw-max. In the miller plateau stage, the formed discharge path is identical to the second variation stage, that is, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged through the second discharge path formed by the second discharge adjustment unit 12, that is, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged through the branch where the third NMOS transistor NM23 is located. The duration t of the third phase of change Tb 2-Tb 3_Tb2-Tb3The estimation can be done by the following equation:

wherein R is_NM23Is the on-resistance value, R, of the third NMOS transistor NM23_cIs the resistance value of the current limiting resistor, g_NM20Is the NMOS power tubeThe transconductance value of NM20 in miller plateau stage, Cgd is the parasitic capacitance between the gate and drain of the NMOS power transistor NM20, V_SWIs the drain voltage value, I, of the NMOS power tube NM20 before being turned off_{ds_max}Is the maximum current value, V, of the drain electrode of the NMOS power tube NM20_millerIs the value of the Miller plateau voltage, V_thn20Is the threshold voltage of the NMOS power transistor NM 20.

24) At the gate voltage V of the NMOS power tube NM20_GATEThe gate parasitic capacitance of the NMOS power tube is discharged based on the second discharge path.

At the gate voltage V of the NMOS power tube NM20_GATEThe fourth variation stage Tb 3-Tb 4, the gate voltage V of the NMOS power transistor NM20_GATEAnd when the Miller platform voltage Vmieler drops to (Vthn4+ Vbe1), the drain current Ids of the NMOS power tube NM20 drops from the maximum current Ids-max, wherein Vthn4 is the threshold voltage of the fourth NMOS tube NM24, and Vbe1 is the voltage difference between the base and the emitter of the first triode Q21. In the fourth variation phase, the gate voltage V of the NMOS power transistor NM20_GATE> (Vthn4+ Vbe1), and V_GATEVthn3, where Vthn3 is the threshold voltage of the third NMOS transistor NM23, and in this phase, the formed discharge path is consistent with the second variation phase, that is, the second discharge path formed by the second adjusting unit 12 discharges the gate parasitic capacitance of the NMOS power transistor NM20, that is, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged through the branch where the third NMOS transistor NM23 is located. The duration t of the fourth phase of variation Tb 3-Tb 4_Tb3-Tb4The estimation can be done by the following equation:

wherein R is_NM23Is the on-resistance value, R, of the third NMOS transistor NM23_cCgs is a parasitic capacitance value between the gate and the source of the NMOS power transistor NM20, Cgd is a resistance value of the current limiting resistor, and NM20 parasitic capacitance value between gate and drain, V_millerVthn4 is the threshold voltage of the fourth NMOS transistor NM24, V_be1Is the voltage difference between the base and emitter of the transistor Q21.

25) At the gate voltage V of the NMOS power tube NM20_GATEThe gate parasitic capacitance of the NMOS power transistor NM20 is discharged based on the second and third discharge paths.

At the gate voltage V of the NMOS power tube NM20_GATEThe fifth variation stage Tb 4-Tb 5, the gate voltage V of the NMOS power transistor NM20_GATEFrom (Vthn4+ Vbe1), the voltage drops to a threshold voltage Vthn20 of the NMOS power tube NM20, and a drain current Ids of the NMOS power tube NM20 drops to 0, where Vthn20 is the threshold voltage of the NMOS power tube NM20, Vthn4 is the threshold voltage of the fourth NMOS tube NM24, and Vbe1 is the voltage between the base and the emitter of the first triode Q21. In the fifth variation phase, the gate voltage V of the NMOS power transistor NM20 is applied_GATE> Vthn20, and V_GATE＞Vthn3，V_GATE< (Vthn4+ Vbe1), where Vthn3 is the threshold voltage of the third NMOS tube NM23, and thus the gate parasitic capacitance of the NMOS power tube NM20 is discharged by the second discharge path formed by the second discharge adjustment unit 12 and the third discharge path formed by the third discharge adjustment unit 13, that is, the gate parasitic capacitance of the NMOS power tube NM20 is discharged by the branch where the third NMOS tube NM23 is located and the branch where the fifth NMOS tube NM25 is located. Since the source of the third NMOS transistor NM23 is connected to the current-limiting resistor Rc to limit the drain current flowing through the third NMOS transistor NM23, and the sum of the on-resistance of the third NMOS transistor NM23 and the resistance of the current-limiting resistor Rc is much smaller than the sum of the on-resistance of the fifth NMOS transistor NM25 and the on-resistance of the sixth NMOS transistor NM26, the drain current flowing through the third NMOS transistor NM23 is negligible compared with the current flowing through the fifth NMOS transistor NM25 and the sixth NMOS transistor NM26, and therefore, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged only through the branch where the fifth NMOS transistor NM25 is located. At this time, the process of the present invention,the duration t of the fifth phases of variation Tb 4-Tb 5_Tb4-Tb5The estimation can be done by the following equation:

wherein R is_NM25Is the on-resistance, R, of the fifth NMOS transistor NM25_NM26Cgs is a parasitic capacitance value between the gate and the source of the NMOS power transistor NM20, Cgd is a parasitic capacitance value between the gate and the drain of the NMOS power transistor NM20, Vthn4 is a threshold voltage of the fourth NMOS transistor NM24, and V is an on-resistance of the sixth NMOS transistor NM26_be1Is the voltage difference between the base and emitter of the transistor Q21, V_thn20Is the threshold voltage value of the NMOS power transistor NM 20.

26) At the gate voltage V of the NMOS power tube NM20_GATEThe gate parasitic capacitance of the NMOS power transistor NM20 is discharged based on the second and third discharge paths.

At the gate voltage V of the NMOS power tube NM20_GATETb 5-Tb 6, the gate voltage V of the NMOS power transistor NM20_GATE> Vthn3, and V_GATE< (Vthn4+ Vbe1), wherein Vthn3 is the threshold voltage of the third NMOS transistor NM23, Vthn4 is the threshold voltage of the fourth NMOS transistor NM24, and Vbe1 is the voltage difference between the base and the emitter of the first transistor Q21. The third NMOS transistor NM23, the fifth NMOS transistor NM25 and the sixth NMOS transistor NM26 are still turned on, and the second discharge path and the third discharge path formed by the second discharge regulation unit 12 and the third discharge regulation unit 13 discharge the gate parasitic capacitance of the NMOS power transistor NM 20. The drain current Ids of the NMOS power tube NM20 is kept at 0, and the gate voltage V thereof_GATEFrom the threshold voltage Vthn20 to 0. Due to the gate voltage V of the NMOS power tube NM20_GATEGradually reducing to 0, the discharge current also gradually reducing to 0, the theoretical calculation time of Tb 5-Tb 6 stage is infinite, but the NMOS power tube NM20 is turned off at this stage, and no power loss is generated, thereforeNo further calculations are made.

In the driving control circuit and the driving control method of the present embodiment, the duration t of the miller plateau phase, that is, the third variation phase, can be increased by increasing the resistance of the current limiting resistor Rc_Tb2-Tb3Therefore, the voltage rising rate dv/dt of the drain electrode of the NMOS power tube NM20 is reduced, and the purposes of improving electromagnetic interference and overshoot breakdown are achieved; furthermore, the on-resistances of the first, fifth, and sixth NMOS transistors NM21, NM25, and NM26 may be reduced to reduce the durations of the first and fifth variation stages Tb0 to Tb1 and Tb4 to Tb5, thereby reducing the on-loss and heat generation amount of the NMOS power transistor NM 20.

Moreover, since the threshold voltages of different types of MOS transistors are usually different, the appropriate first PMOS transistor PM21 and second PMOS transistor PM22 can be selected according to the threshold voltages of different types of PMOS transistors, so that (VDD-2 × Vthp-Vmiller) is smaller, thereby reducing the duration t of the second variation phases Tb1 to Tb2_Tb1-Tb2(ii) a An appropriate fourth NMOS transistor NM24 may be selected according to the threshold voltage of different types of NMOS transistors, such that (Vmller-Vthn 4-V)_Q21) Less, so as to reduce the duration t of said fourth variation phase Tb 3-Tb 4_Tb3-Tb4. By reducing the duration of the two variation phases, the turn-on loss of the NMOS power tube in the turn-off process can be further reduced.

In summary, the drive control circuit and the drive control method of the invention can improve the problems of overvoltage breakdown of the drain voltage of the NMOS power transistor and electromagnetic interference by increasing the duration of the miller stage in the turn-off process of the NMOS power transistor; and the falling time of the grid voltage in the turn-off process of the NMOS power tube can be reduced, and the conduction loss is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (11)

1. A driving control circuit for driving and controlling an NMOS power transistor having a gate parasitic capacitance, the driving control circuit comprising: a PMOS switch tube and a discharge regulating module, wherein,

the grid electrode of the PMOS switching tube is connected with a PWM signal, the source electrode of the PMOS switching tube is connected with power supply voltage, and the drain electrode of the PMOS switching tube is connected with the grid electrode of the NMOS power tube;

the discharging adjusting module is connected between the grid of the NMOS power tube and the ground, is controlled by the PWM signal, and is used for carrying out stage discharging on the grid parasitic capacitance of the NMOS power tube based on different discharging paths along with the change of the grid voltage of the NMOS power tube when the PWM signal is changed from a low level to a high level.

2. The drive control circuit according to claim 1, wherein the discharge regulation module comprises: a first discharge regulating unit, a second discharge regulating unit and a third discharge regulating unit which are connected between the grid of the NMOS power tube and the ground and controlled by the PWM signal,

the first discharge adjusting unit is used for forming a discharge path from the grid parasitic capacitance of the NMOS power tube to the ground in a first change stage of the grid voltage of the NMOS power tube;

the second discharge adjusting unit is used for forming a discharge path from the grid parasitic capacitance of the NMOS power tube to the ground in a first change stage to a sixth change stage of the grid voltage of the NMOS power tube;

the third discharge adjusting unit is used for forming a discharge path from the grid parasitic capacitance of the NMOS power tube to the ground in a fifth change stage and a sixth change stage of the grid voltage of the NMOS power tube.

3. The drive control circuit according to claim 2, wherein the first discharge adjustment unit includes: a first NMOS transistor and a driving portion, wherein,

the grid electrode of the first NMOS tube is connected with the output end of the driving part, the drain electrode of the first NMOS tube is connected with the grid electrode of the NMOS power tube, and the source electrode of the first NMOS tube is grounded;

the drive part is connected between the grid electrode of the NMOS power tube and the ground, is controlled by the PWM signal, and is used for generating and outputting a drive signal in a first change stage of the grid electrode voltage of the NMOS power tube so as to control the first NMOS tube to be conducted.

4. The drive control circuit according to claim 3, wherein the drive section includes: the second NMOS transistor, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the first resistor; the grid electrode of the second NMOS tube is connected to the PWM signal, the drain electrode of the second NMOS tube is connected with the drain electrode and the grid electrode of the first PMOS tube, and the source electrode of the second NMOS tube is grounded; the source electrode of the first PMOS tube is connected with the drain electrode and the grid electrode of the second PMOS tube; the source electrode of the second PMOS tube is connected with the grid electrode of the NMOS power tube, and the grid electrode of the second PMOS tube is connected with the grid electrode of the third PMOS tube; and the source electrode of the third PMOS tube is connected with the grid electrode of the NMOS power tube, and the drain electrode of the third PMOS tube is grounded through the first resistor and is used as the output end of the driving part.

5. The drive control circuit according to claim 2, wherein the second discharge adjustment unit includes: a third NMOS transistor and a current limiting resistor; and the grid electrode of the third NMOS tube is connected with the PWM signal, the drain electrode of the third NMOS tube is connected with the grid electrode of the NMOS power tube, and the source electrode of the third NMOS tube is grounded through the current-limiting resistor.

6. The drive control circuit according to claim 2, wherein the third discharge adjustment unit includes: a control portion and a discharge portion, wherein,

the control part is connected between a power supply voltage and the ground, is controlled by the grid voltage of the NMOS power tube and is used for generating and outputting an effective control signal in a fifth change stage and a sixth change stage of the grid voltage of the NMOS power tube;

the discharge part is connected between the grid of the NMOS power tube and the ground, is controlled by the PWM signal and the control signal, and is used for forming a discharge path from the grid parasitic capacitance of the NMOS power tube to the ground when the control signal is effective.

7. The drive control circuit according to claim 6, wherein the control section includes: the fourth NMOS tube, the first triode and the second resistor; the grid electrode of the fourth NMOS tube is connected with the grid electrode of the NMOS power tube, the drain electrode of the fourth NMOS tube is connected with the power supply voltage through the second resistor and outputs a control signal, and the source electrode of the fourth NMOS tube is connected with the base electrode of the first triode; and the collector electrode of the first triode is connected with the drain electrode of the fourth NMOS tube, and the emitter electrode of the first triode is grounded.

8. The drive control circuit according to claim 7, wherein the discharge portion includes: a fifth NMOS transistor and a sixth NMOS transistor; the grid electrode of the fifth NMOS tube is connected to the control signal, the drain electrode of the fifth NMOS tube is connected with the grid electrode of the NMOS power tube, and the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube; and the grid electrode of the sixth NMOS tube is connected to the PWM signal, and the source electrode of the sixth NMOS tube is grounded.

9. The driving control circuit of claim 8, wherein when the second discharging unit includes the third NMOS transistor and a current limiting resistor, a sum of an on-resistance of the fifth NMOS transistor and an on-resistance of the sixth NMOS transistor is smaller than a sum of an on-resistance of the third NMOS transistor and a resistance of the current limiting resistor.

10. A driving control method for driving and controlling an NMOS power tube with a gate parasitic capacitance is characterized by comprising the following steps:

when the PWM signal is changed from high level to low level, the grid parasitic capacitance of the NMOS power tube is charged to power voltage, and the NMOS power tube is changed from off state to on state;

when the PWM signal is changed from a low level to a high level, the grid parasitic capacitance of the NMOS power tube is discharged in stages based on different discharging paths along with the change of the grid voltage of the NMOS power tube, and the NMOS power tube is changed from a conducting state to a cutting-off state.

11. The driving control method according to claim 10, wherein the step of discharging the gate parasitic capacitance of the NMOS power transistor based on three different discharging paths comprises:

discharging the grid parasitic capacitance of the NMOS power tube based on a first discharging path and a second discharging path in a first change stage of the grid voltage of the NMOS power tube;

discharging the grid parasitic capacitance of the NMOS power tube based on a second discharge path at a second change stage, a third change stage and a fourth change stage of the grid voltage of the NMOS power tube;

and discharging the grid parasitic capacitance of the NMOS power tube based on a second discharge path and a third discharge path in a fifth change stage and a sixth change stage of the grid voltage of the NMOS power tube.

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