CN114389612B - Calibration method and device for analog-to-digital converter based on memristor array - Google Patents
Calibration method and device for analog-to-digital converter based on memristor arrayInfo
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- CN114389612B CN114389612B CN202210038250.9A CN202210038250A CN114389612B CN 114389612 B CN114389612 B CN 114389612B CN 202210038250 A CN202210038250 A CN 202210038250A CN 114389612 B CN114389612 B CN 114389612B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
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Abstract
一种基于忆阻器阵列的模数转化器的校准方法及电子装置。该模数转换器包括输入端、偏置端以及结果输出端，该校准方法包括：通过使用忆阻器阵列的至少一列进行乘加运算，向输入端提供第一电流，并通过调节电路向偏置端提供参考电流，以在结果输出端得到第一数字输出值；判断第一数字输出值与第一电流对应的目标数字输出值是否匹配；以及响应于第一数字输出值与目标数字输出值不匹配，调节向调节电路提供的参考电流的大小。该方法及装置可以实现对模数转换器的校准，并且对现有忆阻器阵列架构的开销小、操作简便。
A calibration method and electronic device for an analog-to-digital converter based on a memristor array. The analog-to-digital converter includes an input terminal, a bias terminal, and a result output terminal. The calibration method includes: performing a multiplication-addition operation using at least one column of the memristor array, providing a first current to the input terminal, and providing a reference current to the bias terminal via a regulation circuit to obtain a first digital output value at the result output terminal; determining whether the first digital output value matches a target digital output value corresponding to the first current; and, in response to a mismatch between the first digital output value and the target digital output value, adjusting the reference current provided to the regulation circuit. This method and device can calibrate the analog-to-digital converter, and has low overhead and simple operation for existing memristor array architectures.
Description
Technical Field
The embodiment of the disclosure relates to a calibration method and device of an analog-to-digital converter based on a memristor array.
Background
With the progress of technology and the rapid development of information technology, a computing architecture based on a memristor array is considered as a new generation of very potential data processing device with the advantages of integrated memory, low energy consumption, large-scale integration, parallel operation and the like. In addition, along with the increasing data storage density, the necessity of the multi-resistance device is increasingly highlighted, on one hand, higher requirements are put on the multi-resistance device, and on the other hand, matched peripheral circuits are needed to perform reliable and efficient writing operation on the device.
Disclosure of Invention
At least one embodiment of the present disclosure provides a calibration method of an analog-to-digital converter, where the analog-to-digital converter includes an input terminal, a bias terminal, and a result output terminal, the calibration method includes providing a first current to the input terminal by performing a multiply-add operation using at least one column of a memristor array, and providing a reference current to the bias terminal by an adjustment circuit to obtain a first digital output value at the result output terminal, determining whether the first digital output value matches a target digital output value corresponding to the first current, and adjusting a magnitude of the reference current provided to the adjustment circuit in response to the first digital output value not matching the target digital output value, to reduce a degree of mismatch between the first digital output value and the target digital output value.
For example, in a calibration method of an analog-to-digital converter provided by at least one embodiment of the present disclosure, in response to a first digital output value not matching the target digital output value, adjusting the magnitude of a reference current provided by an adjustment circuit includes, in response to the first digital output value being greater than the target digital output value, adjusting the reference current to reduce a degree of mismatch between the first digital output value and the target digital output value, or, in response to the first digital output value being less than the target digital output value, adjusting the reference current to reduce a degree of mismatch between the first digital output value and the target digital output value.
For example, in a calibration method of an analog-to-digital converter provided in at least one embodiment of the present disclosure, adjusting a magnitude of a reference current provided by an adjustment circuit includes feeding back a first digital output value of the analog-to-digital converter to the adjustment circuit in response to the first digital output value not matching a target digital output value, changing the reference current by the adjustment circuit according to the first digital output value, and providing the changed first digital output value to a bias terminal.
For example, in a calibration method of an analog-to-digital converter provided by at least one embodiment of the present disclosure, before providing a first current to an input through at least one column of a memristor array, the calibration method further includes programming the at least one column of the memristor array such that a conductance of each memristor in the at least one column is in a first conductance state, wherein a target digital output value is determined corresponding to the first conductance state.
For example, in a calibration method of an analog-to-digital converter provided in at least one embodiment of the present disclosure, a first conductance state of a conductance of each memristor is an intermediate resistance state of a conductance value of each memristor.
For example, in a calibration method of an analog-to-digital converter provided by at least one embodiment of the present disclosure, programming at least one column of the memristor array includes programming the 1 column of the memristor array such that the conductance of each memristor in the 1 column is in a first conductance state.
For example, in a calibration method of an analog-to-digital converter provided in at least one embodiment of the present disclosure, performing a multiply-add operation by using at least one column of a memristor array includes introducing the same input voltage signal to each row of inlet terminals of the memristor array, performing a multiply-add operation on the input voltage signal and a conductance value of a memristor of the at least one column by using the at least one column of the memristor array, and obtaining a first current as an operation result from the input terminal.
For example, in a calibration method of an analog-to-digital converter provided in at least one embodiment of the present disclosure, a reference current when matching between a first digital output value and a target digital output value is selected as a nominal standard reference current of the analog-to-digital converter.
The embodiment of the disclosure provides a calibration device of an analog-to-digital converter, wherein the analog-to-digital converter comprises an input end, a bias end and a result output end, the calibration device comprises a signal acquisition module, an adjusting circuit and a control driving module, wherein the signal acquisition module is configured to operate at least one column of a memristor array to perform multiplication and addition operation to obtain a first current and provide the first current to the input end of the analog-to-digital converter, the adjusting circuit is configured to provide a reference current to the bias end of the analog-to-digital converter, the analog-to-digital converter performs analog-to-digital conversion on the first current according to the first current and the reference current and outputs a first digital output value, the control driving module is configured to receive the first digital output value and judge whether a target digital output value corresponding to the first current is matched with the first current, and when the first digital output value is not matched with the target digital output value, the adjusting circuit is enabled to adjust the magnitude of the reference current so as to reduce the mismatch degree between the first digital output value and the target digital output value.
For example, in a calibration device for an analog-to-digital converter provided in at least one embodiment of the present disclosure, the control driving module is further configured to increase the reference current to reduce the degree of mismatch between the first digital output value and the target digital output value when the first digital output value is greater than the target digital output value, or to decrease the reference current to reduce the degree of mismatch between the first digital output value and the target digital output value when the first digital output value is less than the target digital output value.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.
FIG. 1 shows a schematic diagram of a memristor array;
FIG. 2A shows a schematic diagram of a memristor cell with a 1T1R structure;
FIG. 2B shows a schematic diagram of a memristor cell with a 2T2R structure;
FIG. 2C is a schematic diagram of a memristor device including a memristor array;
FIG. 3 is a schematic flow chart of a memristor array-based analog-to-digital converter calibration method provided in at least one embodiment of the present disclosure;
FIG. 4 is a schematic diagram of an analog-to-digital converter for a memristor array provided in accordance with at least one embodiment of the present disclosure;
FIG. 5 is a schematic flow chart diagram of one example of a memristor array-based analog-to-digital converter calibration method provided in at least one embodiment of the present disclosure;
FIG. 6 is a schematic diagram illustrating an analog-to-digital converter calibration method for a memristor array provided in accordance with at least one embodiment of the present disclosure, and
Fig. 7 is a schematic block diagram of a calibration apparatus for an analog-to-digital converter according to at least one embodiment of the present disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
The present disclosure is illustrated by the following several specific examples. Detailed descriptions of known functions and known components may be omitted as so as to not obscure the description of the embodiments of the present invention. When any element of an embodiment of the present invention appears in more than one drawing, the element is identified by the same reference numeral in each drawing.
The final result of the analog-to-digital converter after the multiplication and addition operation is quantized and output, so that the calibration method based on the memristor array is low in cost, simple and convenient to operate and capable of optimizing the accuracy of the analog-to-digital converter is particularly critical.
Memristors are a new type of electronic device whose conductance state can be adjusted by applying an external stimulus. Prior to memristor array operations, it is often necessary to set individual conductance values in the memristor array to within a desired range, for example, operations for the memristor array including a reset operation and a set operation by adjustment of the memristor resistance, and a sampling operation applied to the memristor resistance reading process.
After setting the conductance for each memristor in the memristor array, the resistance (or conductance) of the memristor cell may be read by a read circuit, which may convert the detected value of the current flowing in the memristor into a corresponding digital value (digital code) by detecting the current. For example, the read circuit includes an SA (SENSING AMPLIFIER, sense amplifier) to perform detection of the current, which may further include an IDAC (bit current digital to analog converter) to provide a reference current required for conversion in order to perform conversion of the detected value of the current to a corresponding digital value. As process feature sizes advance, the conductance value of devices in memristors becomes smaller (i.e., resistance value becomes larger) and, in addition, to avoid read disturb, the upper limit of the read voltage applied to a memristor when reading the resistance value of that memristor is typically limited, e.g., the read voltage is typically 0.2V, and thus the current flowing through that memristor becomes smaller.
In addition, considering the requirements of multi-bit (bit) devices, as well as redundancy in circuit design, the pitch of the read currents used to characterize the different conductance states of the memristor array is also becoming smaller, e.g., the unit current can be as small as the order of hundred nA at 28nm technology. However, in practical simulations it was found that it is not easy to make an exact copy of the current in the order of hundred nA, often requiring calibration of the SA when the device is being programmed.
For example, for a memristor in a memristor array, a conduction interval is typically given and it is desirable for the memristor to be able to program the conductance to within the specified conduction range. In the process of programming memristor conductance, when reading and verifying are performed after the conductance value is set, a series of reference current values provided by the IDACs in the SA of the read circuit are truly defined for the memristor array conductance, so that the IDACs in the SA of the read circuit are crucial for accurate replication of unit currents. In order to ensure that the device is in a specified conductivity range, when the unit reference current image (IDAC is entirely floated) is enlarged, the range utilization of SA is not full, and when the unit reference current image (IDAC is entirely lowered) is reduced, the problem of exceeding the range of SA is caused. Therefore, both cases may cause that the accuracy of the SA in the read circuit in practical application cannot reach the ideal value, and if the device is programmed with reference to the inaccurate current detected by the SA, the conductance range after programming the conductance device may deviate from the preset range.
For example, when the conductance of the memristor is read with a fixed read voltage, e.g., a read voltage of 0.2V, the resulting sense current ranges from 0.4 μa to 4 μa for a conductance of2 μs to 20 μs, which will correspond to a particular conductance, producing a particular and unique digital output value. In order to achieve accurate measurement, the SA in the read circuit needs to be checked. In order to realize the verification of the SA, for example, an externally adjustable and known current source may be used as the input of the SA, the output of the SA is observed, the actual digital output of the SA is compared with the expected digital output, and the magnitude of the current bias of the IDAC included in the SA is further adjusted according to the comparison result, so that the actual digital output code output by the SA corresponds to the expected digital output code, and the verification of the SA is realized.
Conventionally, verifying the accuracy of the SA in a read circuit in a device requires setting an accurate resistor on a chip and applying a predetermined detection voltage to the resistor to verify the SA, or generating an accurate current and detecting the current by the SA to verify the SA, but these approaches certainly increase the overhead and the operation of the verification is troublesome.
On the other hand, for the memristor array, after programming the conductance values of the memristors in the memristor array is completed, in the process of using the memristor array to perform operation (such as performing reasoning operation or training operation of a neural network), the memristor array generates an output signal by performing multiplication and addition operation on an input signal, such as an input voltage signal, and outputs the output signal (current signal) through an output circuit, for example, the output circuit includes an analog-to-digital converter (ADC), and the ADC performs analog-to-digital conversion on the output signal to obtain a corresponding digital value, which is used for subsequent processing by software or hardware, for example. Therefore, the accuracy of the ADC that outputs and reads the memristor array output signal is also a value that needs to be checked, so that the range of the ADC can be matched with the range of the memristor array output signal.
In this regard, the inventors of the present disclosure found that, in actual operation, assuming that the deviation of the detection result of the SA in the read circuit for the memristor array is not particularly large, the deviation of the range of the conductance states of the memristor programmed based on the SA from the predetermined range is not large, and therefore, even if the reference current for the IDAC included in the SA is inaccurate, the relative proportion between the respective conductance states of the memristor programmed using the SA is not changed, and the data of a certain number of bits can be normally characterized, and thus, the linear deviation of one entity occurring with respect to programming using the SA is not an essential problem. Moreover, in the actual circuit implementation, the ratio between the individual conductance states, i.e. linearity, is fully guaranteed when it is guaranteed that the surroundings of the IDAC units in the individual SAs in the read circuit are sufficiently similar. However, for an ADC of the output circuit of the memristor array, since the output current of a column of devices needs to be digitized, if the ADC range is further designed according to the preset resistance range, the output of the ADC is easily out of range or under-utilized. Therefore, the calibration method with low cost and simple operation is realized, and on the premise of not losing the range of SA in the reading circuit, the problem that the accuracy of ADC in the output circuit of the memristor array needs to be solved is urgent.
At least one embodiment of the present disclosure provides a memristor array-based analog-to-digital converter calibration method. The analog-to-digital converter includes an input, a bias, and a result output. The calibration method comprises the steps of performing multiply-add operation by using at least one column of a memristor array, providing a first current to an input end, providing a reference current to a bias end through an adjusting circuit to obtain a first digital output value at a result output end, judging whether the first digital output value is matched with a target digital output value corresponding to the first current, and adjusting the magnitude of the reference current provided to the adjusting circuit in response to the fact that the first digital output value is not matched with the target digital output value so as to reduce the mismatch degree between the first digital output value and the target digital output value.
At least one embodiment of the present disclosure provides a calibration device for an analog-to-digital converter, where the analog-to-digital converter includes an input terminal, an offset terminal, and a result output terminal, and the calibration device includes a signal acquisition module, an adjustment circuit, and a control driving module. The signal acquisition module is configured to operate at least one column in the memristor array to perform multiplication and addition operation to obtain a first current and provide the first current to a first input end of the analog-to-digital converter, the adjusting circuit is configured to provide a reference current to a bias end of the analog-to-digital converter, the analog-to-digital converter performs analog-to-digital conversion on the first current according to the first current and the reference current and outputs a first digital output value, the control driving module is configured to receive the first digital output value and judge whether the first digital output value is matched with a target digital output value corresponding to the first current, and when the first digital output value is not matched with the target digital output value, the adjusting circuit is enabled to adjust the magnitude of the first reference current to reduce the mismatch degree between the first digital output value and the target digital output value.
According to the analog-to-digital converter calibration method and the analog-to-digital converter calibration device based on the memristor array, for example, the analog-to-digital converter (ADC) in the output circuit of the memristor array can calibrate the ADC in the memristor array, the cost of the calibration on the memristor array architecture is small, the operation is simple and convenient, the accuracy of the ADC in the output circuit can be improved based on the accuracy of SA in the reading circuit, and therefore the accuracy of reasoning operation or training operation after the memristor array is programmed is improved.
The operation of the memristor array is to complete multiply-accumulate calculation in parallel according to kirchhoff current law and ohm law, and the storage and calculation of data can be completed by each device of the memristor array, so that the overhead of data movement in a von Neumann-based architecture is avoided.
For example, FIG. 1 shows a schematic diagram of a memristor array. As shown in FIG. 1, the memristor array is composed of a plurality of memristor units, wherein the plurality of memristor units form an array of M rows and N columns, and M and N are positive integers. Each memristor cell includes a switching element and one or more memristors. WL <1>, WL <2>. WL < M > respectively represent the first row and the second row, the word lines of the M-th row, BL <1>, BL <2>. The bit lines of the N-th column respectively represent the first column and the second column, and SL <1>, SL <2>. The source lines of the first row and the second row. The control electrode (such as the gate of a transistor) of a switching element in each row of memristor unit circuits is connected with a word line corresponding to the row, the memristors in each column of memristor unit circuits are connected with a bit line corresponding to the column, and the source of the transistor in each row of memristor unit circuits is connected with a source line corresponding to the row. It should be noted that the directions of the rows and the columns in the present disclosure are not limited to the case of fig. 1, but may be determined according to need, and the scope of the present disclosure is not limited and will not be described in detail below.
For example, the memristor cell shown in fig. 1 may be, for example, a 1T1R structure or a 2T2R structure, where the memristor cell of the 1T1R structure includes one switching transistor and one memristor, and the memristor cell of the 2T2R structure includes two switching transistors and two memristors. The present disclosure is not limited with respect to the type, structure, etc. of memristor devices. It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (e.g., MOS field effect transistors) or other switching devices with the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that the source and drain may be indistinguishable in structure. Embodiments of the present disclosure are not limited in the type of transistor employed.
For example, FIG. 2A shows a schematic diagram of a memristor cell with a 1T1R structure, as shown in FIG. 2A, the memristor cell with the 1T1R structure includes one transistor M1 and one memristor R1.
For example, when transistor M1 is an N-type transistor, its gate is connected to word line terminal WL, e.g., transistor M1 is turned on when word line terminal WL inputs a high level, a first pole of transistor M1 may be a source and configured to be connected to source line terminal SL, e.g., transistor M1 may receive a reset voltage through source line terminal SL, a second pole of transistor M1 may be a drain and configured to be connected to a second pole (e.g., negative electrode) of memristor R1, a first pole (e.g., positive electrode) of memristor R1 is connected to bit line terminal BL, e.g., memristor R1 may receive a set voltage through bit line terminal BL. For example, when transistor M1 is a P-type transistor, its gate is connected to word line terminal WL, e.g., transistor M1 is turned on when word line terminal WL inputs a low level, a first pole of transistor M1 may be a drain and configured to be connected to source line terminal SL, e.g., transistor M1 may receive a reset voltage through source line terminal SL, a second pole of transistor M1 may be a source and configured to be connected to a second pole (e.g., a negative pole) of memristor R1, a first pole (e.g., a positive pole) of memristor R1 is connected to bit line terminal BL, e.g., memristor R1 may receive a set voltage through bit line terminal BL. It should be noted that the resistive random access memory structure may also be implemented as other structures, for example, a structure in which the second pole of the memristor R1 is connected to the source terminal SL, which is not limited by the embodiments of the present disclosure.
The following embodiments will take the N-type transistor as an example of the transistor M1.
The word line terminal WL functions to apply a corresponding voltage to the gate of the transistor M1, thereby controlling the transistor M1 to be turned on or off. In the operation of the memristor R1, for example, the set operation or the reset operation, the transistor M1 needs to be turned on first, that is, an on voltage needs to be applied to the gate of the transistor M1 through the word line end WL. After transistor M1 is turned on, the resistance state of memristor R1 may be changed, for example, by applying voltages to memristor R1 at source terminal SL and bit terminal BL. For example, a set voltage may be applied through the bit line terminal BL to place the memristor R1 in a low resistance state, and a reset voltage may be applied through the source line terminal SL to place the memristor R1 in a high resistance state. For example, the resistance value in the high resistance state is 100 times or more, for example 1000 times or more, that in the low resistance state.
It should be noted that, in the embodiment of the present disclosure, for example, by applying voltages to the word line terminal WL and the bit line terminal BL simultaneously, the resistance value of the memristor R1 may be made smaller and smaller, that is, the operation of changing the memristor R1 from the high resistance state to the low resistance state will be referred to as a set operation, and by applying voltages to the word line terminal WL and the source line terminal SL simultaneously, the resistance value of the memristor R1 may be made larger and larger, that is, the operation of changing the memristor R1 from the low resistance state to the high resistance state will be referred to as a reset operation. For example, the memristor R1 has a threshold voltage that does not change the resistance value (or conductance value) of the memristor R1 when the input voltage magnitude is less than the threshold voltage of the memristor R1. In this case, the resistance value (or conductance value) of the memristor R1 may be calculated by inputting a voltage smaller than the threshold voltage, and the resistance value (or conductance value) of the memristor R1 may be changed by inputting a voltage larger than the threshold voltage.
For example, FIG. 2B shows a schematic diagram of a memristor cell with a 2T2R structure. As shown in fig. 2B, the memristor cell of the 2T2R structure includes two transistors M1 and M2 and two memristors R1 and R2. The following description will take an example in which the transistors M1 and M2 are both N-type transistors.
The gate of the transistor M1 is connected to the word line terminal WL1, e.g. the transistor M1 is turned on when the word line terminal WL1 of M1 inputs a high level, the gate of the transistor M2 is connected to the word line terminal WL2, e.g. the transistor M2 is turned on when the word line terminal WL2 of M2 inputs a high level, the first pole of the transistor M1 may be a source and configured to be connected to the source line terminal SL, e.g. the transistor M1 may receive a reset voltage via the source line terminal SL, the first pole of the transistor M2 may be a source and configured to be connected to the source line terminal SL, e.g. the transistor M2 may receive a reset voltage via the source line terminal SL, and the first pole of the transistor M1 is connected to the first pole of the transistor M2 and together to the source line terminal SL. The second pole of transistor M1 may be a drain and configured to be connected to a second pole (e.g., a negative pole) of memristor R1, the first pole (e.g., a positive pole) of memristor R1 may be connected to bit line terminal BL1, for example memristor R1 may receive a set voltage through bit line terminal BL1, and the second pole of transistor M2 may be a drain and configured to be connected to a second pole (e.g., a negative pole) of memristor R2, the first pole (e.g., a positive pole) of memristor R2 may be connected to bit line terminal BL2, for example memristor R2 may receive a set voltage through bit line terminal BL 2.
It should be noted that, the transistors M1 and M2 in the memristor unit with the 2T2R structure may also be P-type transistors, which is not described herein again.
For example, in the case of performing a read operation on the memristor R1, as shown in fig. 2A, the transistor M1 needs to be turned on first, that is, an on voltage may be applied to the gate of the transistor M1 through the word line terminal WL, for example, the source line terminal SL may be grounded and a dc voltage may be provided to a resistor to be read, for example, a dc voltage may be applied to the bit line terminal BL and a current flowing through the resistor may be read by using SA, and the SA may output a digital output code according to the detected current, so that the digital output code may directly reflect the magnitude of the resistance value in the memristor unit. For example, when the resistance value reflected by the SA deviates from the expected resistance value, a corresponding set operation or reset operation may be performed on the memristor unit, so as to change the resistance value of the memristor unit, and then read again through the SA.
FIG. 2C is a schematic diagram of a memristor device including a memristor array. The memristor device comprises a memristor array and a peripheral driving circuit thereof, wherein the peripheral driving circuit is used for realizing an input and output function. As shown in fig. 2C, the memristor device includes a signal acquisition device, a word line drive circuit, a bit line drive circuit, a source line drive circuit, a memristor array, and a data output circuit. The memristor device may further include a reading circuit (not shown in the figure) including a Sense Amplifier (SA) for reading the resistance value of the memristor after having been programmed.
For example, the signal acquisition device is configured to convert a digital signal to a plurality of first analog signals through a digital-to-analog converter (Digital to Analog converter, DAC) for input to a plurality of column signal inputs of the memristor array when performing, for example, signal processing.
For example, a memristor array includes M source lines, M word lines, and N bit lines, and a plurality of memristor cells arranged in M rows and N columns. For example, each memristor cell is a 1T1R structure, e.g., a parameter matrix for fourier transformation may be mapped to a plurality of memristor cells in a memristor array.
For example, operation of the memristor array is achieved by a word line drive circuit, a bit line drive circuit, and a source line drive circuit.
For example, the word line driving circuit includes a plurality of multiplexers (Mux) for switching the word line input voltages, the bit line driving circuit includes a plurality of multiplexers for switching the bit line input voltages, and the source line driving circuit also includes a plurality of multiplexers (Mux) for switching the source line input voltages. For example, the source line driving circuit further includes a plurality of ADCs for converting analog signals into digital signals.
For example, a memristor array includes a programming (same below) mode and a computing mode. When the memristor array is in the operational mode, the memristor cells are in an initialized state, values of parameter elements in the parameter matrix may be written into the memristor array, e.g., a weight matrix of the neural network is mapped into the memristor array. For example, the source line input voltage, the bit line input voltage, and the word line input voltage of the memristor are switched to corresponding preset voltage intervals through the multiplexer. And then, the resistance value of each memristor in the memristor array can be detected by applying a read voltage to the input end of the memristor array and a read circuit, and if the resistance value of a certain memristor does not accord with a preset value, the setting can be carried out again.
For example, the word line input voltage is switched to the corresponding voltage interval by the control signal wl_sw [1:M ] of the multiplexer in the word line driving circuit in fig. 2C. For example, when the memristor is set, the word line input voltage is set to 2V (volts), for example, when the memristor is reset, the word line input voltage is set to 5V, for example, the word line input voltage may be obtained by the voltage signal v_wl [1:M ] in fig. 2C.
For example, the source line input voltage is switched to the corresponding voltage interval by the control signal sl_sw [1:M ] of the multiplexer in the source line driving circuit in fig. 2C. For example, when the memristor is set, the source line input voltage is set to 0V, for example, when the memristor is reset, the source line input voltage is set to 2V, for example, the source line input voltage may be obtained by the voltage signal v_sl [1:M ] in fig. 2C.
For example, the bit line input voltages are switched to the corresponding voltage intervals by the control signals BL_sw [1:N ] of the multiplexers in the bit line driving circuit in FIG. 2C. For example, the bit line input voltage is set to 2V when the memristor is set, for example, the bit line input voltage is set to 0V when the memristor is reset, for example, the bit line input voltage may be obtained by the DAC in fig. 2C.
For example, when the memristor array is in a calculation mode, the memristors in the memristor array are in a conductive state available for calculation (reasoning or training), and the bit line input voltage input by the column signal input terminal does not change the conductance value of the memristor, for example, the calculation can be completed by performing a multiply-add operation through the memristor array. For example, the word line input voltages are switched to the corresponding voltage intervals by the control signal WL_sw [1:M ] of the multiplexer in the word line driving circuit in FIG. 2C, for example, when an on signal is applied, the word line input voltages of the corresponding row are set to 5V, for example, when no on signal is applied, the word line input voltages of the corresponding row are set to 0V, for example, the GND signal is turned on, the quantization of the output currents of which columns is determined by the control signal SL_sw [1:M ] of the multiplexer in the source line driving circuit in FIG. 2C, and the BL_sw [1:N ] determines which BL applies the input voltages.
For example, the data output circuit may include a plurality of ADCs that may quantize the current signals at the plurality of column signal outputs and convert the quantized current signals to digital output.
Fig. 3 is a schematic flow chart of an analog-to-digital converter calibration method based on a memristor array according to at least one embodiment of the present disclosure, and fig. 4 is a schematic diagram of an analog-to-digital converter for a memristor array according to at least one embodiment of the present disclosure. The following is a description with reference to fig. 3 and 4.
As shown in fig. 4, the memristor device includes a memristor array 201 and an analog-to-digital converter in an output circuit coupled to the memristor array 201, the memristor array 201 includes a plurality of rows and columns of memristor cells, only 1 column is shown in fig. 4 as an example, and other components other than the analog-to-digital converter are omitted. The memristor array 201 may receive one or more voltage signals in a row direction, and output one or more output currents in a column direction after being processed by the memristor array 201, where an output current corresponding to a column of memristors is a result of multiplying and adding a conductance value of the column of memristors and one or more input voltage signals, and a current value of the output current is converted into a digital value by an analog-to-digital converter (described below) in an output circuit. Embodiments of the present disclosure are not limited in the structure and type of memristor cells.
For example, analog signals are input to a plurality of column signal input terminals of the memristor array after the conductance setting (programming) is completed, for example, the analog signals may be voltage signals, so that the memristor array may be controlled to perform multiplication and addition operations. According to kirchhoff's law, the output current of a memristor array can be derived according to the following equation (1):
Formula (1)
Wherein j=1, the combination of the first and second components, M, k=1.., N.
In the above formula (1), V k represents the voltage input to the kth column signal input terminal of the plurality of column signal input terminals, and I j represents the current signal output from the jth row signal output terminal of the plurality of row signal output terminals. G jk denotes the memristor cell bulk conductance value at the j-th row and k-th column. From kirchhoff's law, the memristor array can perform multiply-accumulate calculations (i.e., the multiply-add operations described above) in parallel.
The analog-to-digital converter is used for converting a current analog signal output by a memristor array in the memristor device as a calculation result into a current digital signal, and one column of memristor is connected with one analog-to-digital converter correspondingly. The analog-to-digital converter comprises an input end, a bias end and a result output end, wherein the input end is connected with the output end of at least one column of the memristor array, and the bias end is connected with an adjusting circuit used for calibration.
More specifically, as shown in fig. 4, the analog-to-digital converter may include a signal amplification circuit 401, a comparator 501, and a bit current digital-to-analog conversion circuit (IDAC) 301. The input of the signal amplification circuit 401 is used as the input a of the analog-to-digital converter, receiving the first current I in from the memristor array. The offset end of the bit current digital-to-analog conversion circuit (IDAC) 301, i.e. the offset end of the ADC itself, is used to replicate the off-chip reference current I 0 by an integer multiple to generate a plurality of comparison currents for comparison, each comparison current value corresponding to a digital value, the current values of the plurality of comparison currents (i.e. the corresponding digital values) may be increased one by one, for example, according to the operation mode, or according to, for example, a binary search mode. The comparison current I DAC is input to the bias terminal of the signal amplification circuit 401. Here, the reference current I 0 is provided by the adjusting circuit 302, and the adjusting circuit 302 can adjust the magnitude of the reference current I 0, for example, the larger the reference current I 0, the larger the comparison current value generated by the IDAC 301 for the same digital value.
For example, the signal amplifying circuit 401 may amplify an input signal, for example, the signal amplifying circuit 401 may be a transimpedance amplifier, and convert an input current signal into a voltage signal, where the input first current I in and the comparison current I DAC may be converted into voltage signals and then input to the comparator 501.
The comparator 501 comprises two inputs, a third input D and a fourth input E, respectively, and a result output C. The third input D and the fourth input E are respectively configured to receive two signals for comparison, and the result output C is used as a result output of the analog-to-digital converter. The comparator 501 compares two voltage signals, which are the voltage of the input current and the output current of the IDAC 301 after TIA conversion, respectively, so that it can be compared which of the first current I in and the comparison current I DAC is larger (or smaller). The comparator 501 obtains the relationship between the first current I in and a plurality of digital output values by comparing the first current I in with successive approximations of a plurality of comparison currents (i.e., with currents corresponding to a plurality of digital output values) which are sequentially input, thereby being able to determine a first digital output value N corresponding to the first current I in, which is output as a resultant output value of the analog-to-digital conversion. As described above, the larger the reference current I 0, the larger the comparison current value generated by IDAC 301 for the same digital value, and the smaller the digital value output by output terminal C as a result for the same first current I in.
As shown in fig. 3, for a memristor array that completes programming, the analog-to-digital converter calibration method based on the memristor array includes the following steps S101-S104:
step 101, a first current is provided to an input terminal by performing a multiply-add operation using at least one column of the memristor array, and a reference current is provided to a bias terminal by an adjusting circuit, so as to obtain a first digital output value at a result output terminal.
In the step, a voltage signal is applied to a signal input end of the memristor array in a row direction, at least one column of the memristor array is used for multiplication and addition operation, so that a first current is obtained corresponding to the at least one column of memristor, and the first current is a result of multiplication and addition operation of the applied voltage signal and a conductance value obtained by programming the at least one column of memristor. The analog-to-digital converter generates a first digital output value corresponding to the first current based on the received reference current (i.e., the reference current input to the IDAC 301 of the analog-to-digital converter). For example, the applied voltage signal may be selected as desired, for example, N is an integer N times greater than or equal to 1 than a read voltage (e.g., 0.2V) employed by the read circuit. For example, when the voltage signal is equal to the read voltage, the target digital output value in the following step 102 can be directly obtained by reading the output value of the SA in the circuit, thereby calibrating the SA of the read circuit related to the programming process and the ADC of the output circuit related to the calculation process in a correlated manner, and realizing the self-adaptive calibration of the ADC on the SA.
Step 102, determining whether the first digital output value matches a target digital output value corresponding to the first current.
In response to the first digital output value not matching the target digital output value, the magnitude of the reference current provided to the regulating circuit is adjusted to reduce the degree of mismatch between the first digital output value and the target digital output value, step 103.
Step 104, responsive to the first digital output value matching the target digital output value, determining the first digital output value as a final output value.
The calibration method shown in fig. 3 can calibrate the output digital value of the memristor array after the forward calculation (multiplication and addition operation) is completed on the memristor array, in the method, the first digital output value finally output by the ADC in the output circuit is directly calibrated, so that the additional cost caused by firstly calibrating the final ADC output value after the SA calibration is avoided, the complicated operation required by such secondary calibration is avoided, and the method is also helpful for improving the accuracy of the ADC used for the forward calculation of the memristor array.
As described above, for example, before proceeding to step 101, in order to provide a first current to the input through at least one column of the memristor array, the calibration method therefore further includes programming at least one column of the memristor array such that the conductance of each memristor in the at least one column is in a first conductance state, and reading the set first conductance state using a read circuit (including SA) during the programming. A target digital output value is determined corresponding to the first conductance state, e.g., the target digital output value is determined based on the first conductance state and the voltage signal selected for the forward operation, such that a first current resulting from a multiply-add operation using at least one column of the memristor array after the corresponding voltage signal is input is a desired current value. For example, assuming that the conductance of the memristor is set to 2 μs (corresponding to 500K ohms), when a read voltage of 0.2V is employed, the SA output digital value 0100 (binary) of the read circuit, then when the voltage signal (input signal) applied at the time of the forward operation is also 0.2V, the target digital output value at the time of calibration should be 0100 (binary), or when the voltage signal applied at the time of the forward operation is also 0.4V, the target digital output value at the time of calibration should be 1000 (binary).
For example, in at least one embodiment of the present disclosure, as shown in FIG. 4, prior to the memristor array 201 passing a first current I in to the signal amplification circuit 401, at least one column of the memristor array 201 is first programmed such that the conductance of each memristor in the at least one column is in a first conductance state, e.g., from which a target digital output value N 0 of the ADC for verification purposes is derived.
The multiplication and addition operation is performed by using at least one column of the memristor array, and multiple columns (i.e., 2 or more columns) may be used, or only 1 column may be used, where the calibrated analog-to-digital converter is electrically connected to the output terminals of the multiple columns of memristors, and where the calibrated analog-to-digital converter is electrically connected to the output terminals of the 1 column of memristors, for example.
For example, in at least one embodiment of the present disclosure, 1 column in a memristor array is programmed such that the conductance of each memristor in that column is in a first conductance state. For example, as shown in FIG. 4, 1 column of the selected memristor array 201 is electrically connected to the analog-to-digital converter, and thus a first current I in resulting from the multiplication-addition operation of the 1 column memristor is input to the input terminal A of the analog-to-digital converter under verification.
For example, rows and columns in the memristor array 201 that are to be conductively programmed may be selected by a multiplexer (not shown), and then one-by-one conductive programming may be performed for the memristor cells on the selected columns. For example, when setting the conductance value for a memristor cell on a selected column, the conductance value may be adjusted, for example, by a corresponding set operation or reset operation. In the process of adjusting the conductance values, for example, the conductance values of the memristor units can be read through the SA in the reading circuit, so that the digital output value corresponding to each memristor unit is obtained. For example, when the memristor cells on a selected column of memristors are set to a first conductance state, the first conductance state may be an intermediate resistance state of a conductance value of each memristor, where the intermediate resistance state corresponds to half a range of an analog-to-digital converter (ADC) in the output circuit, for example, a digital value of 0 to 127 (decimal), and the intermediate resistance state corresponds to 64 (binary corresponds to 1000000), and embodiments of the disclosure are not limited thereto.
For example, in the analog-to-digital converter calibration method based on the memristor array provided in at least one embodiment of the present disclosure, step 101 further includes introducing the same input voltage signal to each row of the inlet end of the memristor array, and multiplying and adding the input voltage signal and the conductance values of the memristors of at least one column by using at least one column of the memristor array, and obtaining the first current as the operation result from the input end. In this regard, referring to FIG. 4, the inputs of a selected column of memristors are electrically connected together and are input with the same voltage signal V 0.
Therefore, according to the above formula (1), if the conductance of the memristors in the 1 column is set to be in the intermediate resistance state, when the same voltage signal V 0 is input to the input ends of the plurality of memristor units in the 1 column, the current output values of the memristor units in each row in the column after the multiplication and addition operation all correspond to the current I j under the voltage signal V 0, so that after the addition operation of each row I j, the current output I i corresponding to the memristor units in the column in the intermediate resistance state can be obtained, and accordingly, the conversion result of the current output I i after the ADC also corresponds to the intermediate range of the ADC.
Specifically, for step 101, as shown in FIG. 4, a multiplication and addition operation may be performed by using a column of the memristor array 201 to provide a first current I in to the input terminal A of the analog-to-digital converter and a reference current I 0 to the bias terminal B of the analog-to-digital converter through the adjusting circuit 302, the IDAC 301 outputs a plurality of comparison currents for comparison with the first current I in based on the reference current I 0, and each comparison current value corresponds to a digital value, and the current values of the plurality of comparison currents (i.e., corresponding digital values) may be increased one by one according to an operation mode, or increased according to a binary search mode, for example.
The first current I in and the comparison current I DAC may be amplified by the same signal amplifying circuit 401 and converted into voltage signals respectively, and then enter the comparator 501 for comparison, and after a plurality of periods, the result output terminal C of the comparator 501 outputs a first digital output value N corresponding to the first current I in.
In at least one example, the signal amplification circuit 401 is a transimpedance amplifier that can convert a current signal to a voltage signal. For example, the signal amplifying circuit 401 may amplify and convert the first current I in, so that a corresponding amplified signal V in may be obtained at the third input terminal D of the comparator 501, and for example, the signal amplifying circuit 401 may amplify and convert the comparison current I DAC, so that a corresponding amplified signal V DAC may be obtained at the third input terminal E of the comparator 501.
The comparator 501 compares the amplified signal V in corresponding to the first current I in and the amplified signal V DAC corresponding to the comparison current I DAC, respectively, from the signal amplifying circuit 401. The comparator 501 obtains the first current I in by comparing the first current I in with successive approximations of a plurality of comparison currents (i.e., with currents corresponding to a plurality of digital values) which are sequentially input, and a series of numbers (for example, the series of numbers are composed of numbers of 0 or 1), thereby being able to determine a digital value corresponding to the first current, wherein the digital value is output as a first digital output value N of analog-digital conversion.
For example, in step 102, it is determined whether the first digital output value N matches the target digital output value N corresponding to the first current I in. For example, the comparator 501 may output a corresponding digital signal N after comparing and performing analog-to-digital conversion, collect the digital signal N, then determine whether the first digital output value N matches a target digital output value N 0 (the number may be provided by a system or input by a user, for example) corresponding to the first current I in, and provide the determination result to the adjusting circuit 302 connected to the bit current digital-to-analog conversion circuit 301.
In step 103, the conversion radix of the bit current digital-to-analog conversion circuit 301 may be changed by changing the magnitude of the reference current I 0 applied to the bit current digital-to-analog conversion circuit 301, for example, in response to the first digital output value N not matching the target digital output value N 0, thereby reducing the degree of mismatch between the first digital output value N and the target digital output value N 0, or the first digital output value N may be determined as the final output value in response to the first digital output value N matching the target digital output value N 0.
For example, in the case where the first digital output value N does not match the target digital output value N 0, step 103 may further include reducing the degree of mismatch between the first digital output value N and the target digital output value by adjusting the reference current I 0 applied to the bit current digital-to-analog conversion circuit 301 to a large value when the first digital output value N is greater than the target digital output value N 0, or by adjusting the reference current I 0 applied to the bit current digital-to-analog conversion circuit 301 to a small value when the first digital output value N is less than the target digital output value N 0.
For example, in at least one embodiment of the present disclosure, as shown in fig. 4, the third input D receives the corresponding amplified signal V in and the third input E receives the corresponding amplified signal V DAC, which are compared in the comparator 501, and the comparison result is obtained. For example, the comparator 501 may comprise an M-bit register for recording the result of the successive approximation comparison and a control circuit, e.g. an M-bit register, for example, the result of the comparison of the amplified signal V in and the amplified signal V DAC may be output, controlling the bit current digital-to-analog conversion circuit 301 for the output of the next (sub) comparison current I 0 until the comparator 501 outputs the target digital output value N 0.
For example, in at least one example, according to a search algorithm, an M-bit register is first set to an intermediate value of the span, e.g., for a span of 63 (i.e., 2≡6, in binary representation 111111), then the comparison current corresponding to 32 may be used for the first comparison, the MSB of the register is set to 1, i.e., corresponding to binary result 100000, e.g., with V REF being the nominal comparison voltage corresponding to V DAC for the full span of the analog-to-digital converter, first, the amplified signals V in and V REF/2 are compared in the comparator 501, in the case of V in being greater than V REF/2, the comparator 501 outputs a logic high level or "1", the MSB of the M-bit register remains to 1, i.e., the highest of the final output target digital value is 1, on the contrary, in the case of V in being less than V REF/2, the comparator outputs a logic low level or "2", the highest of the final output target digital value is 0, then the control in the comparator is controlled to shift the MSB logic until the next, and the comparison is completed in the next time, the MSB logic is shifted down according to the next comparison.
For example, in at least one embodiment of the present disclosure, when the first digital output value N is determined not to match the target digital output value N 0 corresponding to the first current I in, the IDAC 301 may further adjust the rated comparison voltage V REF of the analog-to-digital converter corresponding to the reference current I 0, for example, to V REF2 by changing the magnitude of the reference current I 0.
For example, when the first digital output value N is greater than the target digital output value N 0 corresponding to the first current I in, the reference current I 0 may be adjusted by adjusting the reference current I 0 applied to the IDAC 301, that is, the rated comparison voltage V REF of the analog-to-digital converter, so that the reference range of the ADC is adjusted to be greater as a whole, so that the ADC output digital value (output code) corresponding to the reference range of the ADC corresponding to the first current I in after being adjusted to be greater will be reduced, whereas, for example, when the first digital output value N is less than the target digital output value corresponding to the first current I in, the reference current I 0 may be adjusted to be reduced by the IDAC 301, that is, the rated comparison voltage V REF of the analog-to-digital converter corresponding to the reference current I 0 is adjusted to be reduced as a whole, so that the ADC output digital value corresponding to the reference range of the ADC corresponding to the first current I in after being adjusted to be greater will be increased.
After the reference current I 0 applied to IDAC 301 is changed, the comparator 501 of the ADC may output a changed first digital output value N 1 for the first current I in, compare the changed first digital output value N1 with the target digital output value N 0 corresponding to the first current I in again, and decide whether and how to adjust the reference current I 0 applied to IDAC 301 according to the result. The feedback-regulation-output-feedback process is repeated until the desired first digital output value N 0 is finally output at the analog-to-digital converter.
Therefore, according to the comparison result between the first digital output value N and the target digital output value N 0, the rated comparison voltage V REF of the analog-to-digital converter corresponding to the reference current I 0 is further adjusted, so as to reduce the mismatch degree between the first digital output value N and the target digital output value N 0.
In step 104, when the output terminal C output by the comparator 501 results in the first digital output value N corresponding to the first current I in matching the target digital output value N 0, the first digital output value N at this time may be determined as the final output value of the analog-to-digital converter.
For example, accordingly, for calibration, the reference current I 0 at which the first digital output value N matches the target digital output value N 0 is selected as the nominal standard reference current for the analog-to-digital converter, which nominal standard reference current is used as the nominal reference current for the analog-to-digital converter being calibrated.
For example, FIG. 5 is a schematic flow chart of one specific example of a memristor array-based analog-to-digital converter calibration method provided by at least one embodiment of the present disclosure.
For example, in the method shown in fig. 5, the SA in the read circuit is used to set the resistance value of the memristor cell to a desired value, where the output of the ADC of the output circuit is selected to be a value of 100..0 (with bits of 0 omitted) (binary), i.e., the intermediate resistance state of the memristor cell. For example, if the ADC outputs a 6-bit two-level system value (corresponding to a full scale of 127), the resistance value set to 100000 may be selected. When the resistance value is read by the SA corresponding to the intermediate resistance state, the digital output code corresponding to the SA should be the intermediate value of the SA range, and for example, the SA outputs an 8-bit binary value, and the resistance value set to be 10000000 may be selected.
In this example, the ADC calibration method includes the steps of:
Step 601, selecting a column from the memristor array, and programming the resistance of the memristor unit of the column to an intermediate resistance state with SA output of 100..0 when the read voltage is V 0. Accordingly, the full scale range of SA in the read circuit is a resistance state whose output is 111..1.
Step 602, under the condition that the input voltage signal is also V 0, the column selected by the memristor array completes the forward calculation (multiplication and addition operation) under the intermediate resistance state to obtain the binary output value of the ADC, if the output value of the ADC is greater than 100..0, step 603 is executed, if the output value of the ADC is less than 100..0, step 604 is executed, and if the output value of the ADC is equal to 100..0, the calibration is completed.
Step 603, regulating the reference current of the ADC;
step 604, adjusting the reference current of the ADC to be smaller.
For example, in the analog-to-digital converter calibration method provided in the embodiment shown in fig. 5, when the voltage signal V 0 is applied to one column of the memristor array, by programming the resistance value of one column of the memristor cells in the memristor array to the intermediate resistance state, the output value of SA for programming the memristor cells is half of the full scale, for example, for a 6bit device, the output of SA is 100000, and thus, after the forward calculation is completed for one column of the memristor array, the target output value ADC of the corresponding ADC should be 100000. The output digital value obtained in practice can be compared with the target output value 100000 of the ADC corresponding to the intermediate resistance state, and corresponding calibration operation is carried out on the ADC according to the comparison result. For example, when the digital output value of the ADC is larger than the target digital output value 100000 determined based on the intermediate resistance state where the output value of the SA is 100000, the reference range of the ADC is integrally enlarged by enlarging the reference current of the reference current ADC, whereas when the digital output value of the ADC is smaller than the target digital output value 100000 corresponding to the intermediate resistance state, for example, the reference range of the ADC is integrally reduced by reducing the reference current of the reference current ADC, that is, reducing the rated comparison voltage, thereby realizing the calibration of the ADC range.
In addition, the column item conductance in the selected memristor array is set to an intermediate resistance state, so that a target output value 100..0 of the memristor after forward calculation is correspondingly obtained, and further, the output value of the ADC is compared with the target output value 100..0, and then the reference current of the ADC is adjusted, so that the accuracy calibration of the ADC is realized. Therefore, in the process of checking, the resistance of the memristor is set to an intermediate resistance state, so that damage to SA in a reading circuit or ADC in an output circuit in the adjusting process can be reduced, and the protection of an analog-to-digital conversion device is facilitated to be enhanced.
FIG. 6 is a schematic diagram illustrating an analog-to-digital converter calibration method for a memristor array provided in at least one embodiment of the present disclosure.
In fig. 6, the meanings of the parts are as follows and the devices mentioned are for example memristors:
(a) The expected conductance range of the device;
(b) An expected ADC range of range corresponding to the expected conductance range;
(c) Actual conductance range due to SA bias;
(d) The actual ADC range corresponding to the device deviation caused by the deviation of SA;
(e) The actual ADC range of range.
For example, in a typical approach, calibration of the output results of the memristor array during operation includes a two-step calibration. The first step of calibration is the process from (c) to (a), namely, the SA in the reading circuit is calibrated, so that the error of the output value of the SA is reduced, the actual (calibrated) conductance range caused by the deviation of the SA can be matched with the expected conductance range of the device, and the accuracy of the SA when the conductance value of the memristor is programmed is improved. The second step of calibration is the calibration from (e) to (b), namely, for the ADC in the output circuit, the error of the output value of the ADC is reduced, so that the range of the ADC in practice (after calibration) due to the deviation of the ADC can be matched with the range of the ADC range expected corresponding to the range of the conductance expected, thereby improving the accuracy of the ADC when outputting the output current value of the memristor. However, this general method causes the calibration of the SA and the calibration of the ADC to be separated from each other, and if the ADC's range is designed to a preset conductance range, the output of the ADC is easily out of range or the range utilization is not full.
However, generally, the deviation of the SA is not large, the deviation of the measurement result obtained based on the SA from the expected conductance range is not large, and even if there is some inaccuracy in the SA, the relative proportion between the respective conductance states of the respective devices obtained using the same SA is not changed, and data of a certain number can be normally characterized.
Thus, calibration of the range of the ADC used for forward computation for the memristor array can be directly achieved. Thus, as shown in fig. 6, the embodiment of the present disclosure adopts the calibration procedure from (e) to (d) instead of adopting the above-described general method, so that the range of the ADC in reality (after calibration) matches the range of the ADC in reality (after calibration) corresponding to the device deviation due to the deviation of SA, so that the calibration for the ADC is associated with the calibration of SA, thereby realizing the adaptive calibration of the ADC for SA.
For example, when multiplying and computing at least one column in a memristor array, the ADC supports analog-to-digital conversion of the multiplication and addition result of the current of m rows of devices. For the expected conductance range of the device in (a), i.e. the target conductance range of the device, for example, assuming that the expected conductance range of the device is (2 μs,20 μs), the current range of the expected SA is the first interval, i.e. (0.4 μa, 4 μa), when the read voltage is 0.2V, and for the ADC range corresponding to the expected conductance range in (b), the ADC range corresponding to the expected conductance range may be set to (0.4×m) μa within the set forward calculated voltage range. For (c), due to the deviation of SA itself, the actual conductance range of the memristor after programming does not coincide with that in (a), for example, when SA shows that the detected current is 0.4 μA, and the actual conductance value of the memristor is not 20 μS, for example, 25 μS, the output current when forward calculation is performed after the actual device programming is in a second interval, for example, (0.5 μA,5 μA), and for (d), the ADC range interval needs to be calibrated to (0.5 μA) based on the actual ADC range corresponding to the device deviation due to the deviation of SA. Therefore, by adopting the calibration process from (e) to (d), the ADC range calibration can be realized under the condition of taking SA into consideration, and the output precision is improved.
At least one embodiment of the present disclosure further provides a calibration device of an analog-to-digital converter, and fig. 7 is a schematic block diagram of the calibration device of the analog-to-digital converter according to at least one embodiment of the present disclosure.
For example, as shown in fig. 7, the calibration device 700 includes a signal acquisition module 701, an analog-to-digital conversion module 702, and a control driving module 703. The signal acquisition module 701 is configured to operate at least one column of the memristor array to perform a multiply-add operation to obtain a first current, and provide the first current to an input terminal of the analog-to-digital converter, and the adjustment circuit 702 is configured to provide a reference current to a bias terminal of the analog-to-digital converter, wherein the analog-to-digital converter performs analog-to-digital conversion on the first current according to the first current and the reference current, and outputs a first digital output value.
The control driving module 703 is configured to receive the first digital output value, determine whether the first digital output value matches a target digital output value corresponding to the first current, and when the first digital output value does not match the target digital output value, cause the adjusting circuit to adjust the magnitude of the reference current so as to reduce the degree of mismatch between the first digital output value and the target digital output value.
For example, in at least one embodiment of the present disclosure, the adjustment circuit may adjust the magnitude of the reference current when the first digital output value does not match a target digital output value corresponding to the first current, for example, the adjustment circuit may adjust the reference current to a greater magnitude when the first digital output value is greater than the target digital output value, or the adjustment circuit may adjust the reference current to a lesser magnitude when the first digital output value is less than the target digital output value, to reduce the degree of mismatch between the first digital output value and the target digital output value.
It should be noted that, for example, the operation process of the calibration device of the analog-to-digital converter may refer to steps 101 to 104 of the above-mentioned analog-to-digital converter calibration method based on the memristor array and the related descriptions in each embodiment. The repetition is not described in detail herein.
The following points need to be described:
(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.
(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.
The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the disclosure, which is defined by the appended claims.
Claims (8)
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| CN115149952B (en) * | 2022-07-14 | 2025-08-22 | 江南大学 | Current-mode cycle analog-to-digital converter and analog-to-digital conversion method |
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| CN115862708A (en) * | 2022-11-23 | 2023-03-28 | 清华大学 | Memristor array operating method, data processing device |
| CN116032258A (en) * | 2022-12-23 | 2023-04-28 | 清华大学 | Delay buffer unit and operating method thereof, computing device and operating method thereof |
| CN116129961B (en) * | 2023-02-17 | 2025-09-30 | 电子科技大学 | A method for setting the resistance state of a memristor crossbar array device |
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| CN102075188B (en) * | 2010-12-31 | 2013-07-17 | 北京时代民芯科技有限公司 | Digital static calibration circuit of digital-to-analog converter (DAC) |
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