CN114374375A - Decision feedback equalizer and PAM-4 receiver - Google Patents

Abstract

The invention provides a decision feedback equalizer and a PAM-4 receiver, on one hand, parasitic capacitance is reduced by reducing the number of interfaces of an equalizing tap, and the time for establishing a summator is reduced; on the other hand, the delay caused by the sampling decision device is reduced by increasing the bandwidth of the sampling stage and increasing the input amplitude of the latch; therefore, the loop delay of the DFE is comprehensively reduced from two aspects, and the problem of short timing sequence margin is solved.

Description

A Decision Feedback Equalizer and PAM-4 Receiver

technical field

The present invention relates to the field of communication technologies, and more particularly, to a decision feedback equalizer and a PAM-4 receiver.

Background technique

In recent years, with the development of the Internet and digital integrated circuits, especially the continuous improvement of the speed of CPU (Central Processing Unit, central processing unit), the relatively low data transmission rate between chips, between backplanes, and even between local area networks has become more and more It has become the performance bottleneck of digital communication system more and more.

The serial interface has gradually replaced the parallel interface and has become the mainstream high-speed interface because of its advantages such as fewer I/O pins, strong anti-interference ability, and no synchronization problems.

Among them, the serial interface consists of a transmitter and a receiver. The transmitter is used to convert the low-speed parallel signal into a high-speed serial signal, and then send it to the channel. After the receiver receives the signal, it uses the clock data restorer to recover the clock. , and then retime and sample the input signal to finally recover the signal from the emitter.

Due to channel non-idealities and the continuous increase in data rates, factors such as skin effect, discontinuity in transmission line impedance, and dielectric loss, the transmitted data is severely distorted, resulting in inter-symbol crosstalk. Then, the opening degree of the eye diagram of the signal received by the receiving end often cannot meet the system performance index, and the original signal cannot be restored, which increases the bit error rate. The inventor found that an important measure to solve this problem is to use equalization technology to compensate for the non-ideal characteristics of the channel and to expand the bandwidth of the channel.

The Decision Feedback Equalizer (DFE) is an important equalization structure at the receiving end. The input is an analog quantity and the output is a digital quantity. It has the advantage of only amplifying the signal without amplifying the noise.

As PAM-4 (Four-level Pluse Amplitude Modulation, fourth-generation pulse amplitude modulation) modulation replaces NRZ (Non-Retrun to Zero, non-return to zero) modulation and becomes the mainstream modulation method of serial ports, the design of DFE also faces new challenge. Specifically, the loop delay of the DFE must be controlled within 1UI (Unit Interval, unit symbol length) to ensure a correct timing relationship.

However, the balanced tap of the DFE in the traditional structure needs to receive three channels of data, and the load of the summer is large, which limits the improvement of data, and the bandwidth of the traditional sampling decision device is limited, so it is difficult to sample and decide the high-speed data stream.

SUMMARY OF THE INVENTION

In view of this, in order to solve the above problems, the present invention provides a decision feedback equalizer and a PAM-4 receiver, and the technical solutions are as follows:

A decision feedback equalizer, the decision feedback equalizer comprises: first to fourth groups of sampling deciders; each group of sampling deciders is composed of three-way sampling deciders; the first to fourth groups The sampling decider is driven by a four-phase clock;

In any group of sampling judging devices, the main tap inputs of the three-way sampling judging device are used to respectively correspond to the three-way data after receiving the level shift;

The outputs of the three-way sampling deciders in the first group of sampling deciders correspond to the inputs of the equalization taps of the three-way sampling deciders in the second group of sampling deciders respectively;

The outputs of the three-channel sampling decision devices in the second group of sampling decision devices correspond to the inputs of the equalization taps of the three-channel sampling decision devices in the first group of sampling decision devices;

The outputs of the three-way sampling deciders in the third group of sampling deciders respectively correspond to the inputs of the equalization taps of the three-way sampling deciders in the fourth group of sampling deciders;

The outputs of the three-channel sampling decision devices in the fourth group of sampling decision devices correspond to the inputs of the equalization taps of the three-channel sampling decision devices in the third group of sampling decision devices;

The first group of sampling deciders and the second group of sampling deciders are a data sampling decider group, and the third group of sampling deciders and the fourth group of sampling deciders are an edge sampling decider group.

Preferably, in the above decision feedback equalizer, the first to fourth groups of sampling deciders are driven by four-phase clocks, including:

The first group of sampling arbiters is driven by a first clock signal, the third group of sampling arbiters is driven by a second clock signal, the second group of sampling arbiters is driven by a third clock signal, and the fourth group of sampling arbiters is driven by a third clock signal. the sampling decider is driven by the fourth clock signal;

Wherein, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are four-phase clocks, and the phases are sequentially different by 90°.

Preferably, in the above decision feedback equalizer, the sampling decider includes: a summer, a sample and hold module, and a latch;

Wherein, the main tap input of the summer is used to correspond to one of the three channels of data after receiving the level-shift;

The equalized tap input of the summer is used to receive the output of the corresponding sampling arbiter in the corresponding other group of sampling arbiters;

The first equalization strength control end of the summer is used for receiving the first control signal;

The second equalization strength control end of the summer is used for receiving the second control signal;

The first input end of the sample and hold module is connected to the first output end of the summer, and the second input end of the sample and hold module is connected to the second output end of the summer;

The voltage terminal of the sample and hold module is used for receiving a voltage signal;

The first control terminal of the sample and hold module is used for receiving the fifth clock signal, the second control terminal is used for receiving the sixth clock signal, and the third control terminal is used for receiving the seventh clock signal;

The voltage terminal of the latch is used for receiving the voltage signal;

The first input end of the latch is connected to the first output end of the sample and hold module, and the second input end of the latch is connected to the second output end of the sample and hold module;

The control end of the latch is used for receiving the fifth clock signal;

The first output end and the second output end of the latch are used as the output ends of the sampling decider;

Wherein, the fifth clock signal and the sixth clock signal are used to control the working state of the sample and hold module, and then control the working state of the latch;

The seventh clock signal is used to control the sampling speed of the sample and hold module.

Preferably, in the above decision feedback equalizer, the summer includes: first to sixth field effect transistors;

The grid of the first field effect transistor and the grid of the second field effect transistor are used to correspond to one channel of data in the three channels of data after receiving level shifting;

The first electrode end of the first field effect transistor is connected with the first electrode end of the second field effect transistor, and the connection node is connected with the second electrode end of the fifth field effect transistor;

The first electrode terminal of the fifth field effect transistor is grounded, and the grid is used for receiving the first control signal;

The second electrode terminal of the second field effect transistor is connected to the second electrode terminal of the third field effect transistor, and the connection node is used as the second output terminal of the summer;

the second electrode terminal of the first field effect transistor is connected to the second electrode terminal of the fourth field effect transistor, and the connection node is used as the first output terminal of the summer;

The grid of the third field effect transistor and the grid of the fourth field effect transistor are used to receive the outputs of the corresponding sampling deciders in the corresponding other groups of sampling deciders;

The first electrode end of the third field effect transistor is connected with the first electrode end of the fourth field effect transistor, and the connection node is connected with the second electrode end of the sixth field effect transistor;

The first electrode terminal of the sixth field effect transistor is grounded, and the gate is used for receiving the second control signal.

Preferably, in the above decision feedback equalizer, the first to sixth field effect transistors are all N-type field effect transistors.

Preferably, in the above decision feedback equalizer, the sample and hold module includes: seventh to twelfth field effect transistors;

The first electrode end of the seventh FET, the first electrode end of the eighth FET, the first electrode end of the ninth FET, and the first electrode end of the tenth FET an extreme connection, and a connection node is used to receive the voltage signal;

The gate of the eighth field effect transistor is connected to the gate of the ninth field effect transistor, and the connection node is used for receiving the fifth clock signal;

The second electrode terminal of the seventh field effect transistor is connected to the second electrode terminal of the eighth field effect transistor, and the connection node is used as the second output terminal of the sample and hold module, and the connection node is connected to the the second electrode terminal of the eleventh field effect transistor is connected;

The second electrode terminal of the ninth field effect transistor is connected to the second electrode terminal of the tenth field effect transistor, and the connection node is used as the first output terminal of the sample and hold module, and the connection node is connected to the The second electrode terminal of the twelfth field effect transistor is connected;

the gate of the eleventh field effect transistor is connected to the gate of the twelfth field effect transistor, and the connection node is used for receiving the sixth clock signal;

the gate of the seventh field effect transistor and the gate of the tenth field effect transistor are used for receiving the seventh clock signal;

The first electrode end of the eleventh field effect transistor is used as the first input end of the sample and hold module;

The first electrode end of the twelfth field effect transistor is used as the second input end of the sample and hold module.

Preferably, in the above decision feedback equalizer, the seventh to tenth field effect transistors are P-type field effect transistors;

The eleventh field effect transistor and the twelfth field effect transistor are N-type field effect transistors.

Preferably, in the above decision feedback equalizer, the latch includes: thirteenth to seventeenth field effect transistors;

The first electrode terminal of the thirteenth field effect transistor is connected to the first electrode terminal of the fourteenth field effect transistor, and the connection node is used for receiving the voltage signal;

The gate of the thirteenth field effect transistor is connected to the gate of the fifteenth field effect transistor, and the connection node is used as the second output end of the latch;

the second electrode terminal of the thirteenth field effect transistor is connected to the second electrode terminal of the fifteenth field effect transistor, and the connection node is used as the first output terminal of the latch;

The gate of the fourteenth field effect transistor is connected to the gate of the sixteenth field effect transistor, and the connection node also serves as the first output end of the latch;

The second electrode terminal of the fourteenth field effect transistor is connected to the second electrode terminal of the sixteenth field effect transistor, and the connection node also serves as the second output terminal of the latch;

The first electrode terminal of the fifteenth field effect transistor is connected to the first electrode terminal of the sixteenth field effect transistor, and the connection node is connected to the second electrode terminal of the seventeenth field effect transistor;

The first electrode terminal of the seventeenth field effect transistor is grounded, and the gate is used for receiving the fifth clock signal.

Preferably, in the above decision feedback equalizer, the thirteenth field effect transistor and the fourteenth field effect transistor are P-type field effect transistors;

The fifteenth to seventeenth field effect transistors are N-type field effect transistors.

A PAM-4 receiver, the PAM-4 receiver comprising the decision feedback equalizer described in any one of the above.

Compared with the prior art, the beneficial effects realized by the present invention are:

A decision feedback equalizer provided by the present invention, on the one hand, reduces the parasitic capacitance by reducing the number of interfaces of equalizing taps, and reduces the settling time of the summer; The amplitude reduces the delay caused by the sampling arbiter; and further reduces the loop delay of the DFE from two aspects, and solves the problem of tight timing margin.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without creative work.

Fig. 1 is the principle schematic diagram of the traditional decision feedback equalizer;

2 is a schematic diagram of the circuit structure of a data sampling decider in a traditional decision feedback equalizer;

3 is a schematic diagram of the principle of a decision feedback equalizer provided by an embodiment of the present invention;

4 is a schematic diagram of a circuit structure of a sampling decision device provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of signal waveforms with and without the introduction of a seventh clock signal according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the process of invention and creation of the present application, the inventor found that the traditional DFE continues the structure of NRZ modulation, and the half-speed two-tap DFE is used as an example for illustration.

Referring to FIG. 1 , FIG. 1 is a schematic diagram of the principle of a conventional decision feedback equalizer.

The decision feedback equalizer is composed of three-way sampling deciders (corresponding to the three-way data DH/D0/DL after level shifting), each of which is driven by a four-phase clock CK0/CK90/CK180/CK270.

Among them, VA0-VB0-VC0 is the three-bit thermometer code output by the three-way sampling decision device driven by CK0; VA0 corresponds to data DH, VB0 corresponds to data D0, and VC0 corresponds to data DL.

VA90-VB90-VC90 is a three-bit thermometer code output by a three-way sampling decision device driven by CK90; VA90 corresponds to data DH, VB90 corresponds to data D0, and VC90 corresponds to data DL.

VA180-VB180-VC180 is a three-bit thermometer code output by a three-way sampling decision device driven by CK180; VA180 corresponds to data DH, VB180 corresponds to data D0, and VC180 corresponds to data DL.

VA270-VB270-VC270 is a three-bit thermometer code output by a three-way sampling decision device driven by CK270; VA270 corresponds to data DH, VB270 corresponds to data D0, and VC270 corresponds to data DL.

Because the decision feedback equalizer adopts a half-speed structure, the clock frequency is half of the baud rate, so the CK0 and CK10 clocks correspond to the sampling decision of adjacent two-bit data, and CK90 and CK270 correspond to the sampling of the transition edge (edge).

Cross-coupling the data sampling decider driven by CK0 and CK180, and cross-coupling the edge sampling decider driven by CK90 and CK270, that is, the respective outputs are the inputs of each other's equalization taps, so that the current data can be subtracted from the weighted upper The function of one bit of data is to realize a two-tap decision feedback equalizer.

Referring to FIG. 2, FIG. 2 is a schematic diagram of a circuit structure of a data sampling decider in a conventional decision feedback equalizer.

Take the data sampling decider corresponding to VA0 as an example for description, which is composed of a summer and a comparator.

The summer is used to subtract the decision result (VA180/VB180/VC180) of the weighted last bit of data from the current data DH to realize equalization operation.

The current data DH is the main tap data, the judgment result of the previous data is equalization tap data, and the weight coefficient of the equalization tap is determined by the ratio of the tail current controlled by Vbm and Vbp.

The comparator determines the result of the given level according to the output of the summer. If Vxp>Vxn, then VA0P>VA0N, otherwise, VA0P<VA0N.

Based on the decision feedback equalizer shown in Figure 1 and Figure 2, the inventor found that in order to ensure the correct timing relationship in the DFE, the weighted summation of the current data and the previous data must be completed before the next sampling phase. That is, the loop delay of the DFE must be controlled within 1UI, which is the main challenge that tells the DFE design.

Among them, the inventor found that the main factors affecting the DFE loop delay are the settling time of the summer and the clock data delay of the comparator.

In the traditional decision feedback equalizer structure shown in Figure 1, the three-digit thermometer code obtained from the previous data decision needs to be returned to the summer. Therefore, the equalization tap requires three interfaces, which greatly increases the summation The load capacitance of the device increases the settling time.

The clock data delay of the comparator is mainly affected by the bandwidth and gain of the sampling stage. The wider the bandwidth, the faster the sampling speed, and the higher the gain. The higher the signal amplitude at the end of sampling, the faster the decision speed.

Increasing the bandwidth and gain can reduce the delay, but the bandwidth and gain restrict each other, and it is difficult to effectively optimize.

Based on this, the present invention provides a new type of decision feedback equalizer. On the one hand, the parasitic capacitance is reduced by reducing the number of interfaces of equalization taps, and the settling time of the summer is reduced; The input amplitude of the latch reduces the delay caused by the sampling arbiter; and further reduces the loop delay of the DFE from two aspects, and solves the problem of tight timing margin.

In order to make the above objects, features and advantages of the present invention more clearly understood, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

Referring to FIG. 3 , FIG. 3 is a schematic diagram of the principle of a decision feedback equalizer provided by an embodiment of the present invention.

The decision feedback equalizer includes: the first to fourth groups of sampling deciders; each group of sampling deciders is composed of three-way sampling deciders; the first to fourth groups of sampling deciders are composed of four-phase clocks Drive CK0/CK90/CK180/CK270;

In any group of sampling decision devices, the main tap inputs of the three-way sampling decision devices are used to respectively correspond to the three channels of data DH/D0/DL after receiving level shift;

The outputs of the three-way sampling deciders in the first group of sampling deciders correspond to the inputs of the equalization taps of the three-way sampling deciders in the second group of sampling deciders respectively;

The outputs of the three-channel sampling decision devices in the second group of sampling decision devices correspond to the inputs of the equalization taps of the three-channel sampling decision devices in the first group of sampling decision devices;

The outputs of the three-way sampling deciders in the third group of sampling deciders respectively correspond to the inputs of the equalization taps of the three-way sampling deciders in the fourth group of sampling deciders;

The outputs of the three-channel sampling decision devices in the fourth group of sampling decision devices correspond to the inputs of the equalization taps of the three-channel sampling decision devices in the third group of sampling decision devices;

The first group of sampling deciders and the second group of sampling deciders are a data sampling decider group, and the third group of sampling deciders and the fourth group of sampling deciders are an edge sampling decider group.

Wherein, the first to fourth groups of sampling deciders are driven by four-phase clocks, including:

The first group of sampling deciders is driven by the first clock signal CK0, the third group of sampling deciders is driven by the second clock signal CK90, the second group of sampling deciders is driven by the third clock signal CK180, the The fourth group of sampling deciders is driven by the fourth clock signal CK270;

Wherein, the first clock signal CK0, the second clock signal CK90, the third clock signal CK180 and the fourth clock signal CK270 are four-phase clocks, and the phases are sequentially shifted by 90°.

In this embodiment, as shown in FIG. 1 , whether it is a data sampling decider group or an edge sampling decider group, in each group of sampling deciders, the main tap of the first sampling decider is used for receiving level shifting The first channel of data DH after the bit, the main tap of the second channel of the sampling decision device is used to receive the second channel of data D0 after the level shift, and the main tap of the third channel of the sampling decision device is used to receive the level shift. The third data DL after the bit;

Among them, VA0-VB0-VC0 is the three-bit thermometer code output by the three-way sampling decision device driven by CK0; VA0 corresponds to data DH, VB0 corresponds to data D0, and VC0 corresponds to data DL.

VA90-VB90-VC90 is a three-bit thermometer code output by a three-way sampling decision device driven by CK90; VA90 corresponds to data DH, VB90 corresponds to data D0, and VC90 corresponds to data DL.

VA180-VB180-VC180 is a three-bit thermometer code output by a three-way sampling decision device driven by CK180; VA180 corresponds to data DH, VB180 corresponds to data D0, and VC180 corresponds to data DL.

VA270-VB270-VC270 is a three-bit thermometer code output by a three-way sampling decision device driven by CK270; VA270 corresponds to data DH, VB270 corresponds to data D0, and VC270 corresponds to data DL.

Further, as shown in Figure 3, the decision result of the equalization taps returned to each sampling arbiter is a single path instead of the three paths shown in Figure 1, so only one equalization tap is required for each sampling arbiter, and then The parasitic capacitance is greatly reduced, and the settling time required for the summer in the sampling arbiter is reduced.

Optionally, in another embodiment of the present invention, referring to FIG. 4 , FIG. 4 is a schematic diagram of a circuit structure of a sampling decider according to an embodiment of the present invention.

The sampling decider includes: a summer, a sampling and holding module and a latch;

Wherein, the input of the main tap of the summer is used to correspond to one of the three channels of data after receiving level shift; for example, the received data DH.

The equalized tap input of the summer is used to receive the output of the corresponding sample decider in the other group of sample deciders; for example, the VA180 output.

The first equalization strength control end of the summer is used for receiving the first control signal Vbm;

The second equalization strength control end of the summer is used for receiving the second control signal Vbp;

The first input end of the sample and hold module is connected to the first output end of the summer, and the second input end of the sample and hold module is connected to the second output end of the summer;

The voltage terminal of the sample and hold module is used for receiving the voltage signal VDD;

The first control end of the sample and hold module is used for receiving the fifth clock signal φ ₁ , the second control end is used for receiving the sixth clock signal φ ₂ , and the third control end is used for receiving the seventh clock signal φ ₃ ;

the voltage terminal of the latch is used for receiving the voltage signal VDD;

The first input end of the latch is connected to the first output end of the sample and hold module, and the second input end of the latch is connected to the second output end of the sample and hold module;

the control end of the latch is used for receiving the fifth clock signal φ ₁ ;

The first output end VA0p and the second output end VA0n of the latch are used as the output ends of the sampling decider;

Wherein, the fifth clock signal φ ₁ and the sixth clock signal φ ₂ are used to control the working state of the sample and hold module, and then control the working state of the latch;

The seventh clock signal φ ₃ is used to control the sampling speed of the sampling and holding module.

Optionally, as shown in FIG. 4 , the summer includes: first to sixth field effect transistors;

The gate of the first field effect transistor M1 and the gate of the second field effect transistor M2 are used to correspond to one channel of data DH in the three channels of data after receiving level shifting;

The first electrode terminal of the first field effect transistor M1 is connected to the first electrode terminal of the second field effect transistor M2, and the connection node is connected to the second electrode terminal of the fifth field effect transistor M5;

The first electrode terminal of the fifth field effect transistor M5 is grounded, and the gate is used for receiving the first control signal Vbm;

The second electrode terminal of the second field effect transistor M2 is connected to the second electrode terminal of the third field effect transistor M3, and the connection node is used as the second output terminal Vxn of the summer;

The second electrode terminal of the first field effect transistor M1 is connected to the second electrode terminal of the fourth field effect transistor M4, and the connection node is used as the first output terminal Vxp of the summer;

The gate of the third field effect transistor M3 and the gate of the fourth field effect transistor M4 are used to receive the output VA180 of the corresponding sampling decider in the other groups of sampling deciders;

The first electrode terminal of the third field effect transistor M3 is connected to the first electrode terminal of the fourth field effect transistor M4, and the connection node is connected to the second electrode terminal of the sixth field effect transistor M6;

The first electrode terminal of the sixth field effect transistor M6 is grounded, and the gate is used for receiving the second control signal Vbp.

Wherein, the first to sixth field effect transistors are all N-type field effect transistors.

Optionally, as shown in FIG. 4 , the sample-and-hold module includes: seventh to twelfth field effect transistors;

The first electrode end of the seventh field effect transistor M7, the first electrode end of the eighth field effect transistor M8, the first electrode end of the ninth field effect transistor M9, and the tenth field effect transistor M10 The first electrode terminal of is connected, and the connection node is used for receiving the voltage signal VDD;

the gate of the eighth field effect transistor M8 is connected to the gate of the ninth field effect transistor M9, and the connection node is used for receiving the fifth clock signal φ ₁ ;

The second electrode terminal of the seventh field effect transistor M7 is connected to the second electrode terminal of the eighth field effect transistor M8, and the connection node is used as the second output end of the sample and hold module, and the connection node is connected to the second output terminal of the sample and hold module. the second electrode terminal of the eleventh field effect transistor M11 is connected;

The second electrode terminal of the ninth field effect transistor M9 is connected to the second electrode terminal of the tenth field effect transistor M10, and the connection node is used as the first output end of the sample-and-hold module, and the connection node is connected to the first output terminal of the sample and hold module. the second electrode terminal of the twelfth field effect transistor M12 is connected;

the gate of the eleventh field effect transistor M11 is connected to the gate of the twelfth field effect transistor M12, and the connection node is used for receiving the sixth clock signal φ ₂ ;

The gate of the seventh field effect transistor M7 and the gate of the tenth field effect transistor M10 are used to receive the seventh clock signal φ ₃ ;

The first electrode terminal of the eleventh field effect transistor M11 is used as the first input terminal of the sample and hold module;

The first electrode terminal of the twelfth field effect transistor M12 serves as the second input terminal of the sample and hold module.

Wherein, the seventh to tenth field effect transistors are P-type field effect transistors;

The eleventh field effect transistor and the twelfth field effect transistor are N-type field effect transistors.

Optionally, as shown in FIG. 4 , the latch includes: thirteenth to seventeenth field effect transistors;

The first electrode terminal of the thirteenth field effect transistor M13 is connected to the first electrode terminal of the fourteenth field effect transistor M14, and the connection node is used for receiving the voltage signal VDD;

The gate of the thirteenth field effect transistor M13 is connected to the gate of the fifteenth field effect transistor M15, and the connection node is used as the second output end of the latch;

The second electrode terminal of the thirteenth field effect transistor M13 is connected to the second electrode terminal of the fifteenth field effect transistor M15, and the connection node is used as the first output terminal of the latch;

The gate of the fourteenth field effect transistor M14 is connected to the gate of the sixteenth field effect transistor M16, and the connection node also serves as the first output end of the latch;

The second electrode terminal of the fourteenth field effect transistor M14 is connected to the second electrode terminal of the sixteenth field effect transistor M16, and the connection node also serves as the second output terminal of the latch;

The first electrode terminal of the fifteenth field effect transistor M15 is connected to the first electrode terminal of the sixteenth field effect transistor M16, and the connection node is connected to the second electrode terminal of the seventeenth field effect transistor M17 ;

The first electrode terminal of the seventeenth field effect transistor M17 is grounded, and the gate is used for receiving the fifth clock signal φ ₁ .

Wherein, the thirteenth field effect transistor and the fourteenth field effect transistor are P-type field effect transistors;

The fifteenth to seventeenth field effect transistors are N-type field effect transistors.

It should be noted that the schematic diagram of the circuit structure of the sampling decider shown in FIG. 4 is described by taking the sampling decider corresponding to VA0 as an example.

As shown in Figure 4, in the summer, the main tap data is level-shifted data DH, the equalization tap data has only one channel of VA180, and the equalization strength is determined by the difference between the first control signal Vbm and the tail current controlled by the second control signal Vbp. than decide.

When the fifth clock signal φ ₁ is at a low level and the sixth clock signal φ ₂ is at a high level, the eighth field effect transistor M8 and the ninth field effect transistor M9, the eleventh field effect transistor M11 and the twelfth field effect transistor The tube M12 is turned on, the latch is in a non-working state, and it is a sampling state at this time, and the difference between the data DH and the data VA180 is amplified and sent to the output end.

When the fifth clock signal φ ₁ is at a high level and the sixth clock signal φ ₂ is at a low level, the eighth field effect transistor M8 and the ninth field effect transistor M9, the eleventh field effect transistor M11 and the twelfth field effect transistor The tube M12 is turned off, the latch is in a working state, and it is a judgment state at this time.

The cross-coupling inside the latch is a positive feedback loop. If the difference between DH and VA180 is greater than 0 at the end of the sampling period, the positive feedback will pull VOP up to VDD and pull VON down to ground; otherwise, VOP will be pulled down In this case, pull down VON to VDD for correct level decision.

It can be seen from the above description that a sample and hold module is added to the sampling decision device, and the eleventh field effect transistor M11 and the twelfth field effect transistor M12 control its own working state. Then, first, in the decision stage, the first field effect transistor M1 and the second field effect transistor M2 are separated from the output node by the eleventh field effect transistor M11 and the twelfth field effect transistor M12, and the parasitic capacitance of the first field effect transistor M1 and the second field effect transistor M2 does not affect the latching Therefore, the large-sized first field effect transistor M1 and the second field effect transistor M2 can be selected to improve the gain.

Secondly, the control clock is full swing, so the small-sized eleventh field effect transistor M11 and the twelfth field effect transistor M12 can well control the transition of the working state of the sample and hold module, reduce the parasitic capacitance at the output end, and improve the bandwidth, thereby increasing the sampling speed.

Finally, the kickback noise of the latch is separated by the eleventh field effect transistor M11 and the twelfth field effect transistor M12, which reduces the influence of noise.

Further, a seventh clock signal φ ₃ is introduced in the sampling stage, thereby expanding the bandwidth and increasing the sampling speed. The fifth clock signal φ ₁ and the sixth clock signal φ ₂ are a pair of half-speed differential clocks, and the seventh clock signal φ ₃ is the fifth clock signal φ ₁ and the clock signal with a difference of 90°, which are respectively inverted and passed through NAND gate is generated. The seventh clock signal φ ₃ is a 25% duty cycle clock that differs from the fifth clock signal φ ₁ by a delay of about two inverters, 2T _inv .

Referring to FIG. 5 , FIG. 5 is a schematic diagram of signal waveforms in which a seventh clock signal is introduced and a seventh clock signal is not introduced according to an embodiment of the present invention.

The sampling stage can be divided into two stages: Invalid Tracking and Valid Tracking.

The period from the falling edge of the fifth clock signal φ ₁ to the transition of the summer output signals Vxp and Vxn to the 0V crossover point is an invalid sampling stage, because this period of signal has already been determined by another sampling decision driven by an inverted clock. sampled.

The period from the transition of the summer output signals Vxp and Vxn to 0V to the rising edge of the fifth clock signal φ ₁ is the valid sampling phase.

When the fifth clock signal φ ₁ is at a low level, the latch is in an inactive state, and the sampling phase begins.

If the seventh clock signal φ ₃ is not used, the effective sampling stage is divided into two stages t _r1 and t _a1 .

t _r1 refers to the time required from the transition of Vxp and Vxn to 0V to the transition of the outputs VA0P and VA0N to 0V, and _{t a1} refers to the time required from the transition of the output to 0V to the rising edge of the fifth clock signal φ1.

The sampling phase does not really start until the end of t _r1 . Reducing t _r1 means that the output signal can reach the 0V crossover point faster, thereby increasing the sampling speed and reducing the DFE loop delay.

If the seventh clock signal φ ₃ is introduced into the sampling decider, after the falling edge of the fifth clock signal φ ₁ is delayed by 2T _inv , the seventh clock signal φ ₃ has a falling edge. At this time, the seventh field effect transistor M7 and the tenth field The effect transistor M10 is turned on, the output impedance is reduced, the bandwidth is expanded, and the speed of the output jumping to 0V is accelerated, t _r1 is reduced to t _r2 , and t _a1 is increased to t _a2 .

t _a2 can be further divided into two parts: t _1a2 and t _2a2 . In the t _1a2 stage, the seventh clock signal φ ₃ remains at a low level to provide a wide bandwidth to improve the working speed. In the t _2a2 stage, the seventh clock signal φ ₃ becomes a high level, the seventh FET M7 and the tenth FET M10 are turned off, the output impedance increases, and the gain is improved.

At the end of the sampling phase, the output amplitude increases from A1 to A2, which increases the input amplitude of the latch, thereby reducing the time required for latching.

It can be seen from the above description that on the one hand, the decision feedback equalizer reduces the parasitic capacitance and the settling time of the summer by reducing the number of interfaces of equalization taps; on the other hand, it improves the bandwidth of the sampling stage and increases the input amplitude of the latch. The delay caused by the sampling decider is reduced; the loop delay of the DFE is reduced comprehensively from two aspects, and the problem of tight timing margin is solved.

Further, based on all the above embodiments of the present invention, another embodiment of the present invention further provides a PAM-4 receiver, where the PAM-4 receiver includes the decision feedback equalizer described in the above embodiments.

A decision feedback equalizer and a PAM-4 receiver provided by the present invention have been introduced in detail above. In this paper, specific examples are used to illustrate the principles and implementations of the present invention. The descriptions of the above embodiments are only for help. Understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. In summary, the content of this specification does not It should be understood as a limitation of the present invention.

It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. For the same and similar parts among the various embodiments, refer to each other Can. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

It should also be noted that in this document, relational terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply those entities or operations There is no such actual relationship or order between them. Furthermore, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article, or device of a list of elements is included, inherent to, or is also included for, those processes. , method, article or device inherent elements. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

The above description of the disclosed embodiments enables any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A decision feedback equalizer, characterized in that the decision feedback equalizer comprises: the first to fourth groups of sampling deciders; each group of sampling deciders is composed of three-way sampling deciders; One to the fourth group of sampling deciders are driven by four-phase clocks; In any group of sampling judging devices, the main tap inputs of the three-way sampling judging device are used to respectively correspond to the three-way data after receiving the level shift; The outputs of the three-way sampling deciders in the first group of sampling deciders correspond to the inputs of the equalization taps of the three-way sampling deciders in the second group of sampling deciders respectively; The outputs of the three-channel sampling decision devices in the second group of sampling decision devices correspond to the inputs of the equalization taps of the three-channel sampling decision devices in the first group of sampling decision devices; The outputs of the three-way sampling deciders in the third group of sampling deciders respectively correspond to the inputs of the equalization taps of the three-way sampling deciders in the fourth group of sampling deciders; The outputs of the three-channel sampling decision devices in the fourth group of sampling decision devices correspond to the inputs of the equalization taps of the three-channel sampling decision devices in the third group of sampling decision devices; The first group of sampling deciders and the second group of sampling deciders are a data sampling decider group, and the third group of sampling deciders and the fourth group of sampling deciders are an edge sampling decider group. 2. The decision feedback equalizer according to claim 1, wherein the first to fourth groups of sampling deciders are driven by a four-phase clock, comprising: The first group of sampling arbiters is driven by a first clock signal, the third group of sampling arbiters is driven by a second clock signal, the second group of sampling arbiters is driven by a third clock signal, and the fourth group of sampling arbiters is driven by a third clock signal. the sampling decider is driven by the fourth clock signal; Wherein, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are four-phase clocks, and the phases are sequentially different by 90°. 3. The decision feedback equalizer according to claim 1, wherein the sampling decision device comprises: a summer, a sample and hold module and a latch; Wherein, the main tap input of the summer is used to correspond to one of the three channels of data after receiving the level-shift; The equalized tap input of the summer is used to receive the output of the corresponding sampling arbiter in the corresponding other group of sampling arbiters; The first equalization strength control end of the summer is used for receiving the first control signal; The second equalization strength control end of the summer is used for receiving the second control signal; The first input end of the sample and hold module is connected to the first output end of the summer, and the second input end of the sample and hold module is connected to the second output end of the summer; The voltage terminal of the sample and hold module is used for receiving a voltage signal; The first control terminal of the sample and hold module is used for receiving the fifth clock signal, the second control terminal is used for receiving the sixth clock signal, and the third control terminal is used for receiving the seventh clock signal; The voltage terminal of the latch is used for receiving the voltage signal; The first input end of the latch is connected to the first output end of the sample and hold module, and the second input end of the latch is connected to the second output end of the sample and hold module; The control end of the latch is used for receiving the fifth clock signal; The first output end and the second output end of the latch are used as the output ends of the sampling decider; Wherein, the fifth clock signal and the sixth clock signal are used to control the working state of the sample and hold module, and then control the working state of the latch; The seventh clock signal is used to control the sampling speed of the sample and hold module. 4. The decision feedback equalizer according to claim 3, wherein the summer comprises: first to sixth field effect transistors; The grid of the first field effect transistor and the grid of the second field effect transistor are used to correspond to one channel of data in the three channels of data after receiving level shifting; The first electrode end of the first field effect transistor is connected with the first electrode end of the second field effect transistor, and the connection node is connected with the second electrode end of the fifth field effect transistor; The first electrode terminal of the fifth field effect transistor is grounded, and the grid is used for receiving the first control signal; The second electrode terminal of the second field effect transistor is connected to the second electrode terminal of the third field effect transistor, and the connection node is used as the second output terminal of the summer; the second electrode terminal of the first field effect transistor is connected to the second electrode terminal of the fourth field effect transistor, and the connection node is used as the first output terminal of the summer; The grid of the third field effect transistor and the grid of the fourth field effect transistor are used to receive the outputs of the corresponding sampling deciders in the corresponding other groups of sampling deciders; The first electrode end of the third field effect transistor is connected with the first electrode end of the fourth field effect transistor, and the connection node is connected with the second electrode end of the sixth field effect transistor; The first electrode terminal of the sixth field effect transistor is grounded, and the gate is used for receiving the second control signal. 5 . The decision feedback equalizer of claim 4 , wherein the first to sixth field effect transistors are all N-type field effect transistors. 6 . 6. The decision feedback equalizer according to claim 3, wherein the sample and hold module comprises: seventh to twelfth field effect transistors; The first electrode end of the seventh FET, the first electrode end of the eighth FET, the first electrode end of the ninth FET, and the first electrode end of the tenth FET an extreme connection, and a connection node is used to receive the voltage signal; The gate of the eighth field effect transistor is connected to the gate of the ninth field effect transistor, and the connection node is used for receiving the fifth clock signal; The second electrode terminal of the seventh field effect transistor is connected to the second electrode terminal of the eighth field effect transistor, and the connection node is used as the second output terminal of the sample and hold module, and the connection node is connected to the the second electrode terminal of the eleventh field effect transistor is connected; The second electrode terminal of the ninth field effect transistor is connected to the second electrode terminal of the tenth field effect transistor, and the connection node is used as the first output terminal of the sample and hold module, and the connection node is connected to the The second electrode terminal of the twelfth field effect transistor is connected; the gate of the eleventh field effect transistor is connected to the gate of the twelfth field effect transistor, and the connection node is used for receiving the sixth clock signal; the gate of the seventh field effect transistor and the gate of the tenth field effect transistor are used for receiving the seventh clock signal; The first electrode end of the eleventh field effect transistor is used as the first input end of the sample and hold module; The first electrode end of the twelfth field effect transistor is used as the second input end of the sample and hold module. 7. The decision feedback equalizer according to claim 6, wherein the seventh to tenth field effect transistors are P-type field effect transistors; The eleventh field effect transistor and the twelfth field effect transistor are N-type field effect transistors. 8. The decision feedback equalizer according to claim 3, wherein the latch comprises: thirteenth to seventeenth field effect transistors; The first electrode terminal of the thirteenth field effect transistor is connected to the first electrode terminal of the fourteenth field effect transistor, and the connection node is used for receiving the voltage signal; The gate of the thirteenth field effect transistor is connected to the gate of the fifteenth field effect transistor, and the connection node is used as the second output end of the latch; the second electrode terminal of the thirteenth field effect transistor is connected to the second electrode terminal of the fifteenth field effect transistor, and the connection node is used as the first output terminal of the latch; the gate of the fourteenth field effect transistor is connected to the gate of the sixteenth field effect transistor, and the connection node also serves as the first output end of the latch; The second electrode terminal of the fourteenth field effect transistor is connected to the second electrode terminal of the sixteenth field effect transistor, and the connection node also serves as the second output terminal of the latch; The first electrode end of the fifteenth field effect transistor is connected with the first electrode end of the sixteenth field effect transistor, and the connection node is connected with the second electrode end of the seventeenth field effect transistor; The first electrode terminal of the seventeenth field effect transistor is grounded, and the gate is used for receiving the fifth clock signal. 9. The decision feedback equalizer according to claim 8, wherein the thirteenth field effect transistor and the fourteenth field effect transistor are P-type field effect transistors; The fifteenth to seventeenth field effect transistors are N-type field effect transistors. 10. A PAM-4 receiver, wherein the PAM-4 receiver comprises the decision feedback equalizer according to any one of claims 1-9.

Images