CN114334886A - Electron irradiation resistant MOSFET (metal-oxide-semiconductor field effect transistor) reinforced packaging structure - Google Patents
Electron irradiation resistant MOSFET (metal-oxide-semiconductor field effect transistor) reinforced packaging structure Download PDFInfo
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- CN114334886A CN114334886A CN202111575963.0A CN202111575963A CN114334886A CN 114334886 A CN114334886 A CN 114334886A CN 202111575963 A CN202111575963 A CN 202111575963A CN 114334886 A CN114334886 A CN 114334886A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
本发明提供了一种抗电子辐照的MOSFET加固封装结构，属于电子电力器件技术领域，具体包括：第一抗辐照导电片、第二抗辐照导电片和缓冲导电片；第一抗辐照导电片和第二抗辐照导电片覆盖MOSFET芯片；且第一抗辐照导电片和第二抗辐照导电片均为高Z材料；第一抗辐照导电片的一端通过缓冲导电片与MOSFET芯片上方的源极连接；第二抗辐照导电片的一端与MOSFET芯片下方的漏极连接；第一抗辐照导电片用于抵挡MOSFET芯片上方的电子辐照；第二抗辐照导电片用于抵挡MOSFET芯片下方的电子辐照。本发明实现了抗辐照性能、体积、重量乃至成本的折中。
The invention provides a MOSFET reinforced packaging structure resistant to electron irradiation, belonging to the technical field of electronic power devices, and specifically comprising: a first anti-radiation conductive sheet, a second anti-radiation conductive sheet and a buffer conductive sheet; a first anti-radiation conductive sheet The photoconductive sheet and the second anti-radiation conductive sheet cover the MOSFET chip; and the first anti-radiation conductive sheet and the second anti-radiation conductive sheet are both high-Z materials; one end of the first anti-radiation conductive sheet passes through the buffer conductive sheet It is connected to the source above the MOSFET chip; one end of the second anti-radiation conductive sheet is connected to the drain below the MOSFET chip; the first anti-radiation conductive sheet is used to resist the electron irradiation above the MOSFET chip; the second anti-radiation conductive sheet The conductive sheet is used to resist electron irradiation under the MOSFET chip. The present invention realizes the compromise between radiation resistance performance, volume, weight and even cost.
Description
Technical Field
The invention belongs to the technical field of electronic power devices, and particularly relates to an electron irradiation resistant MOSFET (metal oxide semiconductor field effect transistor) reinforced packaging structure.
Background
When a power semiconductor device such as a SiC MOSFET works under application conditions such as a space radiation environment, the working reliability of the device is affected by threats of high-energy electrons, heavy particles, gamma rays and the like. When the MOSFET device is irradiated by electrons, trapped charges and interface states are generated at the interface of a gate oxide layer of the device, so that the phenomena of threshold voltage drift, transconductance characteristic degradation and the like are caused, and the device is aged or even damaged. Therefore, the device is reinforced, and the capability of resisting electron irradiation of the device is improved, so that the device has important significance for reliable operation under the strong radiation working condition.
At present, the radiation-resistant reinforcement of the MOSFET device mainly focuses on the improvement of the chip body structure, thereby increasing the radiation-resistant capability of the chip and the device. However, the improvement of the chip body structure increases the process difficulty and the process cost. The radiation-resistant reinforcement of the MOSFET device from the packaging point of view has the advantage of simple processing technology, and therefore, the radiation-resistant reinforcement is an important research direction.
At present, researches for improving the radiation resistance of devices from the packaging angle are more in the field of electronic devices, for example, in patent documents 201110320158.3 and 201720208903.8, radiation resistance reinforcement of the devices is realized by combining radiation resistance materials and shells, but the problems that redundant materials are too much, the weight, the volume and the cost of the devices are increased, and the operation of the devices in space is not facilitated.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide an electron irradiation resistant MOSFET reinforcement packaging structure, aiming at solving the problem that the irradiation resistance reinforcement of the existing MOSFET chip is concentrated on the reconstruction of a chip body structure, which can increase the process difficulty and the process cost; and the radiation resistance of the MOSFET chip is improved from the packaging angle, so that the problems of excessive redundant radiation resistance materials, increased weight, volume and cost of the MOSFET chip exist.
In order to achieve the above object, the present invention provides an electron irradiation resistant MOSFET ruggedized package structure, comprising: the radiation-resistant conducting strip comprises a first radiation-resistant conducting strip, a second radiation-resistant conducting strip and a buffer conducting strip;
the first anti-radiation conducting strip and the second anti-radiation conducting strip cover the MOSFET chip; the areas of the first anti-radiation conducting strip and the second anti-radiation conducting strip are larger than that of the MOSFET chip; the first anti-radiation conducting strip and the second anti-radiation conducting strip are both made of high-Z materials (high atomic number materials);
a source electrode above the MOSFET chip is connected with one end of the first anti-radiation conducting strip through a buffer conducting strip; the lower part of the MOSFET chip is connected with one end of the second anti-radiation conducting strip through a drain electrode;
the first anti-radiation conducting strip is used for resisting electron radiation above the MOSFET chip; the second anti-radiation conductive sheet is used for resisting electron radiation below the MOSFET chip.
Preferably, one side of the first radiation-resistant conducting strip is connected with one side of the buffering conducting strip by adopting a solder; the other side of the buffering conducting strip is connected with the MOSFET chip by adopting solder; the buffer conducting strip is used for relieving the stress of the MOSFET chip and the solder.
Preferably, the buffer conductive sheet material is a molybdenum sheet with the thickness of 0.6mm-3 mm;
preferably, the package structure is reinforced to MOSFET against electron irradiation, further comprising: the power terminal comprises a third conducting strip, a fourth conducting strip, a fifth conducting strip and a power terminal;
one end of the fourth conducting strip is connected with the other end of the first anti-radiation conducting strip through solder, and the other end of the fourth conducting strip is connected with the power terminal and used for leading out a source electrode of the MOSFET chip;
the other end of the second anti-radiation conducting strip is connected with the power terminal through solder and used for leading out a drain electrode of the MOSFET chip;
one end of the third conducting strip is connected with the grid electrode of the MOSFET chip, and the other end of the third conducting strip is connected with the fifth conducting strip through solder and used for leading out the grid electrode of the MOSFET chip through the power terminal.
Preferably, an epoxy injection molding process is used to secure and protect the MOSFET ruggedized package structure.
Preferably, the first radiation resistant conducting strip, the second radiation resistant conducting strip and the third conducting strip are tungsten or tantalum and have the thickness of 0.2mm-2 mm;
preferably, the fourth conducting strip, the fifth conducting strip and the power terminal are made of copper materials.
Preferably, the MOSFET is a sipmosfet or SiCMOSFET.
Generally, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:
the area of the first anti-radiation conducting strip and the area of the second anti-radiation conducting strip are larger than that of the MOSFET chip, the first anti-radiation conducting strip and the second anti-radiation conducting strip can be closely attached to the MOSFET chip and can resist the electron radiation of about 90% of the outside, and meanwhile, redundant metal is less, so that the volume and the weight of the whole MOSFET reinforced packaging structure are smaller after being combined with the MOSFET chip, and the radiation resistance, the volume, the weight and the cost are compromised; meanwhile, the existing mature process is adopted to finish the manufacturing, and the process difficulty is not increased.
In the invention, a second anti-radiation conducting strip is connected with a power terminal to lead out a drain electrode of the MOSFET chip; the grid electrode is led out through the conducting strip and the power terminal, and the source electrode is led out through the fourth conducting strip and the power terminal, so that a bonding wire in a traditional packaging structure is eliminated, parasitic inductance is reduced, the problems of voltage overshoot caused by the parasitic inductance and electromagnetic interference under a high-frequency working condition when the MOSFET chip is switched off are effectively reduced, and the advantage of high switching speed of the existing silicon carbide device is favorably exerted.
The fourth conducting strip, the fifth conducting strip and the power terminal are all made of copper materials, so that the radiation resistance of the MOSFET chip is not negatively affected, and meanwhile, the weight of the MOSFET chip is reduced due to the adoption of the copper materials.
Drawings
Fig. 1 is a schematic diagram of an electron irradiation resistant MOSFET ruggedized package structure provided by an embodiment of the invention;
fig. 2 is a schematic structural diagram of a conventional bond wire-based SiC MOSFET device provided by an embodiment of the present invention;
FIG. 3 is a three-dimensional schematic diagram of an electron irradiation resistant MOSFET ruggedized package structure provided by an embodiment of the present invention;
FIG. 4 is an anti-irradiation experimental result of a traditional bonding wire-based SiC MOSFET device and an anti-electron irradiation MOSFET reinforced packaging structure SiC MOSFET device;
the same reference numbers will be used throughout the drawings to refer to the same or like elements or structures, wherein:
1-MOSFET chip; 2-buffering the conducting strip; 3-a first radiation-resistant conductive sheet; 4-a second radiation resistant conductive sheet; 5-a third conductive sheet; 6-a fourth conductive sheet; 7-a fifth conductive sheet; 8-a power terminal; 9-epoxy resin; 10-upper electron irradiation; 11-lower electron irradiation; 12-solder layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Examples
As shown in fig. 1, the present embodiment provides an electron irradiation resistant MOSFET ruggedized package structure, including: the buffer conductive sheet 2, the first anti-radiation conductive sheet 3, the second anti-radiation conductive sheet 4, the third conductive sheet 5, the fourth conductive sheet 6, the fifth conductive sheet 7, the power terminal 8, the epoxy resin 9 and the solder layer 12;
as shown in fig. 1 and 3, the lower drain of the MOSFET chip 1 is connected to the second radiation resistant conductive sheet 4 through a solder layer 12, and the second radiation resistant conductive sheet 4 leads out of the chip drain through the power terminal 8; the area of the second anti-radiation conducting sheet 4 is far larger than that of the MOSFET chip 1, and the second anti-radiation conducting sheet is used for resisting electron radiation from the lower part of the MOSFET chip;
the source electrode above the MOSFET chip 1 is connected with the buffering conducting strip 2 through a solder layer 12; the other end of the buffering conducting strip 2 is connected with the first anti-radiation conducting strip 3 through a solder layer 12, and a source electrode of the MOSFET chip is led out through a fourth conducting strip 6 and a power terminal 8; the buffer conducting strip 2 plays a role in relieving the stress of the MOSFET chip 1 and the solder layer 12; the area of the first radiation-resistant conducting sheet 3 is larger than that of the MOSFET chip 1, and is used for resisting electron radiation from the upper part of the MOSFET chip;
the grid of the MOSFET chip 1 is connected with the third conducting strip 5 through a solder layer 12, and then the grid of the MOSFET chip 1 is led out through the fifth conducting strip 7 and the power terminal 8;
the third conductive sheet 5 and the first radiation-resistant conductive sheet 3 together resist electron radiation from above the MOSFET chip;
the first anti-radiation conducting strip 3, the second anti-radiation conducting strip 4 and the third conducting strip 5 are made of high-Z material conducting strips such as tungsten and tantalum, the thickness of the conducting strips is 0.2mm-2mm from the position right above or right below the MOSFET chip 1, and the conducting strips are used for resisting high-energy electron radiation; the heights of the upper surfaces of the first radiation-resistant conducting strip 3 and the third conducting strip 5 are the same;
the fourth conducting strip 6, the fifth conducting strip 7 and the power terminal 8 are all made of copper materials, and the copper materials basically have no influence on the radiation resistance of the MOSFET chip 1, so the copper materials are adopted for reducing the weight of devices;
finally, all the components form the epoxy resin 9 into a solid through an injection molding process to protect the MOSFET chip;
compared with the traditional packaging structure with bonding wires shown in figure 2, the invention greatly improves the anti-irradiation capability of the device, simultaneously reduces the parasitic inductance of the device due to the elimination of the bonding wires, and further reduces the problems of voltage overshoot caused by the parasitic inductance when the device is turned off and electromagnetic interference under high-frequency working conditions.
Note that the MOSFET is a sipmosfet or SiCMOSFET.
Verification experiment
Table 1 below shows the parasitic inductance extraction results of the MOSFET ruggedized package structure resistant to electron irradiation and the conventional bonding wire based package structure; wherein L isgsloopAnd LdsloopParasitic inductances of a driving loop and a power loop of the MOSFET device respectively; as can be seen from the results, compared with the conventional bonding wire based package structure, although the MOSFET ruggedized package structure provided by the present invention is additionally provided with the radiation-resistant conductive sheet and the buffer layer, the parasitic inductances of the driving loop and the power loop are still reduced by 13.16% and 35.28%, respectively.
TABLE 1
In order to verify the anti-irradiation performance of the packaging structure provided by the invention, a verification experiment adopts a 1.2kV/149ASiC MOSFET anti-irradiation packaging structure and a traditional packaging SiC MOSFET device, wherein the first anti-irradiation conducting strip 3 and the second anti-irradiation conducting strip 4 of the packaging structure are made of high-Z material tungsten, and the thickness of the high-Z material tungsten is 0.5 mm; performing an electron irradiation experiment on a SiC MOSFET device to be irradiated by adopting an EBLab-200ebeam Technologies electron beam irradiation device, wherein the electron energy is 0.2MeV, and the irradiation dose is gradually increased; finally, the change of the threshold voltage of the device under different doses of electron irradiation of the MOSFET reinforced packaging structure resisting electron irradiation and the traditional packaging SiC MOSFET device is obtained, and the result is shown in FIG. 4. As can be seen from the figure: compared with the traditional packaging SiC MOSFET device, the irradiation resistance of the irradiation-resistant SiC MOSFET reinforced packaging structure provided by the invention is obviously improved under the condition of consistent external conditions, the process complexity is not increased, and the application of the irradiation-resistant SiC MOSFET reinforced packaging structure in the environments of aerospace and the like is facilitated. Further, as the cumulative irradiation dose Φ is gradually increased, the threshold voltage variation Δ V under 0.2MeV irradiationthA law that initially changes significantly and then levels off will be presented.
In summary, compared with the prior art, the invention has the following advantages:
the first anti-radiation conducting strip and the second anti-radiation conducting strip have larger areas than that of the MOSFET chip and can cover the MOSFET chip, and the first anti-radiation conducting strip and the second anti-radiation conducting strip can be tightly attached to the metal MOSFET chip and can resist the electron radiation of about 90% of the outside, and meanwhile, the redundant metal is less, so that the volume and the weight of the whole MOSFET reinforced packaging structure are smaller after being combined with the MOSFET chip, and the compromises of the anti-radiation performance, the volume, the weight and the cost are realized.
In the invention, a second anti-radiation conducting strip is connected with a power terminal to lead out a drain electrode of the MOSFET chip; the grid electrode is led out through the conducting strip and the power terminal, and the source electrode is led out through the fourth conducting strip and the power terminal, so that a bonding wire in a traditional packaging structure is eliminated, parasitic inductance is reduced, and the problems of voltage overshoot caused by the parasitic inductance and electromagnetic interference under a high-frequency working condition when the MOSFET chip is switched off are effectively reduced. Is beneficial to exerting the advantage of high switching speed of the existing silicon carbide device.
The fourth conducting strip, the fifth conducting strip and the power terminal are all made of copper materials, so that the radiation resistance of the MOSFET chip is not negatively affected, and meanwhile, the weight of the MOSFET chip is reduced due to the adoption of the copper materials.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
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| CN202111575963.0A CN114334886A (en) | 2021-12-21 | 2021-12-21 | Electron irradiation resistant MOSFET (metal-oxide-semiconductor field effect transistor) reinforced packaging structure |
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| CN202111575963.0A CN114334886A (en) | 2021-12-21 | 2021-12-21 | Electron irradiation resistant MOSFET (metal-oxide-semiconductor field effect transistor) reinforced packaging structure |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635754A (en) * | 1994-04-01 | 1997-06-03 | Space Electronics, Inc. | Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages |
| US20050017339A1 (en) * | 2003-06-19 | 2005-01-27 | Shigeharu Yoshiba | Semiconductor device and switching element |
| US20150200178A1 (en) * | 2014-01-13 | 2015-07-16 | Infineon Technologies Austria Ag | Connection Structure and Electronic Component |
| CN112967938A (en) * | 2020-12-29 | 2021-06-15 | 中国电子科技集团公司第四十七研究所 | Aerospace-level integrated circuit total dose shielding method and anti-radiation reinforcement effect verification method |
| CN113345871A (en) * | 2021-04-25 | 2021-09-03 | 华中科技大学 | Low parasitic inductance series power module |
| WO2021223694A1 (en) * | 2020-05-06 | 2021-11-11 | Yan Xinhai | Power semiconductor device |
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2021
- 2021-12-21 CN CN202111575963.0A patent/CN114334886A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635754A (en) * | 1994-04-01 | 1997-06-03 | Space Electronics, Inc. | Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages |
| US20050017339A1 (en) * | 2003-06-19 | 2005-01-27 | Shigeharu Yoshiba | Semiconductor device and switching element |
| US20150200178A1 (en) * | 2014-01-13 | 2015-07-16 | Infineon Technologies Austria Ag | Connection Structure and Electronic Component |
| WO2021223694A1 (en) * | 2020-05-06 | 2021-11-11 | Yan Xinhai | Power semiconductor device |
| CN112967938A (en) * | 2020-12-29 | 2021-06-15 | 中国电子科技集团公司第四十七研究所 | Aerospace-level integrated circuit total dose shielding method and anti-radiation reinforcement effect verification method |
| CN113345871A (en) * | 2021-04-25 | 2021-09-03 | 华中科技大学 | Low parasitic inductance series power module |
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