CN114328356B

CN114328356B - Mutual conversion module board of GMLAN signal and double-wire CAN signal

Info

Publication number: CN114328356B
Application number: CN202210001402.8A
Authority: CN
Inventors: 陈永亮; 周蓉; 李冬华
Original assignee: Shanghai Yuran Industrial Co ltd
Current assignee: Shanghai Yuran Industrial Co ltd
Priority date: 2022-01-04
Filing date: 2022-01-04
Publication date: 2024-01-30
Anticipated expiration: 2042-01-04
Also published as: CN114328356A

Abstract

The invention discloses a mutual conversion module board of a GMLAN signal and a double-wire CAN signal, which comprises a double-wire CAN module, a GMLAN module and a singlechip module, wherein the double-wire CAN module sends the CAN signal to the singlechip module through a CAN tool, the GMLAN module sends the GMLAN signal to the singlechip module, and the singlechip receives, stores and converts the two signals and sends the signals to the double-wire CAN module or the GMLAN module.

Description

Mutual conversion module board of GMLAN signal and double-wire CAN signal

Technical field:

the invention relates to the field of information processing, in particular to the field of interconversion of a vehicle GMLAN signal and a double-wire CAN signal.

The background technology is as follows:

in the development of an electronic module of an automobile, a high-speed double-wire CAN bus is generally adopted, while in a general automobile, a GMLAN bus is adopted, so that the electronic module developed by the double-wire CAN bus is conveniently applied to the general automobile, and the signals of the two buses are required to be mutually converted.

CAN is an internationally standardized serial communication protocol, the english full name of which is controllerareaanetwork.

At the end of the 80 s of the 20 th century, the industry developed rapidly and the automotive industry was gradually rising, and a company called Bosch, germany, first proposed the concept of the CAN protocol. At this time, as more and more consumers are increasingly demanding electronic operation based automotive functions, the communication between these electronic devices becomes more and more complex, and the signal lines connecting them become more and more complex. As the electronic control assemblies of modern automobiles are ever-larger, the signal lines for communication between these assemblies are also ever-increasing, and CAN buses have been proposed to solve this series of problems. They then designed a simple bus topology to which all peripheral devices that need to communicate can connect and communicate. In order to reduce the number of signal wire harnesses and realize high-speed communication of large-scale data through a plurality of local area networks, an electric business company named bosh in germany has developed a CAN communication protocol mainly aiming at automobiles in 1986, and then CAN is gradually developed and continuously perfected, and in 1993, the CAN bus has been widely applied to the fields of aviation, automobiles, security and the like because of high real-time performance of the serial communication protocol.

MGLAN is a general automotive lan, which is called a general motorslocationnetwork.

With the rapid development of global economy, people pursue quality of life more and more, vehicles become necessary articles for people to live, and the serial data communication connection of vehicles with complex and complicated functions among general saab, general international, general North America and the general North America makes the application of electronic modules with the same functions on different vehicle types extremely difficult. The general technical commission of companies then proposed a single-wire communication protocol with data communication baud rate of 20 to 50kbps using the same serial data protocol and physical layer as the essential elements, and developed the GMLAN known now from the international project group by development and modification of various schemes.

The GMALN only needs one line for communication, which greatly reduces the complexity of the vehicle body, but the communication speed is greatly reduced, the GMALN message is a fragment of a message sent in one single GMLAN physical layer transmission, the data bytes of the GMALN message are integer bytes of 0-8, the number of bytes can be less than 8, but the number of bytes cannot exceed 8, otherwise, the GMALN message overflows, and the data after the storage position is affected. When signals are transmitted, a set of signals are arranged together for transmission, with a message corresponding to a GMLAN identifier (i.e., ID).

To apply the international open internet standard reference model in GMLAN, the model must be modified, so that several layers with similar functions are finally extracted from the model, and at the same time, additional layers for describing some functions in detail in the automotive environment are added, and the GMLAN communication model is shown in fig. 1-3. The node management layer can exchange signals with the data link layer, the physical layer and the application layer, the network management layer can exchange data with the interaction layer, the data link layer and the application layer, the interaction layer, the network layer, the data link layer and the physical layer can only exchange data one by one.

The existing products of Vehiclespy3 on the market CAN realize the mutual conversion of the GMLAN signal and the double-wire CAN signal, and the high price is the greatest disadvantage of the products although the functions are perfect, for example, the RAO.GALAXY purchase price in Vehiclespy3 is 13 ten thousand RMB, and the neo.VIFIRE2 purchase price is 7 ten thousand RMB.

The invention comprises the following steps:

aiming at the defects existing in the prior art, the embodiment of the invention aims to provide a mutual conversion module board of a GMLAN signal and a double-wire CAN signal, which uses a low-cost technology and equipment to realize the mutual conversion of the double-wire CAN signal and the GMLAN signal, and is designed to be divided into a double-wire CAN module, a GMLAN module and a singlechip module. The double-wire CAN module sends CAN signals to the singlechip module through the CAN tool, the GMLAN module sends GMLAN signals to the singlechip module through the universal automobile instrument, and the singlechip receives, stores and converts the two signals and sends the signals to the double-wire CAN module or the GMLAN module. The design adopts low-cost components and debugging tools to successfully realize the stable conversion of the GMLAN and CAN signals, and CAN reduce the development cost of vehicle equipment.

In order to achieve the above purpose, the present invention provides the following technical solutions:

the mutual conversion module board of the GMLAN signal and the double-wire CAN signal comprises a double-wire CAN module, a GMLAN module and a singlechip module, wherein the double-wire CAN module sends the CAN signal to the singlechip module through a CAN tool, the GMLAN module sends the GMLAN signal to the singlechip module, and the singlechip receives, stores and converts the two signals and sends the signals to the double-wire CAN module or the GMLAN module.

As a further scheme of the invention, when the CAN signal is converted into the GMLAN signal, a CAN tool is used for transmitting the CAN signal to the double-wire CAN module, the double-wire CAN module transmits the received CAN signal to the singlechip, the singlechip receives the CAN signal and then stores the CAN signal in the internal buffer area, the singlechip reads out and processes the data in the buffer area and transmits the processed data to the GMLAN module, and the GMLAN module receives the data given by the singlechip and transmits the data to the instrument; when GAMLAN signal is transferred to CAN signal, the data of signal instrument is sent to GMLAN module through GMLAN bus, after receiving data, the GMLAN module sends data to single chip microcomputer, after receiving signal, the single chip microcomputer puts into storage area, after processing, the data is transferred to double-wire CAN module.

As a further scheme of the invention, the singlechip module comprises a GD32F305VCT6 chip; the GMLAN module includes an NCV7356 chip; the two-wire CAN module includes a TJA1042 chip.

As a further scheme of the invention, the singlechip module comprises a GD32F305VCT6 chip, a reset circuit, a power circuit and a crystal oscillator, further preferably, an NCV7356 chip, pins TXD and RXD, which are responsible for signal transmission and reception with the singlechip GD32F305VCT6, are respectively connected with the pins of the singlechip GD32F305VCT6, the mode control bit of the TJA1042 chip CAN transmit and receive CAN_H and CAN_L at a low level, the pin 1TXD and the pin 4RXD are respectively connected with the corresponding pins of the singlechip, the pin CANH and the pin CANL are respectively connected with a CAN bus through a common mode choke coil ACT45-101, and a 60 ohm terminal resistor is respectively connected between the CAN_H and the CAN_L so as to filter interference and prevent signal interference source signals reflected in the signal transmission process.

As a further aspect of the present invention, at the time of signal conversion: firstly resetting all peripheral devices, initializing FLASH and a system clock, resetting the system clock, initializing GPIO, configuring a GPIO port, calling a two-wire CAN module and a GMLAN module, processing and transmitting data of the two modules, resetting all registers except a backup domain when power supply reset occurs, and otherwise, continuing to execute the program until the program is ended.

As a further scheme of the invention, the two-wire CAN module works: initializing a two-wire CAN module, setting an IO port, opening data receiving, starting to receive data, putting the received data into a designated storage area according to a rule, performing data processing, starting to transmit the data after the data processing is finished, judging whether the data is successfully transmitted after the corresponding time, returning if the data is successfully transmitted, and otherwise, continuing to transmit the data until the data is successfully transmitted.

As a further scheme of the invention, the GMLAN module works: initializing a GMLAN module, opening data receiving, starting to receive data, putting the received data into a designated storage area according to a rule, then carrying out corresponding data processing, starting to send the data after the processing is finished, judging whether the data is successfully sent after the corresponding time, if the data is failed to be sent, continuing to send the data, continuing to judge whether the data is successfully sent until the data is successfully sent, and returning to a main function.

In order to more clearly illustrate the structural features and efficacy of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and examples.

Description of the drawings:

fig. 1 is a general block diagram of the present invention GMLAN signal and two-wire CAN signal interconversion module board.

FIG. 2 is a schematic diagram of a single-chip microcomputer module in the invention;

FIG. 3 is a pin diagram of a GD32F305VCT6 chip in the present invention;

FIG. 4 is a schematic diagram of a GD32F305VCT6 power supply in accordance with the present invention;

FIG. 5 is a circuit diagram of the crystal oscillator circuit referred to in the present invention;

FIG. 6 is a diagram of the pins and peripheral circuits of the NCV7356 chip of the present invention;

FIG. 7 is a diagram of the TJA1042 chip pins and peripheral circuitry referred to in the present invention;

FIG. 8 is a flow chart of a main routine mentioned in the present invention;

FIG. 9 is a two-wire CAN module program flow diagram as referred to in the invention;

fig. 10 is a flow chart of the GMLAN module program mentioned in the present invention.

FIG. 11 is a schematic diagram of the type of GD32F3 chips set forth in the present invention.

Fig. 12 is a general design circuit diagram referred to in the present invention.

The specific embodiment is as follows:

the invention will be further described in the following clear and complete description with reference to the figures and the associated knowledge, it being evident that the described applications are only some, but not all embodiments of the invention.

In the invention, through the mutual conversion module board of the GMLAN signal and the double-wire CAN signal, the design is divided into three modules of a double-wire CAN module, a GMLAN module and a singlechip module. The double-wire CAN module sends CAN signals to the singlechip module through the CAN tool, the GMLAN module sends GMLAN signals to the singlechip module through the universal automobile instrument, and the singlechip receives, stores and converts the two signals and sends the signals to the double-wire CAN module or the GMLAN module. The design adopts low-cost components and debugging tools to successfully realize the stable conversion of the GMLAN and CAN signals, and CAN reduce the development cost of vehicle equipment.

Referring to fig. 1, the inter-conversion module board of the GMLAN signal and the two-wire CAN signal comprises a two-wire CAN module, a GMLAN module and a single-chip microcomputer module, wherein the two-wire CAN module sends the CAN signal to the single-chip microcomputer module through a CAN tool, the GMLAN module sends the GMLAN signal to the single-chip microcomputer module, and the single-chip microcomputer receives, stores, converts and sends the two signals to the two-wire CAN module or the GMLAN module.

In the invention, when a CAN signal is converted into a GMLAN signal, a CAN tool is used for transmitting the CAN signal to a double-wire CAN module, the double-wire CAN module transmits the received CAN signal to a singlechip, the singlechip receives the CAN signal and then stores the CAN signal in an internal buffer area, the singlechip reads and processes the data in the buffer area and transmits the data to the GMLAN module, and the GMLAN module receives the data given by the singlechip and transmits the data to an instrument; when GAMLAN signal is transferred to CAN signal, the data of signal instrument is sent to GMLAN module through GMLAN bus, after receiving data, the GMLAN module sends data to single chip microcomputer, after receiving signal, the single chip microcomputer puts into storage area, after processing, the data is transferred to double-wire CAN module.

Further preferably, the singlechip module comprises a GD32F305VCT6 chip, and specifically comprises a main chip GD32F305VCT6, a reset circuit, a power circuit and a crystal oscillator. The main chip is GD32F305VCT6, when the CPU works at the frequency less than or equal to 128MHz, the program running in FLASH can have the running waiting period reaching the degree of approximately zero. GD 32F-series microcontrollers provide features such as hardware dividers, thumb-2 instruction sets, low interrupt response times, multi-bus simultaneous access, and bit-band operation, which enhance their computing power. The chip comprisesKernel (I)>The processor core is the next generation processor core, can well support the requirements of low power consumption and high performance in the market, and the memory can be mapped to a storage space of 4GB, so that the system has good flexibility, and the working voltage is 2.6V-3.6V.

The GD32F305VCT6 has 3 Boot modes, mainFlashMemory, systemMemory and On-chip RAM, and can be configured through BOOT1 and BOOT0 pins. After the two pins are set, a power-on reset or system reset operation is performed. On the 4 th rising edge after the reset operation, the BOOT pin will be latched, thereby determining the start-up option. In this design, BOOT0 and BOOT1 are connected low, namely, the starting mode is set as MainFlashmemory, so that the starting address of FLASH starting after reset is 0x08000000.

GD32F305VCT6 includes three reset controls: system reset, power reset, and backup domain reset. The design mainly uses power supply reset, and is reset by power-on/power-off. The power reset is active low and all registers except the backup domain are reset during the power reset. The power reset pin remains low until the internal LDO power reference provides a good 1.2V voltage. The reset entry vector is fixed at address 0x0000_0004.

In the invention, the GMLAN module comprises an NCV7356 chip, and pins 1, 7, 8 and 14 are GND, grounded, pins 2 and 5 are TXD and RXD respectively, and are responsible for transmitting and receiving signals with a single-chip microcomputer GD32F305VCT6, and are respectively connected with pins 51 and 52 of the single-chip microcomputer GD32F305VCT6. 3. The 4 pins are mode control pins, which are connected with high level through a resistor and grounded through a decoupling capacitor of 0.1uF, namely the chip mode is set to be a general mode. Pins 6, 13 and 9 are suspended, pin 11 is a resistor load pin and is connected with pin 12 CANH through a resistor, and the high-resistance state can be switched to when the chip breaks down so as to protect the circuit. In fig. 6, an inductance of 47uH is connected in parallel with a resistance of 1K and then connected in series with the CANH pin, and then grounded through a decoupling capacitor, where the inductance and the capacitor are used to eliminate electromagnetic interference of the circuit to the external environment. Pin 10 is VBAT pin, is battery powered pin, and when VDD power was shut down, the switch was switched to the VBAT pin with the power to the power, was supplied with power by VBAT.

In the present invention, the two-wire CAN module includes a TJA1042 chip, and referring to fig. 7, pin 8 is a STB pin, and is a mode control bit of the TJA1042 chip, and CAN send and receive can_h and can_l at low level. The pin 1TXD, the pin 4RXD and the singlechip are used for transmitting and receiving signals, the pins are respectively connected with 96 pins and 95 pins of the singlechip, the pin 6CANH and the pin 5CANL are connected with a CAN bus through a common mode choke coil ACT45-101, and a 60 ohm terminal resistor is respectively connected between the CAN_H and the CAN_L so as to filter interference, prevent signals reflected back in the signal transmission process from interfering original signals, and finally the signals are grounded through a decoupling capacitor. The common mode choke coils ACT45-101 can filter out common mode electromagnetic interference on the signal lines on one hand and can inhibit the circuit from sending out electromagnetic interference to the outside on the other hand. The pin 5SPLIT is connected with a 3.3V power supply and is used for stabilizing the CAN bus voltage, and then the voltage is grounded through a capacitor of 0.1uF, so that the decoupling effect of the circuit is achieved. Pin 3VDD is connected to the 5V power supply and is grounded via a decoupling capacitor of 0.1uF, and pin 2VSS is grounded.

In the present invention, at the time of signal conversion: firstly resetting all peripheral devices, initializing FLASH and a system clock, resetting the system clock, initializing GPIO, configuring a GPIO port, calling a two-wire CAN module and a GMLAN module, processing and transmitting data of the two modules, resetting all registers except a backup domain when power supply reset is generated, otherwise, continuing to execute a program until the program is finished, and further, when the two-wire CAN module works: initializing a two-wire CAN module, setting an IO port, opening data receiving, starting to receive data, putting the received data into a designated storage area according to a rule, performing data processing, starting to send the data after the data processing is finished, judging whether the data is successfully sent after the corresponding time, returning if the data is successfully sent, and otherwise, continuing to send the data until the data is successfully sent; the GMLAN module works: initializing a GMLAN module, opening data receiving, starting to receive data, putting the received data into a designated storage area according to a rule, then carrying out corresponding data processing, starting to send the data after the processing is finished, judging whether the data is successfully sent after the corresponding time, if the data is failed to be sent, continuing to send the data, continuing to judge whether the data is successfully sent until the data is successfully sent, and returning to a main function.

The following provides a specific embodiment of the present invention

Example 1

Referring to fig. 1-12, the inter-conversion module board of the GMLAN signal and the two-wire CAN signal of the present invention realizes the inter-conversion of the two-wire CAN and the GMLAN signal by low cost technology and equipment; the design is divided into three modules, namely a double-wire CAN module, a GMLAN module and a singlechip module. The double-wire CAN module sends CAN signals to the singlechip module through the CAN tool, the GMLAN module sends GMLAN signals to the singlechip module through the universal automobile instrument, and the singlechip receives, stores and converts the two signals and sends the signals to the double-wire CAN module or the GMLAN module. The design adopts low-cost components and debugging tools to successfully realize the stable conversion of the GMLAN and CAN signals, and CAN reduce the development cost of vehicle equipment.

Referring to fig. 1, the universal automobile instrument comprises a two-wire CAN module, a GMLAN module and a single-chip microcomputer module, wherein the universal automobile instrument is a mechanical instrument panel on a universal automobile, the CAN instrument is an auxiliary instrument and is responsible for simulating physical signals on the automobile, and the two modules are not designed.

The double-wire CAN module mainly comprises a CAN chip and a peripheral circuit thereof, the GMLAN module mainly comprises a GMLAN chip and a peripheral circuit thereof, and the singlechip mainly comprises a domestic GD32 chip and a minimum system thereof. When the CAN is converted into the GMLAN, a CAN tool is used for transmitting a CAN signal to a double-wire CAN module, the double-wire CAN module transmits the received CAN signal to a singlechip, the singlechip receives the CAN signal and then stores the CAN signal in an internal buffer area, the singlechip reads out and processes the data in the buffer area and transmits the data to a GMLAN module, the GMLAN module transmits the data to an instrument after receiving the data fed by the singlechip, and finally the data CAN be displayed on the instrument; when GAMLAN changes CAN, the data of the signal instrument CAN be sent to the GMLAN module through the GMLAN bus, the GMLAN module sends the data to the singlechip after receiving the data, the singlechip receives the signal and then sends the signal to the storage area, the signal is processed and then forwarded to the double-wire CAN module, the double-wire CAN module sends the data to KVASERLEAFLIGHTV2, and finally the data sent by the instrument is displayed on the PC end software interface of the tool.

Compared with STM32, the domestic GD23 series has the advantages that the kernel is an upgrade of Cortex-M3 and compatible with Cortex-M3, the zero-waiting technology of Flash is realized, the instruction extracting time is reduced, the code executing speed is faster, the capacity of Flash and RAM of GD in the same series is also larger, the GD can reach 108MHz on the main frequency, and the highest ST is 72MHz, so the code executing speed of GD chips is faster. Because GD is a domestic chip, the cost is lower, so that the selection of GD series chips is decided.

The GD32F3 series is an upgrade of the GD32F1 series, and for convenience of design modification, the GD32F3 series is primarily defined, and the GD32F3 series chip type is shown in fig. 11. Considering the problem of Flash execution speed, the code execution speed of the first 256K is normal, and the code response interrupt speed of the back 256K is very slow, so the FLASH of the chip is required to be more than or equal to 256K, the FLASH of only 256K is required for design prediction, the FLASH is determined to be 256K in consideration of economic problems, and the two-way CAN is required for design, so the chip with two paths of CAN channels is required to be selected. The main chip of the design is selected as GD32F305VCT6.

In the present embodiment, the system architecture of GD32F305VCT6 includes storage,Core and bus architecture and organization. />The kernel is a new generation processor kernel, can well support the market demands of low power consumption and high performance, and greatly enhances the market applicability. The core comprises three buses: ICode bus, DCode bus, system bus. The memory organization adopts the Harvard structure, and all memory access requirements can be reasonably obtained in the 3 buses according to different memory spaces and purposesAnd (5) distribution. The system architecture memory of the GD32F305VCT 6can be mapped to 4GB of storage space, so the system has good flexibility and expandability.

In this embodiment, GMLAN module chip select, chip NCV7356 is a physical layer device for single line data links capable of multiple access with different carrier sense, with collision resolution (CSMA/CR) protocols such as Bosch Controller Area Network (CAN) version 2.0. The purpose of a serial data link network is to be used in applications that do not require high data rates, and the lower data rates may enable cost reduction of physical media components and microprocessors and/or dedicated logic devices that use the network.

The network should be capable of operating in either a normal data rate mode or a high speed data download mode for assembly line and service data transfer operations. The normal communication rate is typically 33kbit/s and the NCV7356 is designed from a single wire to support many additional functions such as low voltage lockout, suspending the input of a false input signal, and outputting space time to handle the car's ring tone and low sleep mode current.

The following are NCV7356 chip characteristics

The operating voltage range is 5.0 to 27V. The inputs to the logic are compatible with 3.3V and 5V supply systems. Control pins of the external voltage regulator. Sleep mode timeout is prepared. A complete receiver filter. The load can be prevented from toppling over, and the jump is started. Thermal overload and short circuit protection. And (5) locking under-voltage. The bus dominates the timeout feature. The NCV prefix is used for automobiles and other applications where location and change control is required.

In this embodiment, the selection of the CAN chip specifically includes: chips of the two-way high speed CAN have TJA1040, PCA82C250, PCA82C251 and TJA1042, but TJA1042 was developed from the high speed CAN of TJA1040, PCA82C250 and PCA82C251, which provides improved electromagnetic compatibility (EMC) and electrostatic discharge (ESD) performance, as well as characteristics. Therefore, for the two-wire CAN module, in order to facilitate the design modification and implementation, TJA1042 with higher performance is selected, and the chip characteristics of TJA1042 mainly include:

is fully compatible with ISO11898-2 and ISO11898-5. Is suitable for 12V and 24V systems. Low electromagnetic radiation (EME) and high electromagnetic immunity (EMI); the Vio input allows direct access to the 3V to 5V microcontroller; a very low standby mode with host and bus wakeup functions. When not activated, the transceiver is disconnected from the bus (zero load); high ESD handling capability on bus pins. In an automotive environment, pins of a bus are protected from transients. The time-out function is dominant when data is Transmitted (TXD). The bus in standby mode dominates the timeout function. With undervoltage detection of pinVCC and VIO.

In this embodiment, the design of the singlechip module includes: referring to fig. 2, the main chip GD32F305VCT6, reset circuit, power supply circuit and crystal oscillator are included; referring to FIG. 3, the main chip is GD32F305VCT6, and when the CPU operates at a frequency of 128MHz or less, the program running in FLASH can have a running waiting period to the extent of approximately zero. GD 32F-series microcontrollers provide features such as hardware dividers, thumb-2 instruction sets, low interrupt response times, multi-bus simultaneous access, and bit-band operation, which enhance their computing power. The chip comprisesKernel (I)>The processor core is the next generation processor core, can well support the requirements of low power consumption and high performance in the market, and the memory can be mapped to a storage space of 4GB, so that the system has good flexibility, and the working voltage is 2.6V-3.6V.

Referring to fig. 4, GD32F305VCT6 has three power domains, a backup domain, a 1.2V power domain and a VDD/VDDA domain, where VDD is connected to VDDA, and then connected to 3.3V power after being connected to ground through 6 0.1uF capacitors and 6 1uF capacitors, so that decoupling capability of the power can be improved by connecting a plurality of capacitors, and VSS is connected to VSSA and grounded. A voltage regulator is installed in the VDD/VDDA domain to supply power to the 1.2V power domain. The backup domain is that when the VDD power supply is turned off, the power supply switch switches the power supply to the Vbat pin, and the Vbat pin is connected to the 3.3V power supply after being connected to the ground through 1 0.1uF capacitor and 1uF decoupling capacitor.

Referring to FIG. 5, a GD32F305VCT6 minimum system oscillator circuit is shown. The crystal oscillator circuit is connected to pins 12 and 13 of GD32F305VCT6, and the circuit mainly comprises a crystal oscillator, a load capacitor and an internal circuit. The crystal oscillator adopts an internal high-speed 8M RC oscillator clock (HSI), and two 18pF capacitors are responsible for starting and resonating and are respectively connected to two sides of the crystal oscillator and grounded.

In this embodiment, the GMLAN module design includes: referring to fig. 6, an NCV7356 chip pin and peripheral circuit diagram is shown. Pins 1, 7, 8 and 14 are GND, grounded, pins 2 and 5 are TXD and RXD respectively, and are responsible for transmitting and receiving signals with the single chip microcomputer GD32F305VCT6 and are respectively connected with pins 51 and 52 of the single chip microcomputer GD32F305VCT6. 3. The 4 pins are mode control pins, which are connected with high level through a resistor and grounded through a decoupling capacitor of 0.1uF, namely the chip mode is set to be a general mode. Pins 6, 13 and 9 are suspended, pin 11 is a resistor load pin and is connected with pin 12 CANH through a resistor, and the high-resistance state can be switched to when the chip breaks down so as to protect the circuit. And the 9596 pins of GD32F305VCT6 are initialized to CAN1 RX and CAN 1TX, respectively, of the chip CAN module. In fig. 5, an inductance of 47uH is connected in parallel with a resistance of 1K and then connected in series with the CANH pin, and then grounded through a decoupling capacitor, where the inductance and the capacitor are used to eliminate electromagnetic interference of the circuit to the external environment. Pin 10 is VBAT pin, is battery powered pin, and when VDD power was shut down, the switch was switched to the VBAT pin with the power to the power, was supplied with power by VBAT.

In this embodiment, the two-wire CAN module design specifically includes: referring to fig. 7, a chip pin and peripheral circuit diagram of TJA1042 is shown. Pin 8 is the STB pin, is the mode control bit of TJA1042 chip, and CAN send and receive CAN_H and CAN_L when the level is low. The pin 1TXD, the pin 4RXD and the singlechip are used for transmitting and receiving signals, the pins are respectively connected with 96 pins and 95 pins of the singlechip, the pin 6CANH and the pin 5CANL are connected with a CAN bus through a common mode choke coil ACT45-101, and a 60 ohm terminal resistor is respectively connected between the CAN_H and the CAN_L so as to filter interference, prevent signals reflected back in the signal transmission process from interfering original signals, and finally the signals are grounded through a decoupling capacitor. The common mode choke coils ACT45-101 can filter out common mode electromagnetic interference on the signal lines on one hand and can inhibit the circuit from sending out electromagnetic interference to the outside on the other hand. The pin 5SPLIT is connected with a 3.3V power supply and is used for stabilizing the CAN bus voltage, and then the voltage is grounded through a capacitor of 0.1uF, so that the decoupling effect of the circuit is achieved. Pin 3VDD is connected to the 5V power supply and is grounded via a decoupling capacitor of 0.1uF, and pin 2VSS is grounded.

Referring to fig. 8, the main program first resets all peripheral devices, initializes FLASH and a system clock, reconfigures the system clock, initializes GPIO, configures GPIO ports, invokes the two-wire CAN module subroutine and the GMLAN module subroutine, and processes and transmits data of the two modules. When the power reset is generated, resetting all registers except the backup domain, otherwise, continuing to execute the program until the program is ended.

Referring to fig. 9, a two-wire CAN module program flow diagram is shown. The method comprises the steps of initializing a two-wire CAN module, setting an IO port, opening data receiving, starting to receive data, putting the received data into a designated storage area according to a rule, performing data processing, starting to send the data after the data processing is finished, judging whether the data is successfully sent or not after a certain time, returning if the data is successfully sent, and if the data is not successfully sent, continuing to send the data until the data is successfully sent.

Referring to fig. 10, a GMLAN module program flow chart is shown. When the method is started, the GMLAN module is initialized, then data receiving is started, the received data is put into a specified storage area according to rules, then corresponding data processing is carried out, after the data processing is finished, the data is started to be sent, whether the data is successfully sent is judged after a certain time, if the data is failed to be sent, the data is continuously sent, whether the data is successfully sent is continuously judged, until the data is successfully sent, and then a main function is returned.

In this embodiment, through the above circuit design and board test, the GMALN signal and the two-wire CAN signal module board CAN realize accurate interconversion of the GMALN signal and the two-wire CAN signal.

Example 2

The GMLAN signal and two-wire CAN signal interconversion module board application embodiments,

compiling the flow: the compilation environment selects keil5. Keil5 is installed. And downloading the chip library of the update keil5. And importing the written engineering into the keil5, clicking to complete compiling and starting compiling. When the compiling is wrong, the engineering is correspondingly modified, and the compiling is carried out again after the modification until the compiling passes;

hardware debugging flow: the debugging respectively uses a dashboard and CAN tool of a general automobile and BUSMASTER. The instrument panel is responsible for displaying the converted GMLAN signal received from the singlechip, then sending the GMLAN signal containing the state content of the instrument panel to the singlechip, and the BUSMASTER is connected with the CAN tool and is responsible for simulating the CAN signal, and also responsible for receiving the CAN signal converted by the singlechip and displaying the CAN signal on the BUSMASTER.

The specific process of hardware debugging is as follows:

and (5) carrying out hardware welding according to the drawn circuit diagram, and checking whether the virtual welding or the short circuit is carried out by using a universal meter after the welding is finished.

The BUSMASTER and the CAN driver are installed, and the signal name, the correct address and the related parameter setting of the CAN signal to be transmitted are added to the message of the BUSMASTER.

Installing a Jlink driver, connecting the power ends of the instrument and the hardware board to a 12V direct current stabilized power supply according to a designed connection circuit, connecting the ground ends to the ground, connecting the Jlink and a CAN tool, checking the connection state, and carrying out the next step when the connection state is correct.

And downloading the compiled program into the hardware chip.

And opening a BUSMASTER transmitting interface, filling in a state value of a signal to be transmitted, and checking the signal to be transmitted to transmit the signal.

And (3) observing the display state of the corresponding signal of the instrument, and if the display state is not in accordance with the expected state, carrying out corresponding modification on the engineering, and operating the process again until the instrument display reaches the expected state.

Debugging results: the state of the instrument panel CAN be correctly controlled by controlling the CAN signal sent by the BUSMASTER, and the BUSMASTER CAN also correctly receive the state sent by the instrument, which shows that the conversion circuit board CAN realize the mutual conversion between the GMLAN signal and the double-wire CAN signal.

The technical principle of the present invention has been described above in connection with specific embodiments, but is only the preferred embodiment of the present invention. The protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. Other embodiments of the invention will occur to those skilled in the art without the exercise of inventive effort and are intended to fall within the scope of the invention.

Claims

The mutual conversion module board of the GMLAN signal and the double-line CAN signal is characterized by comprising a double-line CAN module, a GMLAN module and a singlechip module, wherein the double-line CAN module sends CAN signals to the singlechip module through a CAN tool, the GMLAN module sends the GMLAN signals to the singlechip module, the singlechip receives, stores and converts the two signals and sends the signals to the double-line CAN module or the GMLAN module, and the double-line CAN module works: initializing a two-wire CAN module, setting an IO port, opening data receiving, starting to receive data, putting the received data into a designated storage area according to a rule, then performing data processing, starting to send the data after the data processing is finished, judging whether the data is successfully sent after corresponding time, returning if the data is successfully sent, otherwise, continuing to send the data until the data is successfully sent, wherein the GMLAN module works: initializing a GMLAN module, opening data receiving, starting to receive data, putting the received data into a designated storage area according to a rule, then carrying out corresponding data processing, starting to send the data after the processing is finished, judging whether the data is successfully sent after the corresponding time, if the data is failed to be sent, continuing to send the data, continuing to judge whether the data is successfully sent until the data is successfully sent, and returning to a main function.
2. The mutual conversion module board of the GMLAN signal and the double-wire CAN signal according to claim 1, wherein when the CAN signal is converted into the GMLAN signal, a CAN tool is used for sending the CAN signal to the double-wire CAN module, the double-wire CAN module sends the received CAN signal to the singlechip, the singlechip receives the CAN signal and then stores the CAN signal in an internal buffer area, the singlechip reads out and processes the data in the buffer area and sends the processed data to the GMLAN module, and the GMLAN module receives the data given by the singlechip and sends the data to the instrument; when GAMLAN signal is transferred to CAN signal, the data of signal instrument is sent to GMLAN module through GMLAN bus, after receiving data, the GMLAN module sends data to single chip microcomputer, after receiving signal, the single chip microcomputer puts into storage area, after processing, the data is transferred to double-wire CAN module.
3. The GMLAN signal to two-wire CAN signal interconversion module board of claim 2 wherein said single chip module includes a GD32F305VCT6 chip; the GMLAN module includes an NCV7356 chip; the two-wire CAN module includes a TJA1042 chip.
4. The GMLAN signal to two-wire CAN signal interconversion module board of claim 1, wherein the single chip module includes a GD32F305VCT6 chip, a reset circuit, a power circuit, and a crystal oscillator.
5. The GMLAN signal to two-wire CAN signal interconversion module board of claim 4 wherein upon signal conversion: firstly resetting all peripheral devices, initializing FLASH and a system clock, resetting the system clock, initializing GPIO, configuring a GPIO port, calling a two-wire CAN module and a GMLAN module, processing and transmitting data of the two modules, resetting all registers except a backup domain when power supply reset occurs, and otherwise, continuing to execute the program until the program is ended.
6. The module board for mutually converting GMLAN signals and two-wire CAN signals according to claim 5, wherein the NCV7356 chip, pins TXD, RXD, is responsible for transmitting and receiving signals with the single-chip microcomputer GD32F305VCT6, and is respectively connected with the pins of the single-chip microcomputer GD32F305VCT6.
7. The module board for mutual conversion between GMLAN signal and two-wire CAN signal according to claim 5, wherein the mode control bit of the TJA1042 chip CAN send and receive can_h and can_l at low level, pin 1TXD and pin 4RXD are connected with corresponding pins of the single chip respectively, pin CANH and pin CANL are connected with CAN bus through a common mode choke ACT45-101, and a 60 ohm termination resistor is connected between can_h and can_l respectively to filter interference and prevent signal reflected back in signal transmission from interfering original signals.