CN114328327A - PCIe link processing method and device - Google Patents

Abstract

Embodiments of the present application provide a PCIe link processing method and device, and relate to the field of communications. The method includes: receiving a service processing request; acquiring a first topology diagram of a PCIe system; the first topology diagram includes multiple PCIe chains in the PCIe system displaying the interface including the first topology map; in the case of receiving a trigger operation for any PCIe link in the first topology map, using any PCIe link to process the service corresponding to the service processing request. In the embodiment of the present application, the user can select an appropriate PCIe link according to his own processing requirements for the PCIe link, so that the user's diversified usage scenarios for the PCIe link can be satisfied.

Description

PCIe link processing method and device

technical field

The present application relates to the field of communication technologies, and in particular, to a PCIe link processing method and apparatus.

Background technique

The high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) has good transmission performance and strong throughput, and devices based on the PCIe protocol have been widely used in the field of information and communication technology.

Generally, a PCIe device can use a PCIe link to perform service scheduling. For example, in a scheduling scenario, a PCIe device can randomly select one or more PCIe links for data transmission.

However, the above link selection method cannot meet the user's diverse usage requirements for PCIe links.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a PCIe link processing method and device, which relate to the field of communications. The method includes: receiving a service processing request, acquiring and displaying a topology diagram of a PCIe system, so that a user can flexibly select a desired wish in an interface according to requirements The link for service transmission, in the case of receiving a trigger operation for any PCIe link in the topology diagram, uses any PCIe link to process the service corresponding to the service processing request. In the embodiment of the present application, the user can select the PCIe link according to the requirements, so the diversified usage requirements of the user for the PCIe link can be met.

In a first aspect, an embodiment of the present application provides a PCIe link processing method, including: receiving a service processing request; acquiring a first topology diagram of a PCIe system; the first topology diagram including multiple PCIe links in the PCIe system; displaying Including an interface of the first topology map; in the case of receiving a trigger operation for any PCIe link in the first topology map, use any PCIe link to process the service corresponding to the service processing request. In this way, the user can select the PCIe link according to the requirements, which can meet the user's diversified usage requirements for the PCIe link.

In an exemplary manner, acquiring a first topology diagram of the PCIe system includes: acquiring a second topology diagram of the PCIe system; determining a target device required for processing services; adding redundant devices to the target device in the second topology diagram , to get the first topology map. In this way, when the target device fails, the redundant device can replace the function of the target device, complete service transmission, reduce the impact of the device failure on service processing, and improve the availability of the PCIe system.

In an exemplary manner, adding a redundant device to the target device in the second topology map to obtain the first topology map includes: in the second topology map, disconnecting a partial chain between the redundant device and other devices and the redundant device is used as the backup device of the target device; the other devices are different from the target device. In this way, by disconnecting the link relationship between the target device and other devices, redundant links can be added to the target device to reduce the impact of device failure on service processing, thereby increasing security for service transmission.

In an exemplary manner, determining the target device required for processing the service includes: determining the target device required for processing the service according to the service type of the service. In this way, the target device required for processing the service can be directly obtained according to numerous parameters obtained from the service, so that the computer can use the target device to process other PCIe links.

In an exemplary manner, the service type includes one or more of the following: the data type of the service, the protocol of the service, or the parameter of the service; the parameter of the service is the parameter required when the service is scheduled. In this way, a PCIe link that better matches the service type can be selected according to a more exact service type.

In an exemplary manner, the parameters of the service include one or more of the following: the execution time requirement of the service, the response requirement of the service, or the required bandwidth of the service. In this way, a more matching PCIe link can be selected according to more exact service parameters.

In an exemplary manner, the first topology diagram includes: link quality levels of multiple PCIe links, and/or link attributes of multiple PCIe links. In this way, the user can see not only the topology of the current PCIe system, but also the link properties of each PCIe link on the interface, and can visually display the current state of the PCIe system.

In an exemplary manner, link quality levels of the multiple PCIe links are determined according to link attributes of the multiple PCIe links; wherein, in the interface, the display status of each PCIe link is related to the quality level of the PCIe link. In this way, the link quality level of the link quality of the PCIe link that can be visually represented can be obtained according to various parameters of the link attribute of the complex PCIe link, so as to realize the visualization of the link quality level of the PCIe link.

In an exemplary manner, the display state of the PCIe link includes: the color of the PCIe link and/or the size of the PCIe link. In this way, the user can intuitively see the link quality levels of different PCIe links on the interface where the topology diagram is located, so that the user can select the desired PCIe link scheduling service in the future.

In an exemplary manner, the link attribute of the PCIe link includes one or more of the following: the connection status of the PCIe link, the cascading relationship of the PCIe link, the bandwidth of the PCIe link, or the device of the PCIe link number. In this way, an accurate link quality level can be obtained by using more accurate link attributes.

In an exemplary manner, using any PCIe link to process the service corresponding to the service processing request includes: using a link switch in the PCIe system to schedule the service to any PCIe link for processing; or, using PCIe A register in the system that schedules services to any PCIe link for processing. In this way, when the PCIe link needs to be adjusted, a more appropriate link processing method can be selected according to the actual scene.

In an exemplary manner, when no trigger operation is received within a preset time, the target PCIe link is selected for the service by using the service type of the service and the link quality levels of the multiple PCIe links. In this way, the preset time for receiving the user-triggered operation set in the computing device can optimize the delay and reduce the energy consumption of link processing.

In an exemplary manner, using the service type of the service and the link quality levels of multiple PCIe links to select a target PCIe link for the service, including: determining the bandwidth of the service according to the service type; Quality level, select the target PCIe link that meets the bandwidth of the service among multiple PCIe links. In this way, the method of accurately selecting a PCIe link according to the service bandwidth and PCIe link quality can solve different requirements for link bandwidth and quality in different service scenarios, improve the availability of the PCIe system, and maximize the value of the PCIe link.

In a second aspect, an embodiment of the present application provides a PCIe link processing apparatus.

The PCIe link processing apparatus may be a terminal device, or may be a chip or a chip system in the terminal device. The PCIe link processing apparatus may include a processing unit and a display unit. When the PCIe link processing apparatus is a terminal device, the processing unit may be a processor. The PCIe link processing apparatus may further include a storage unit, which may be a memory. The storage unit is used for storing instructions, and the processing unit executes the instructions stored in the storage unit, so that the terminal device implements a PCIe link processing described in the first aspect or any possible implementation manner of the first aspect method. When the PCIe link processing apparatus is a chip or a chip system in a terminal device, the processing unit may be a processor. The processing unit executes the instructions stored in the storage unit, so that the terminal device implements the PCIe link processing method described in the first aspect or any possible implementation manner of the first aspect. The storage unit may be a storage unit in the chip (eg, a register, a cache, etc.), or a storage unit (eg, a read-only memory or a random access memory, etc.) in the terminal device located outside the chip.

Exemplarily, the processing unit is used to receive a service processing request; the processing unit is used to obtain a first topology diagram of the PCIe system; the first topology diagram includes a plurality of PCIe links in the PCIe system; the display unit is used to display An interface including a first topology map; a processing unit configured to process a service corresponding to a service processing request by using any PCIe link in the case of receiving a trigger operation for any PCIe link in the first topology map.

In an exemplary manner, the processing unit is specifically configured to obtain a second topology diagram of the PCIe system; determine a target device required for processing services; add redundant devices to the target device in the second topology diagram to obtain a first topology picture.

In an exemplary manner, the processing unit is specifically configured to, in the second topology diagram, disconnect a partial link relationship between the redundant device and other devices, and use the redundant device as a backup device of the target device; wherein , other devices are different from the target device.

In an exemplary manner, the processing unit is specifically configured to determine the target device required for processing the service according to the service type of the service.

In an exemplary manner, the service type includes one or more of the following: the data type of the service, the protocol of the service, or the parameter of the service; the parameter of the service is the parameter required when the service is scheduled.

In an exemplary manner, the parameters of the service include one or more of the following: the execution time requirement of the service, the response requirement of the service, or the required bandwidth of the service.

In an exemplary manner, the first topology diagram includes: link quality levels of multiple PCIe links, and/or link attributes of multiple PCIe links.

In an exemplary manner, the processing unit is specifically configured to determine the link quality levels of the multiple PCIe links according to the link attributes of the multiple PCIe links; wherein, in the interface, the display status of each PCIe link and the PCIe link The link quality level of the link is related.

In an exemplary manner, the display state of the PCIe link includes: the color of the PCIe link and/or the size of the PCIe link.

In an exemplary manner, the link attribute of the PCIe link includes one or more of the following: the connection status of the PCIe link, the cascading relationship of the PCIe link, the bandwidth of the PCIe link, or the device of the PCIe link number.

In an exemplary manner, the processing unit is specifically configured to use a link switch in the PCIe system to schedule services to any PCIe link for processing; or, use a register in the PCIe system to schedule services to any PCIe link. processed on a PCIe link.

In an exemplary manner, the processing unit is further configured to select a target PCIe for the service by using the service type of the service and the link quality level of the multiple PCIe links when the trigger operation is not received within a preset time. link.

In an exemplary manner, the processing unit is specifically configured to determine the bandwidth of the service according to the service type; and according to the link quality level of the PCIe link, select a target PCIe link that satisfies the bandwidth of the service from the multiple PCIe links.

In a third aspect, an embodiment of the present application further provides a system, which includes the PCIe link processing device mentioned in the foregoing embodiments of the present application, and the device in the system can be integrated into a whole machine or device, or the device in the system It can also be provided independently as an element or device.

In a fourth aspect, an embodiment of the present application further provides a terminal, where the terminal includes the PCIe link processing apparatus mentioned in the above embodiment of the present application or any of the above systems.

In a fifth aspect, an embodiment of the present application further provides a chip, including at least one processor, at least one display screen, and an interface; the interface is used to provide program instructions or data for at least one processor; at least one processor is used to execute program lines instructions to implement the first aspect or any method of possible implementations of the first aspect; at least one display screen to implement the steps displayed in the first aspect or any of the possible implementations of the first aspect.

In a sixth aspect, an embodiment of the present application provides a PCIe link selection device, including at least one processor and at least one display screen, and the at least one processor is configured to call a program in a memory to implement the first aspect or any of the first aspect. Any one of the possible implementations; at least one display screen is used to realize the steps of displaying the first aspect or any one of the possible implementations of the first aspect.

In a seventh aspect, an embodiment of the present application provides a PCIe link selection device, including: at least one processor, at least one display screen, and an interface circuit, where the interface circuit is configured to provide information input and/or information output for the at least one processor; At least one processor is used to run code instructions to implement any method in the first aspect or any possible implementation manner of the first aspect; at least one display screen is used to implement any of the first aspect or any possible implementation manner of the first aspect. Shown steps of a method.

In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium, where an instruction is stored in the computer-readable storage medium, and when the instruction is executed, any one of the first aspect or any possible implementation manner of the first aspect is implemented. a method.

It should be understood that the second to eighth aspects of the present application correspond to the technical solutions of the first aspect of the present application, and the beneficial effects obtained by each aspect and the corresponding feasible implementation manner are similar, and will not be repeated.

Description of drawings

FIG. 1 is a schematic structural diagram of a computing device according to an embodiment of the present application;

FIG. 2 is a schematic flowchart of a PCIe link processing method provided by an embodiment of the present application;

3 is a schematic interface diagram of a user-triggered request provided by an embodiment of the present application;

4 is a schematic diagram of an interface for displaying a topology diagram according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a PCIe link switch according to an embodiment of the present application;

FIG. 6 is a schematic interface diagram of a service scheduling failure provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of a PCIe link processing apparatus according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a hardware structure of a PCIe link processing apparatus according to an embodiment of the present application.

Detailed ways

In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish the same or similar items with basically the same function and effect. For example, the first value and the second value are only used to distinguish different values, and do not limit their order. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like are not necessarily different.

It should be noted that, in this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or illustrations. Any embodiment or design described in this application as "exemplary" or "such as" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present the related concepts in a specific manner.

In this application, "at least one" means one or more, and "plurality" means two or more. "And/or", which describes the association relationship of the associated objects, indicates that there can be three kinds of relationships, for example, A and/or B, which can indicate: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A, B can be singular or plural. The character "/" generally indicates that the associated objects are an "or" relationship. "At least one item(s) below" or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (a) of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c may be single or multiple .

In a possible manner of using the PCIe system for service processing, the computing device will randomly select one or more PCIe links for processing the service. However, the actual conditions of each PCIe link in the PCIe system are different, and different link conditions create differences between PCIe links, which leads to the fact that in the actual service transmission scenario, computing devices are randomly selected for the service. For PCIe links, there may be a PCIe link failure or a narrow bandwidth of the PCIe link, which affects the service transmission process. Especially with the wide application of PCIe devices, users have put forward higher usage requirements for PCIe links.

Therefore, an embodiment of the present application provides a PCIe link processing method, which is used for receiving a service processing request, acquiring and displaying a topology diagram of a PCIe system, and after receiving a trigger operation for any one or more PCIe links in the topology diagram In this case, select any one or more PCIe links to process services. This PCIe link processing method can display each PCIe link in the PCIe system through a topology diagram, and select the corresponding PCIe link according to the user's diverse requirements for PCIe links, thereby improving the user's ability to use computing devices to process services. flexibility.

In order to better understand the methods of the embodiments of the present application, the following first describes the computing devices to which the embodiments of the present application are applicable.

The methods of the embodiments of the present application are applicable to computing devices using the PCIe protocol. Exemplarily, FIG. 1 is a schematic structural diagram of a computing device according to an embodiment of the present application. As shown in FIG. 1 , the computing device may specifically include: a software layer 10 and a hardware layer 20 . The software layer 10 includes an operating system (operating system, OS) 101 of a computing device and at least one virtual machine, and FIG. 1 shows a virtual machine 102 as an example. The software layer 10 may further include a basic input output system (Basic Input Output System, BIOS) 103 . A virtual machine monitor (VMM) 1011 and a link processing module 1012 are deployed in the operating system 101 . The hardware layer 20 includes a CPU 201, a memory 202, a root complex 203, a PCIe switch 204, and a PCIe device group 205. The PCIe device group includes one or more PCIe devices. Figure 1 shows two PCIe devices: GPU 2051 and GPU 2052 are shown as examples. GPU 2051 communicates with PCIe switch 204 and GPU 2052 communicates directly with root complex 203.

Wherein, the virtual machine manager 1011 is used to implement the management of virtual machines. In practical applications, the virtual machine manager can be specifically implemented by components such as VMM, libirt, qemu, and nova.

Optionally, the virtual machine manager 1011 may access the PCIe bus system, and query related parameters of each device in the PCIe bus system, such as device identification, hardware specifications, or other related parameters such as the physical address of the device. Specifically, the PCIe bus system may include all devices in the hardware layer 20 shown in FIG. 1 . Among them, each device in the PCIe bus system corresponds to a register. The virtual machine manager 1011 may configure the registers of each device in the PCIe bus system to obtain state information stored in the registers. The status information is used to record information when the device is running, such as whether the device is currently running a fault, data information generated when the device is running, and so on.

Further, the virtual machine manager 1011 can query the topology of the PCIe bus system, and the topology is as follows: the root complex 203 includes a first PCIe link and a second PCIe link, and the first PCIe link includes the PCIe switch 204 and GPU2051, the second PCIe link includes GPU2052. Since the virtual machine manager 1011 can query the device identifiers of all PCIe devices in the PCIe bus system, according to the device identifier of one PCIe device, the device identifiers of other PCIe devices of the PCIe link where the PCIe device is located can be obtained.

The link processing module 1012 is configured to process the PCIe link in the computing device. In practical applications, when the computing device receives a user's trigger operation on any PCIe link, the computing device will select any PCIe link to process the service.

In some examples, the virtual machine manager 1011 and the link processing module 1012 may be provided in the operating system 101 in the form of third-party software, or partially within the operating system 101 and partially outside the operating system 101. This embodiment of the present application Not limited.

Optionally, the link processing module 1012 may also be set in the virtual machine manager 1011, which is not limited in this embodiment of the present application.

The virtual machine 102 may be created by the virtual machine manager 1011 after receiving the virtual machine creation instruction, and the virtual machine creation instruction carries the resource requirements of the virtual machine to be created, and the resource requirements include the processors required by the virtual machine. , hard disk, memory or network and other requirements, also need to include the device identification of the PCIe device in the PCIe device group, such as the device identification of the GPU 2051 in FIG. 1 or the device identification of the GPU 2052, etc., to assign the PCIe device to the virtual machine. use. The number of the virtual machines is not limited. FIG. 1 only uses one virtual machine 102 as an example, which does not constitute a limitation. Correspondingly, after completing the creation of each virtual machine, the virtual machine manager can also save the corresponding relationship between the virtual machine and the PCIe device deployed in the virtual machine, for example, the device identifier of the PCIe device is established in the form of a table. (BDF) and the virtual machine identifier (VM id) of the virtual machine using the PCIe device, etc., so that the subsequent virtual machine manager can determine one or more virtual machines corresponding to the PCIe device according to the corresponding relationship. . Wherein, one PCIe device may correspond to one or more virtual machines, and each virtual machine corresponds to deploying one or more PCIe devices, which is not limited in this embodiment of the present application.

As shown in FIG. 1 , the virtual machine 102 includes a processor GPU 101 ′, a hard disk (not shown in FIG. 1 ), a memory (not shown in FIG. 1 ), a network (not shown in FIG. 1 ), an operating system 1022 and basic inputs The output system (basic input output system, BIOS) 1023. The virtual machine manager 1011 virtualizes the PCIe device to obtain a virtualized PCIe device. For example, GPU 2051' can be obtained by virtualizing GPU 2051 in Figure 1 . The hard disk, memory or network is also obtained by virtual machine manager 1011 by virtualizing corresponding hardware of the computing device, and the operating system 1022 and BIOS 1023 are obtained by simulation by virtual machine manager 1011, which is not limited in this embodiment of the present application.

Each device in the hardware layer 20 can be connected through a PCIe bus to form a PCIe bus system. For example, in FIG. 1 , the CPU 201 , the memory 202 , the root complex 203 , the PCIe switch 204 , the GPU 2051 and the GPU 2052 are connected through a PCIe bus to form a PCIe bus system. The communication link between any two devices in the hardware layer 20 is also referred to as a PCIe link.

The PCIe device group 205 includes at least one PCIe device, and the PCIe device serves as a PCIe endpoint (Endpoint, EP) defined in the PCIe protocol, which may include, but is not limited to, a field-programmable gate array (FPGA), a graphics processor ( graphics processing unit, GPU) and devices such as chips. In FIG. 1 , the GPU 2051 and the GPU 2052 are shown as examples.

Wherein, any PCIe device in the PCIe device group can communicate with the root complex 203 through the PCIe switch 204 . For example, GPU 2051 in FIG. 1 may communicate with root complex 203 through PCIe switch 204. Optionally, the PCIe devices in the PCIe device group may also communicate directly with the root complex 203 , for example, the GPU 2052 in FIG. 1 may directly communicate with the root complex 203 . Optionally, when there are multiple PCIe devices communicating with the PCIe switch, any two PCIe devices in the multiple PCIe devices can communicate with each other through the PCIe switch 204, which is not shown in FIG. 1 .

Further, the root complex 203 is further provided with a root port (root point, RP) 2031 and a root port 2032 , and the PCIe switch 204 is provided with an upstream port 2041 and a downstream port 2042 . The root port 2031 is connected to the upstream port 2041 , the downstream port 2042 is connected to the GPU 2051 , and the root port 2032 is connected to the GPU 2052 . In this embodiment of the present application, the number of PCIe switches is not limited. FIG. 1 shows a PCIe switch 204 as an example. The PCIe switch 204 is connected to a PCIe device group 205 .

In the embodiment of the present application, as shown in FIG. 1 , a PCIe link switch (not shown in FIG. 1 ) may also be included, for controlling the on/off of the PCIe link. The PCIe link switch may be a relay switch that controls the on-off of the PCIe link, a magnetic switch, or a multiplexing switch that controls the on-off of multiple PCIe links. It can be understood that, a specific PCIe link switch is not limited in this embodiment of the present application.

It can be understood that the architecture illustrated in the embodiments of the present application does not constitute a specific limitation on the computing device. In other embodiments of the present application, the computing device may include more or fewer components than shown, or combine some components, or separate some components, or different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The embodiments of the present application are applicable to the above application scenarios for link processing. It can be understood that the embodiment of the present application only provides one application scenario of link processing that can be implemented, and does not limit other specific application scenarios that can implement link processing.

The vocabulary described in the embodiments of the present application will be described below. It can be understood that the description is for explaining the embodiments of the present application more clearly, and does not necessarily constitute a limitation on the embodiments of the present application.

The PCIe described in the embodiments of the present application may be: a high-speed serial computer expansion bus standard, which belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and the connected devices allocate exclusive channel bandwidth, do not share bus bandwidth, and mainly support active Features such as power management, error reporting, end-to-end reliable delivery, hot-plugging, and quality of service. Its main advantage is the high data transmission rate, so it has been widely used in the field of information and communication.

The PCIe link described in the embodiments of this application may refer to a communication channel from one node to another node. The PCIe link in this embodiment is a communication channel used to transmit data in the PCIe system.

The topology diagram described in the embodiments of the present application may refer to a network structure diagram composed of network node devices and communication media. The topology map can describe the network structure more clearly and vividly, which is helpful for network expansion, network troubleshooting or link selection in the future. For example, the PCIe topology diagram may be a tree diagram showing the cascaded structure of the PCIe system.

The bandwidth described in this embodiment of the present application may be: the amount of data that can pass through the link per unit time, and may be used to identify the data transmission capability.

The high performance computing (high performance computing, HPC) described in the embodiments of the present application may be: a branch of computer science, which mainly refers to the technology of researching and developing high performance computers from the aspects of architecture, parallel algorithm and software development. It can generally refer to computing systems and environments that use many processors (as part of a single machine) or several computers organized in a cluster (operating as a single computing resource).

The PCIe system described in the embodiments of this application may be a system composed of a PCIE device in a single computing device, or a system composed of multiple computing devices.

The technical solutions of the present application and how the technical solutions of the present application solve the above-mentioned technical problems will be described in detail below with specific examples. The following specific embodiments can be implemented independently or combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

Exemplarily, FIG. 2 is a schematic flowchart of a PCIe link processing method provided by an embodiment of the present application. As shown in Figure 2, the method may include the following steps:

S201. Receive a service processing request.

In this embodiment of the present application, the service processing request may be a request generated based on a user's triggering operation on the service and used to request the computing device to process the service.

Exemplarily, when the user places the service in the specified window area through a trigger operation, or when the service is placed on a specified node, the service processing request can be sent, and the computing device can receive the service in response to the user's trigger operation. Process the request.

The user's trigger operation may include a single click operation, a multiple click operation, a touch operation (the touch information of the touch operation may include other types of touch information such as touch coordinates, touch strength or time stamp of the touch operation), sliding operation , drag operations, and/or long press operations. It can be understood that, the specific trigger operation is not limited in the embodiment of the present application.

Exemplarily, FIG. 3 is a schematic interface diagram of a user-triggered request provided by an embodiment of the present application.

As shown in FIG. 3 , the interface may include other windows such as a service processing window 301 and a topology display window 302 . The service processing window 301 may include: a service upload control 303 and a service requirement control 305 and other functional controls. The service upload control 303 may be used to trigger service upload, and the service requirement control 305 may be used to receive user input for setting parameters of the service. The service display window 302 may include other controls such as the CPU control 304.

The method of dragging and uploading services is determined according to the different types of services that the user needs to process. Wherein, when the computing device recognizes that the service type is related to a non-root node, it can drag the service to the service upload control 303 or drag the service to the service processing window 301; when the computing device recognizes that the service type is related to the root node When the node is related, the service can be dragged and dropped into the CPU control 304 . The non-root node service represents that the service is transmitted between devices; the root node service represents that the service is transmitted between the CPU and the device.

Exemplarily, when the user needs to process non-root node services such as video service, image service or text service, the video service, image service or text service can be dragged and dropped to the service upload control 303 or the service processing window 301; When processing root node services such as high-performance computing services, the main program corresponding to the service can be dragged and dropped to the CPU control 304 .

In a possible implementation manner, when the user triggers the business requirement control 305, an interface for configuring parameters corresponding to the business requirement control can be displayed, and the user can enter the parameters required for the business scheduling process in the interface, such as the business scheduling requirements. bandwidth and other parameters.

Exemplarily, as shown in FIG. 3 , when the user triggers the service requirement control 305 , the computing device may pop up a service requirement window 3051 in the interface shown in FIG. 3 in response to the user's trigger operation. The user can input the execution time of the service in the pending input 3052 in the service requirement window 3051, the response time of the service in the pending input 3053, or input parameters such as the required bandwidth of the service in the pending input 3054. The computing device can perform adaptive processing on the service by using the parameters required by the service set by the user.

It should be noted that the operation interface of the computing device shown in FIG. 3 above is only used as an example, and does not constitute a limitation to the embodiments of the present application. In other feasible implementation manners, the interface for triggering the service processing request may also be The user operation in this embodiment of the present application is received.

S202. Obtain a first topology diagram of the PCIe system.

In the embodiment of the present application, the first topology diagram includes multiple PCIe links in the PCIe system, and the PCIe link may include device nodes and communication relationships between devices. The specific form is not limited.

In a possible implementation manner, the first topology map may be a topology map obtained after link scanning is performed on the PCIe system.

Exemplarily, the method for obtaining the first topology map of the PCIe system may be: using a UNIX-like operating system (linux), query the PCIe device scanned on the PCIe system through a system command (lspci –v –t), and the execution result will be in the form of: All PCIe devices in the system are displayed in the form of a tree, and a first topology diagram of the PCIe system is obtained, where the first topology diagram includes multiple PCIe links in the PCIe system.

In another possible implementation manner, the first topology map may be: a topology map obtained after link scanning is performed on the PCIe system, and a first topology map obtained by further adjusting the topology map.

For example, the first topology map may be obtained by performing adaptive link adjustment on the topology map according to service requirements, and the specific form of the adjustment is not limited in this embodiment of the present application.

It can be understood that the method for obtaining the first topology map of the PCIe system may also include other contents according to actual application scenarios, and other methods for obtaining the first topology map of the PCIe system are not limited in this embodiment of the present application.

S203. Display an interface including the first topology map.

In this embodiment of the present application, after obtaining the first topology map, the computing device may automatically display an interface including the first topology map, or the computing device may display an interface including the first topology map based on a user's instruction, and so on.

Exemplarily, FIG. 4 is a schematic diagram of an interface for displaying a topology map according to an embodiment of the present application.

As shown in FIG. 4, the topology display window 302 in the interface can display the first topology diagram of the PCIe system, and the first topology diagram may include: the CPU 304 (which can be used as the root node of the PCIe system), the PCIe switch 401, PCIe switch 402 , PCIe switch 403 , PCIe switch 404 , PCIe switch 405 , and PCIe switch 406 . The PCIe switch 402 mounts the PCIe device 415; the PCIe switch 403 mounts the PCIe device 406; the PCIe switch 404 mounts the PCIe device 410 and the PCIe device 411; the PCIe switch 405 mounts the PCIe device 412, the PCIe device 413 and the PCIe device 414; the PCIe switch 406 mounts the PCIe device 407, the PCIe device 408, and the PCIe device 409, and the devices are connected by line segments.

In a possible way, in the interface shown in FIG. 4, when the user wants to process the video service, the video service can be dragged and dropped to the service upload control 303 or the service upload window 301, and the user can trigger the service. The demand control 305 is to input the parameters required for the service scheduling into it. The computing device receives the user's trigger operation, and parses the PCIe device required for processing the service.

In the interface shown in FIG. 4 , the computing device resolves that the video service needs to be processed in the PCIe device 406 . The computing device will recommend two appropriate PCIe links for the service based on the type of video service and the link quality level of the PCIe link that can handle the service. Including an optimal PCIe link (CPU304-PCIe switch 401-PCIe switch 403-PCIe device 406) with a higher link quality level and marked with a dark color, and a link level slightly lower than the optimal PCIe link PCIe link (CPU304-PCIe switch 401-PCIe switch 404-PCIe device 406). It can be understood that the computing device may recommend one or more PCIe links for the user, and the recommended number of PCIe links is not limited in this embodiment.

In a possible way, in the interface shown in FIG. 4, when the user wants to process the high-performance computing service, he can drag the main program of the service to the CPU 304, and the user can trigger the service requirement control 305, and the processing will be processed. The parameters required by the high-performance computing business are entered in it. The main program of the high-performance computing service includes a scheduler. The scheduler is used to interact with scheduling software in other servers. In the scenario of processing high-performance computing services, the PCIe device in FIG. 4 may be a server that complies with the PCIe protocol. The server includes a scheduling software client (or an agent program), and the scheduling software client can communicate with the main program. The scheduler interacts, so that the main program can get the status of all servers on the PCIe link. The main program can determine the servers required for the high-performance computing and the specific processing content in each server. Subsequently, the link processing can be performed by using the method provided in this embodiment. Exemplarily, the services scheduled by using the PCIe link may include: rich media, streaming media, text, simple computing or high-performance computing or other services. It can be understood that, the embodiments of the present application do not limit services.

S204. In the case of receiving a trigger operation for any PCIe link in the first topology diagram, use any PCIe link to process the service corresponding to the service processing request.

In this embodiment of the present application, when the user triggers any PCIe link in the first topology map by clicking, dragging, pressing, or sliding in the first topology map, the user's Triggering the operation, the computing device will use the PCIe link triggered by the user to process the service corresponding to the service processing request. For example, a PCIe link switch or a PCIe register may be used to control the on/off of the PCIe link, so that any one of the PCIe links can be used to process services.

Exemplarily, in the interface shown in FIG. 4, the interface displays two PCIe links recommended for the user, when the user selects the optimal PCIe link (CPU304-PCIe switch) marked with a dark color by dragging and dropping. 401-PCIe switch 403-PCIe device 406), the computing device can use the PCIe link switch or the PCIe register to disconnect the link between the CPU 304 and the PCIe switch 402, and the link between the PCIe switch 401 and the PCIe switch 404 , the service can be scheduled along the optimal PCIe link identified by the dark color, so that the service can be processed in the PCIe device 406 .

In a PCIe link processing method provided by an embodiment of the present application, a computing device can receive a service processing request, obtain and display a topology diagram of a PCIe system, so that a user can flexibly select a link for service transmission in an interface according to requirements, In the case that the computing device receives the trigger operation for any PCIe link in the topology diagram, the computing device processes the service corresponding to the service processing request by using any PCIe link. In the embodiment of the present application, the user can select the PCIe link according to the requirements, so the diversified usage requirements of the user for the PCIe link can be met.

On the basis of the embodiment corresponding to FIG. 2 , in a possible implementation manner, S202 includes: obtaining a second topology diagram of the PCIe system; determining a target device required for processing services; adding a target device to the second topology diagram Redundant equipment, to obtain the first topology diagram.

In this embodiment of the present application, the redundant device may be a replaceable device added by the computing device to the target device required for processing the service. For example, when the target device fails, the computing device can use the PCIe link formed by the redundant device to transmit services. Scan the PCIe system to obtain the first topology map formed by adding redundant devices. The user can then use the interface displaying the first topology diagram to select an appropriate PCIe link to transmit services.

Exemplarily, in the interface of the topology diagram shown in FIG. 4 , the computing device may determine, according to the service, that the target devices required for processing the service are the PCIe device 406 , the PCIe switch 401 , and the PCIe switch 403 . The computing device may add a redundant device to the PCIe switch 401 in the target device, and the redundant device may be the PCIe switch 404 .

When the service is transmitted through the PCIe link (CPU304-PCIe switch 401-PCIe switch 403-PCIe device 406), and the computing device detects that the PCIe switch 401 is faulty, it can trigger the redundant device (PCIe switch 404), and the service can be The faulty device is replaced with the PCIe switch 404, and the computing device will utilize another PCIe link (CPU304-PCIe switch 401-PCIe switch 404-PCIe device 406) to transmit traffic. Scan the PCIe system after adding redundant devices, and obtain the interface of the first topology diagram as shown in FIG. 4 .

Based on this, the redundant device can replace the function of the target device when the target device fails, complete the service transmission, reduce the impact of the device failure on the service processing, and improve the availability of the PCIe system.

On the basis of the embodiment corresponding to FIG. 2 , in a possible implementation manner, adding redundant devices to the target device in the second topology diagram, and obtaining the first topology diagram includes: in the second topology diagram, disconnecting redundant devices Part of the link relationship between the redundant device and other devices, and the redundant device is used as the backup device of the target device.

In this embodiment of the present application, the other device is a device different from the target device. The method for disconnecting part of the link relationship between the redundant device and other devices may be: using the PCIe link switch to control the on/off of the PCIe link between the devices in the PCIe system, or using the PCIe register to change the PCIe register The configuration of the ports in the PCIe system controls the opening and closing of the ports of the devices in the PCIe system.

Exemplarily, in the interface of the topology diagram shown in FIG. 4 , the computing device may use the PCIe switch 404 as a redundant device of the PCIe switch 401 . When the computing device detects that the PCIe switch 401 is faulty, it can trigger the PCIe switch to act as a redundant device of the PCIe switch 401 . The computing device may disconnect the link relationship between the PCIe link (CPU304-PCIe switch 404) through the PCIe link switch, or change the configuration of the PCIe register to close the port for transmission between the PCIe switch and the CPU304.

Based on this, it is possible to add redundant links to the target device by disconnecting the link relationship between the target pen and other devices, reduce the impact of device failures on service processing, and thus increase security for service transmission.

On the basis of the embodiment corresponding to FIG. 2 , in a possible implementation manner, determining the target device required for processing the service includes: determining the target device required for processing the service according to the service type of the service.

In this embodiment of the present application, the service type may include one or more of the following: a data type of the service, a protocol of the service, or other service types such as parameters of the service. The parameters of the service are parameters required when the service is scheduled. The parameters of the service may include one or more of the following parameters: the execution time requirement of the service, the response requirement of the service, or the required bandwidth of the service and other service parameters. The execution time requirement of the service is the time required for scheduling the service. The response requirement of the service is the time required for the computing device to receive the service scheduling request after triggering the processing request of the service. The required bandwidth of the service is the bandwidth required for running the service.

The method for determining the target device required for processing the service according to the service type of the service may be: performing a service modeling on the service according to the service type of the service, and using the service modeling to determine the target device required for processing the service. The business modeling method can utilize other methods such as mathematical modeling or neural network model, which can determine the target device required by the business. It can be understood that the method for determining the target device required by the service according to the service type may include other contents according to the actual application scenario, which is not limited in this embodiment of the present application.

Based on this, the target device required for processing the service can be directly obtained according to numerous parameters obtained from the service, so that the computer can use the target device to perform other link processing.

On the basis of the embodiment corresponding to FIG. 2 , in a possible implementation manner, the first topology diagram includes: link quality levels of multiple PCIe links, and/or link attributes of multiple PCIe links .

In this embodiment of the present application, the link quality level of the PCIe link is a level set for evaluating the quality of the PCIe link. The link properties of the PCIe link can display the link status of the PCIe link. The link attribute of the PCIe link includes one or more of the following: the connection status of the PCIe link, the cascading relationship of the PCIe link, the bandwidth of the PCIe link, or the number of devices of the PCIe link.

The connection status of the PCIe link indicates whether the current PCIe link can transmit services. If the current connection status of the PCIe link is normal, it indicates that the current PCIe link can transmit services; if the current PCIe link is capable of transmitting services If the connection status of the channel is faulty, it means that the current PCIe link cannot transmit services. The cascading relationship of the PCIe link is the path formed by the devices through which the service data passes when the service is transmitted. The bandwidth of the PCIe link represents the amount of data that can be transmitted by the PCIe link in a unit time. The number of devices on the PCIe link is the number of devices on the PCIe link through which service data passes during service transmission. Wherein, the link attribute of the PCIe link can be read from the PCIe register.

Based on this, users can see not only the topology of the current PCIe system, but also the link properties of each PCIe link on the interface, and can visually display the current state of the PCIe system.

On the basis of the embodiment corresponding to FIG. 2 , in a possible implementation manner, the link quality levels of the multiple PCIe links are determined according to the link attributes of the multiple PCIe links; wherein, in the interface, each PCIe link The displayed status is related to the PCIe link quality level.

In this embodiment of the present application, the method for determining the link quality level according to the link attribute may be: modeling the acquired link attributes of multiple PCIe links, or determining according to the link level scoring table of the PCIe link Link quality level of multiple PCIe links. The rules for determining the link quality level of the PCIe link according to the link attribute of the PCIe link can be followed: the higher the bandwidth of the PCIe link, the fewer the number of devices in the PCIe link, and the higher the path of the cascading relationship of the PCIe link. Shorter, the less bandwidth attenuation of the PCIe link, the higher the link quality level of the PCIe link.

In a possible implementation manner, the obtained link attributes of multiple PCIe links may be modeled to determine the link quality of the PCIe links.

Exemplarily, the link quality of the PCIe link may be determined by using a machine learning model. Use the obtained link attributes of multiple PCIe links as the samples required for training the machine learning model; input the samples into the machine learning model, and output the link quality of the PCIe link; use the loss function to compare the output of the model The gap between the link quality of the predicted PCIe link and the link quality of the real PCIe link; when the gap between the link quality of the predicted PCIe link and the link quality of the real PCIe link does not satisfy the loss function, then Adjust the parameters of the model and continue training; until the difference between the link quality of the output PCIe link and the link quality of the real PCIe link satisfies the loss function, then the model training ends, and a machine that can determine the link quality of the PCIe link is obtained Learning models. Then, the model can be used to output the link quality level of the PCIe link.

In a possible implementation manner, the link quality of the PCIe link may be determined according to the obtained link attributes of the multiple PCIe links by comparing with the link level scoring table of the PCIe link.

Exemplarily, as shown in Table 1, the link rating table may include parameters of multiple PCIe links, and the parameters may include: link number, link description, link depth, and link bandwidth of the PCIe link. , number of devices, link quality and/or link quality level and other link parameters. The link level scoring table may be obtained according to statistical calculation of historical data of PCIe link service transmission stored in the computing device. The historical data may include data such as parameters of the PCIe link during service transmission, service transmission time, and service response time. Exemplarily, when there is a PCIe link (SwitchA->SwitchA->End C1) in the topology diagram, it is possible to obtain the link quality of the PCIe link as excellent and the link quality level by looking up the link level score table. for SS. It can be understood that the parameters in the link level scoring table of the PCIe link may include other contents according to actual application scenarios, which are not limited in this embodiment of the present application.

Table 1

Exemplarily, the service type may be that after the computing device acquires link attributes of multiple PCIe links, the parameter information of the link attributes may be input into the link level scoring table. The link level scoring table will compare various parameter information in the input link attribute with the parameter information of the link recorded in the link level scoring table, and determine the link quality level for the PCIe link corresponding to the parameter information .

It can be understood that the method for determining the link quality level according to the link attribute may also include other contents according to the actual application scenario, which is not limited in this embodiment of the present application.

Based on this, the link quality level of the link quality of the PCIe link that can be visually represented can be obtained according to various parameters of the complex link attribute of the PCIe link, so as to realize the visualization of the link quality level of the PCIe link.

On the basis of the embodiment corresponding to FIG. 2 , in a possible implementation manner, the display state of the PCIe link may include: the color of the PCIe link, the size of the PCIe link, and/or the grayscale of the PCIe link, etc. . The color of the PCIe link can be, in the interface for displaying the topology diagram, different types of service scheduling processes can be displayed by using different colors of the PCIe link.

Exemplarily, when using the PCIe link to schedule video services, text services, and image services at the same time, the PCIe link through which the video service is transmitted can be displayed in red, and the PCIe link through which the text service is transmitted can be displayed in green. The PCIe link through which the text traffic is transmitted is shown in yellow.

The size of the PCIe link, in the interface displaying the topology diagram, the different widths of the connecting lines between devices can be used to indicate the link quality level of the PCIe link, and the link quality level of each PCIe link can correspond to different PCIe links dimensions of the road. Exemplarily, when the link quality level of the PCIe link is excellent, the connection line of the PCIe link is displayed as wider; when the link quality level of the PCIe link is good, the connection line of the PCIe link is displayed as wider. narrow. In an actual application scenario, when the link quality levels of the PCIe links are the same, the connecting lines of the PCIe links display the same width of the connecting lines.

The grayscale of the PCIe link may be, and the PCIe link may also use grayscale of different depths to represent the link quality level of the PCIe link. Exemplarily, when the link quality level of the PCIe link is excellent, the grayscale displayed by the connection line of the PCIe link is darker; when the link quality level of the PCIe link is good, the connection of the PCIe link is Lines appear lighter in gray. In a practical application scenario, when the link quality levels of the PCIe links are the same, the grayscales displayed by the connecting lines of the PCIe links are the same.

It can be understood that the display state of the PCIe link may include other contents according to an actual application scenario, which is not limited in this embodiment of the present application.

Based on this, the user can intuitively see the link quality levels of different PCIe links on the interface where the topology map is located, so that the user can select the desired PCIe link scheduling service in the future.

On the basis of the embodiment corresponding to FIG. 2 , in a possible implementation manner, S204 includes: using a link switch in the PCIe system to schedule services to any PCIe link for processing; register to schedule services to any PCIe link for processing.

In this embodiment of the present application, a link switch (or referred to as a PCIe link switch) of a PCIe system may be used to input 0 or 1 to a pin of a hardware device controlled by the PCIe link switch. Wherein, 1 indicates that the circuit of the PCIe link switch is closed to control the path state of the PCIe link, and 0 indicates that the circuit of the PCIe link switch is disconnected and controls the open circuit state of the PCIe link. The PCIe link switch may be a relay switch, a magnetic switch and other switches that control the link on and off.

Exemplarily, FIG. 5 shows a schematic diagram of a PCIe link switch. The on-off of the PCIe link switch can be controlled by a complex programmable logic device (Complex Programming Logic Device, CPLD), and further, the PCIe link switch can control the on-off state of the PCIe link. It can be understood that the PCIe link switch may include other contents according to different actual application scenarios, and the type of the PCIe link switch is not limited in this embodiment of the present application.

In a possible implementation manner, the configuration parameters of the registers in the PCIe system can be changed to control the opening and closing states of each device port in the PCIe system, thereby controlling the on-off of the PCIe link.

Based on this, when the PCIe link needs to be adjusted, a more appropriate link processing method can be selected according to the actual scenario.

On the basis of the embodiment corresponding to FIG. 2 , in a possible implementation manner, when the trigger operation is not received within a preset time, the service type of the service and the link quality level of the multiple PCIe links are used, Select the target PCIe link for the service.

In the embodiment of the present application, when the computing device receives the trigger operation of the user within the preset time, the link processing method provided in the embodiment of the present application may be executed. The method for determining the target PCIe link according to the service type and the link quality level of the PCIe link can be selected for the service according to the service parameters such as the bandwidth required during the service scheduling operation, the service execution time requirement, the service response requirement and so on. A suitable PCIe link.

Based on this, the preset time for receiving the user-triggered operation set in the computing device can optimize the delay and reduce the energy consumption of link processing.

On the basis of the embodiment corresponding to FIG. 2 , in a possible implementation manner, using the service type of the service and the link quality levels of multiple PCIe links to select a target PCIe link for the service, including: determining according to the service type The bandwidth of the service; according to the link quality level of the PCIe link, select the target PCIe link that satisfies the bandwidth of the service among multiple PCIe links.

Exemplarily, when the user needs to schedule the video service and the text service, the computing device can analyze the bandwidth required by the video service and the text service. When the computing device parses and obtains that the bandwidth required by the video service is higher than the bandwidth required by the text service, the computing device will select a high-bandwidth PCIe link for the video service according to the link quality level of the PCIe link. Select a lower bandwidth PCIe link for this text service.

In a possible implementation manner, the computing device can also select a corresponding PCIe link for the service according to the priority of the service. Exemplarily, when the user uses the service more frequently, a PCIe link with higher link quality can be matched for the service; when the user uses the service less frequently, a link can be randomly matched for the service. PCIe link in normal state.

Based on this, the method of accurately selecting a PCIe link according to the service bandwidth and PCIe link quality can solve the different requirements for link bandwidth and quality in different business scenarios, improve the availability of the PCIe system, and maximize the value of the PCIe link. .

On the basis of the embodiment corresponding to FIG. 2 , in a possible implementation manner, in the interface of the topology diagram, the user triggers the selection of any PCIe link for service scheduling, and when the PCIe link selected by the user is processing service When a fault occurs during the process, the user can select other normally running PCIe links for service scheduling.

Exemplarily, when the computing device detects that the PCIe link processing the service is faulty, it can send an error report, and pop up a system prompt window 601 as shown in FIG. 6 in the interface where the topology map is located. The content of the prompt window 601 may be: service scheduling fails, please select another PCIe link. The error report can trigger the update of the topology map in the interface, and the computing device will rescan the PCIe link, and use the link processing method provided in this embodiment to recommend an appropriate link again according to the service type for the user to select.

In a possible implementation manner, if the computing device does not receive a triggering operation for the user to select a link within a preset time, the computing device will select an optimal PCIe link by default to perform service scheduling.

Based on this, when service scheduling fails, users can select other normal links for scheduling to meet the needs of users to schedule services in multiple scenarios.

On the basis of the embodiment corresponding to FIG. 2 , in a possible implementation manner, in the interface of the topology diagram, the user triggers the selection of any PCIe link for service scheduling, and when the user adds a service that needs to be scheduled, the computing device Corresponding to the user's triggering operation for adding a service, another appropriate PCIe link is selected for the added service to schedule the added service.

Exemplarily, in the interface shown in FIG. 4 , the user can expand the service processing window 301 and drag and drop the added service into the service processing window 301 . In response to the user's triggering operation, the computing device may recommend a suitable PCIe link for the added service, and the PCIe link will be identified with a color, size and grayscale different from the PCIe link that has been scheduled for services. The link processing method performed by the computing device in response to the user-triggered operation will not be described again.

Based on this, when the user wants to increase the demand for scheduling services, they can drag and drop the service onto the interface to meet the needs of users for scheduling services in multiple scenarios.

The methods of the embodiments of the present application are described above with reference to FIG. 1 to FIG. 6 , and the apparatuses provided by the embodiments of the present application for executing the above methods are described below. It should be readily appreciated by those skilled in the art that methods and apparatus may be combined and referenced with each other.

The following is an example of dividing each function module corresponding to each function to illustrate:

As shown in FIG. 7 , FIG. 7 shows a schematic structural diagram of a PCIe link processing apparatus provided by an embodiment of the present application.

The PCIe link processing apparatus may be the terminal device in the embodiment of the present application, or may be a chip or a chip system in the terminal device. The PCIe link processing apparatus includes: a display unit 701 and a processing unit 702, wherein the processing unit 702 is used to receive a service processing request; the processing unit 702 is used to obtain a first topology diagram of the PCIe system; the first topology diagram includes A plurality of PCIe links in the PCIe system; the display unit 701 is used to display an interface including the first topology map; the processing unit 702 is used to receive a trigger operation for any PCIe link in the first topology map. In this case, use any PCIe link to process the service corresponding to the service processing request.

Exemplarily, taking the PCIe link processing device as a terminal device or a chip or a chip system applied in the terminal device as an example, the display unit 701 is configured to support the PCIe link processing device to perform the display steps in the above embodiments, and the display unit 701 The processing unit 702 is configured to support the PCIe link processing apparatus to perform the processing steps in the above embodiments.

The processing unit 702 may be integrated with the display unit 701, and the processing unit 702 and the display unit 701 may communicate.

In a possible implementation manner, the PCIe link processing apparatus may further include: a storage unit 703 . The storage unit 703 may include one or more memories, and the memories may be devices used for storing programs or data in one or more devices or circuits.

The storage unit 703 can exist independently, and is connected with the processing unit 702 through a communication bus. The storage unit 703 may also be integrated with the processing unit 702 .

Taking the PCIe link processing apparatus as an example of a chip or a chip system of the terminal device in the embodiment of the present application, the storage unit 703 may store the computer execution instructions of the method of the terminal device, so that the processing unit 702 executes the terminal device in the above embodiment. Methods. The storage unit 703 may be a register, a cache or a random access memory (random access memory, RAM), etc., and the storage unit 703 may be integrated with the processing unit 702 . The storage unit 703 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, and the storage unit 703 may be independent of the processing unit 702 .

In an exemplary manner, the processing unit 702 is specifically configured to obtain a second topology diagram of the PCIe system; determine a target device required for processing services; add redundant devices to the target device in the second topology diagram to obtain the first topology diagram. Topology.

In an exemplary manner, the processing unit 702 is specifically configured to, in the second topology diagram, disconnect a partial link relationship between the redundant device and other devices, and use the redundant device as a backup device of the target device; Among them, other devices are different from the target device.

In an exemplary manner, the processing unit 702 is specifically configured to determine the target device required for processing the service according to the service type of the service.

In an exemplary manner, the service type includes one or more of the following: the data type of the service, the protocol of the service, or the parameter of the service; the parameter of the service is the parameter required when the service is scheduled.

In an exemplary manner, the parameters of the service include one or more of the following: the execution time requirement of the service, the response requirement of the service, or the required bandwidth of the service.

In an exemplary manner, the first topology diagram includes: link quality levels of multiple PCIe links, and/or link attributes of multiple PCIe links.

In an exemplary manner, the processing unit 702 is specifically configured to determine the link quality levels of the multiple PCIe links according to the link attributes of the multiple PCIe links; The link quality level of the PCIe link is related.

In an exemplary manner, the display state of the PCIe link includes: the color of the PCIe link and/or the size of the PCIe link.

In an exemplary manner, the link attribute of the PCIe link includes one or more of the following: the connection status of the PCIe link, the cascading relationship of the PCIe link, the bandwidth of the PCIe link, or the device of the PCIe link number.

In an exemplary manner, the processing unit 702 is specifically configured to use a link switch in the PCIe system to schedule services to any PCIe link for processing; or, use a register in the PCIe system to schedule services to processing on any PCIe link.

In an exemplary manner, the processing unit 702 is further configured to select a target for the service by using the service type of the service and the link quality level of the multiple PCIe links when the trigger operation is not received within a preset time. PCIe link.

In an exemplary manner, the processing unit 702 is specifically configured to determine the bandwidth of the service according to the service type; according to the link quality level of the PCIe link, select a target PCIe link that satisfies the bandwidth of the service among multiple PCIe links .

In a possible implementation manner, the PCIe link processing apparatus may further include: a communication unit 704 . The communication unit 704 is used to support the interaction between the PCIe link processing apparatus and other devices. Exemplarily, when the PCIe link processing apparatus is a terminal device, the communication unit 704 may be a communication interface or an interface circuit. When the PCIe link processing apparatus is a chip or a chip system in a terminal device, the communication unit 704 may be a communication interface. For example, the communication interface may be an input/output interface, a pin or a circuit, or the like.

FIG. 8 is a schematic diagram of a hardware structure of a PCIe link processing apparatus according to an embodiment of the present application.

As shown in FIG. 8 , the network management apparatus includes: a memory 801 , a processor 802 and a display screen 804 . The communication device may further include an interface circuit 803, wherein the memory 801, the processor 802, the interface circuit 803 and the display screen 804 can communicate; exemplarily, the memory 801, the processor 802, the interface circuit 803 and the display screen 804 can communicate through Bus communication, the memory 801 is used to store computer execution instructions, controlled and executed by the processor 802, and displayed by the display screen 804, thereby realizing the split-screen display method provided by the following embodiments of the present application.

In a possible implementation manner, the computer-executed instructions in the embodiments of the present application may also be referred to as application code, which is not specifically limited in the embodiments of the present application.

Optionally, the interface circuit 803 may further include a transmitter and/or a receiver. Optionally, the above-mentioned processor 802 may include one or more CPUs, and may also be other general-purpose processors, digital signal processors (digital signal processors, DSPs), application specific integrated circuits (application specific integrated circuits, ASICs), and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps in combination with the method disclosed in the present application can be directly embodied as executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

Embodiments of the present application also provide a computer-readable storage medium. The methods described in the above embodiments may be implemented in whole or in part by software, hardware, firmware or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media can include both computer storage media and communication media and also include any medium that can transfer a computer program from one place to another. The storage medium can be any target medium that can be accessed by a computer.

In one possible implementation, the computer-readable medium may include RAM, ROM, compact disc read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or a Any other medium or the required program code in the form of instructions or data structures and can be accessed by the computer. Also, any connection is properly termed a computer-readable medium. For example, if you use coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies (such as infrared, radio, and microwave) to transmit software from a website, server, or other remote source, coaxial Cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc, laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The embodiments of the present application are described with reference to flowcharts and/or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. It will be understood that each flow and/or block in the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processing unit of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processing unit of the computer or other programmable data processing device produce Means for implementing the functions specified in a flow or flow of a flowchart and/or a block or blocks of a block diagram.

The present application describes multiple embodiments in detail with reference to multiple flowcharts, but it should be understood that the related descriptions of these flowcharts and their corresponding embodiments are only examples for ease of understanding, and should not constitute any limitation to the present application. Every step in each flowchart is not necessarily required to be executed, for example, some steps can be skipped. Moreover, the execution sequence of each step is not fixed, nor limited to what is shown in the figures, and the execution sequence of each step should be determined by its function and internal logic.

The multiple embodiments described in this application may be arbitrarily combined or the steps may be executed alternately. The execution sequence of each embodiment and the execution sequence of the steps in each embodiment are not fixed, nor are they limited to the drawings. As shown, the execution sequence of each embodiment and the cross execution sequence of each step of each embodiment should be determined by its functions and inherent logic.

Although the application has been described in conjunction with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made therein without departing from the spirit and scope of the application. Accordingly, this specification and drawings are merely exemplary illustrations of the application as defined by the appended claims, and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of this application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims (17)

1. A processing method for PCIe link of high-speed serial computer expansion bus standard relates to the communication field, and is characterized by comprising the following steps:

receiving a service processing request;

acquiring a first topological graph of a PCIe system; the first topological graph comprises a plurality of PCIe links in the PCIe system;

displaying an interface comprising the first topological graph;

and under the condition that a triggering operation aiming at any PCIe link in the first topological graph is received, processing the business corresponding to the business processing request by utilizing the PCIe link.

2. The method of claim 1, wherein obtaining the first topology map of the PCIe system comprises:

acquiring a second topological graph of the PCIe system;

determining target equipment required for processing the service;

and adding redundant equipment to the target equipment in the second topological graph to obtain the first topological graph.

3. The method according to claim 2, wherein the adding redundant devices to the target device in the second topology map to obtain the first topology map comprises:

in the second topological graph, disconnecting a part of link relations between the redundant equipment and other equipment, and taking the redundant equipment as standby equipment of the target equipment; wherein the other device is a device different from the target device.

4. The method of claim 2 or 3, wherein the determining the target device required for processing the service comprises:

and determining target equipment required for processing the service according to the service type of the service.

5. The method of claim 4, wherein the traffic type comprises one or more of: the data type of the service, the protocol of the service or the parameter of the service; the parameters of the service are parameters required when the service is scheduled.

6. The method of claim 5, wherein the parameters of the service comprise one or more of the following: the execution time requirement of the service, the response requirement of the service or the required bandwidth of the service.

7. A method according to any of claims 1-3, characterized in that said first topology comprises: a link quality level of the plurality of PCIe links, and/or a link attribute of the plurality of PCIe links.

8. The method of claim 7, further comprising:

determining link quality levels of the PCIe links according to the link attributes of the PCIe links;

and in the interface, the display state of each PCIe link is related to the link quality grade of the PCIe link.

9. The method of claim 8, wherein the display status of the PCIe link comprises: a color of the PCIe link and/or a size of the PCIe link.

10. The method of any of claims 7-8, wherein the link attributes of the PCIe link include one or more of: the connection state of the PCIe link, the cascade relation of the PCIe link, the bandwidth of the PCIe link or the number of devices of the PCIe link.

11. The method according to any of claims 1-10, wherein said utilizing any of the PCIe links to process traffic corresponding to the traffic handling request comprises:

utilizing a link switch in the PCIe system to dispatch the service to any PCIe link for processing;

or, the service is dispatched to any PCIe link for processing by using a register in the PCIe system.

12. The method of claim 1, further comprising:

and under the condition that the triggering operation is not received within the preset time, selecting a target PCIe link for the service by using the service type of the service and the link quality grades of the PCIe links.

13. The method of claim 12, wherein said selecting a target PCIe link for the transaction using the transaction type of the transaction and the link quality level for the plurality of PCIe links comprises:

determining the bandwidth of the service according to the service type;

and selecting a target PCIe link meeting the bandwidth of the service from the PCIe links according to the link quality level of the PCIe link.

14. A PCIe link processing apparatus, comprising: at least one processor for invoking a program in a memory to perform the method of any of claims 1-13 and at least one display for performing the steps displayed in the method of any of claims 1-13.

15. A PCIe link processing apparatus, comprising: at least one processor, at least one display screen, and interface circuitry for providing information input and/or information output to the at least one processor, the at least one processor being configured to perform the method of any of claims 1-13, the at least one display screen being configured to perform the steps displayed in the method of any of claims 1-13.

16. A chip comprising at least one processor, at least one display screen, and an interface;

the interface is used for providing program instructions or data for the at least one processor;

the at least one display screen for performing the steps shown in the method of any one of claims 1-13;

the at least one processor configured to execute the program line instructions to implement the method of any of claims 1-13.

17. A computer-readable storage medium having instructions stored thereon that, when executed, cause a computer to perform the method of any of claims 1-13.

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