CN114264914B - Matrix switch self-test method, matrix switch and automatic test system - Google Patents
Matrix switch self-test method, matrix switch and automatic test system Download PDFInfo
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- CN114264914B CN114264914B CN202111517143.6A CN202111517143A CN114264914B CN 114264914 B CN114264914 B CN 114264914B CN 202111517143 A CN202111517143 A CN 202111517143A CN 114264914 B CN114264914 B CN 114264914B
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Abstract
The application relates to a matrix switch self-checking method, a matrix switch and an automatic test system. The method comprises the steps of carrying out a first fault test on a first node and a second node to judge whether the first node and the second node have faults or not, obtaining a test node group from the matrix when a first fault test result is that the first node and the second node have faults, wherein the test node group comprises a third node and a fourth node, the nodes in the test node group, the first node and the second node are different nodes on the same column of the matrix, and carrying out a second fault test on the first node and the second node through the test node group to determine the fault nodes in the first node and the second node. The application solves the problem that the fault test can not be carried out on the nodes of the high-density matrix switch in the related technology.
Description
Technical Field
The present application relates to the field of matrix switches, and in particular, to a matrix switch self-checking method, a matrix switch and an automatic test system.
Background
The switch network is an important component of the automatic test system, is responsible for controlling the signal flow direction, is a key of interface design for realizing automatic test, and is an important automatic test device for completing signal switching between a plurality of tested objects and a plurality of test instruments. As the number and complexity of the objects to be measured increases, the density requirements for the matrix switch become higher. At present, in the related art, failure test cannot be performed on the node of the high-density matrix switch, so that a specific failure node cannot be determined when the node of the high-density matrix switch fails, and thus the failure node of the high-density matrix switch cannot be maintained in time, and an operator is affected to perform normal work by using the high-density matrix switch, so that how to perform failure test on the node of the high-density matrix switch becomes a problem to be solved urgently.
Disclosure of Invention
The application provides a matrix switch self-checking method, a matrix switch and an automatic testing system, which are used for solving the problem that the failure test cannot be carried out on the nodes of a high-density matrix switch in the related technology.
The application provides a matrix switch self-checking method, which comprises the steps of carrying out a first fault test on a first node and a second node to judge whether the first node and the second node have faults or not, obtaining a test node group from a matrix when a first fault test result is that faults exist, wherein the test node group comprises a third node and a fourth node, the nodes in the test node group, the first node and the second node are different nodes on the same column of the matrix, and carrying out a second fault test on the first node and the second node through the test node group to determine the fault nodes in the first node and the second node.
The application provides a matrix switch, which is applied to the self-checking method of the matrix switch in the first aspect, and comprises a matrix component, a relay component and an analog-to-digital converter, wherein the row and the column of the matrix component are respectively greater than or equal to 4, the relay component is used for controlling the closing or opening of a loop where a node is located, the analog-to-digital converter is respectively connected with the matrix component and the relay component, and the analog-to-digital converter is used for converting the on voltage or the off voltage of a test loop into data quantity and outputting the data quantity.
In a third aspect, the present application provides an automatic test system, which includes the matrix switch of the second aspect, and a controller, where the controller is connected to the matrix switch, and the controller is configured to perform a fault test on the matrix switch.
In a fourth aspect, the present application provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;
A memory for storing a computer program;
and a processor, configured to implement the steps of the matrix switch self-checking method according to any one of the embodiments of the first aspect when executing the program stored in the memory.
In a fifth aspect, there is provided a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the matrix switch self-test method of any one of the embodiments of the first aspect.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
The matrix switch self-checking method comprises the steps of performing a first fault test on a first node and a second node to judge whether the first node and the second node have faults or not, wherein the first node and the second node are of different types, so that fault tests can be performed on the first node and the second node of the matrix switch, when a fault exists as a result of the first fault test, a test node group is obtained from the matrix, the test node group comprises a third node and a fourth node, the nodes in the test node group and the first node and the second node are different nodes on the same column of the matrix, the second fault test is performed on the first node and the second node respectively through the test node group to determine the fault nodes existing in the first node and the second node, the fault test can be performed on the first node and the second node according to the application for the matrix switch, the fault test can be performed on the second node and the matrix switch according to the application for the method, the fault test can be conveniently performed on the second node, the fault test node can not be performed on the first node and the second node, the second node can not be tested on the same column, and the first node and the second node can not be tested, and the second node can be tested on the matrix, and the first node.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of an alternative 4X4 matrix switch according to an embodiment of the present application;
Fig. 2 is a schematic diagram of an off state of a relay assembly of an alternative matrix switch according to an embodiment of the present application;
Fig. 3 is a schematic structural view of a closed state of a relay assembly of an alternative matrix switch according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an alternative mXn matrix switch according to an embodiment of the present application;
FIG. 5 is a schematic flow chart of an alternative matrix switch self-checking method according to an embodiment of the present application;
FIG. 6 is a schematic flow chart of another alternative matrix switch self-checking method according to an embodiment of the present application;
FIG. 7 is a schematic flow chart of another alternative matrix switch self-checking method according to an embodiment of the present application;
FIG. 8 is a schematic flow chart of another alternative matrix switch self-checking method according to an embodiment of the present application;
FIG. 9 is a schematic flow chart of another alternative matrix switch self-checking method according to an embodiment of the present application;
FIG. 10 is a schematic flow chart of another alternative matrix switch self-checking method according to an embodiment of the present application;
FIG. 11 is a schematic flow chart of another alternative matrix switch self-test method according to an embodiment of the present application;
FIG. 12 is a schematic flow chart of another alternative matrix switch self-test method according to an embodiment of the present application;
fig. 13 is a schematic structural diagram of an alternative electronic device according to an embodiment of the present application.
Reference numerals:
Matrix assembly 110, node 111, relay assembly 120, analog to digital converter 130, resistor 140.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In order to solve the problems mentioned in the background art, according to an aspect of the embodiments of the present application, there is provided an embodiment of a matrix switch.
Fig. 1 is a schematic structural diagram of an alternative 4X4 matrix switch according to an embodiment of the present application. The matrix switch of the embodiment of the present application may include a matrix assembly 110, a relay assembly 120, and an analog-to-digital converter 130, and the rows and columns of the matrix are equal to 4. The matrix may include a plurality of nodes 111, and any two different kinds of nodes 111 on the same column are used as a first node and a second node to perform a first fault test on the first node and the second node, so as to determine whether the first node and the second node have faults.
In the embodiment of the present application, when the first fault test result indicates that a fault exists, an arbitrary test node group is obtained from the matrix, where the test node group may include a third node and a fourth node, the third node and the fourth node may be different types of nodes 111, the first node and the second node form a first test loop, the relay assembly 120 may be a self-checking relay, and the relay assembly 120 is disposed in the first test loop. When the first test circuit is on, the first node, the second node and the relay assembly 120 are all closed, and when the first test circuit is off, the first node, the second node, the relay and the first node and the second node may be all opened.
In the above embodiment, the first node and the second node may be different types of nodes 111, the second node may be a node 111 connected to the ground line when the first node is a node 111 not connected to the ground line, and the second node may be a node 111 not connected to the ground line when the first node is a node 111 connected to the ground line. Similarly, the third node and the fourth node may be different types of nodes 111, and when the third node is a node 111 not connected to the ground line, the fourth node is a node 111 connected to the ground line, and when the third node is a node 111 connected to the ground line, the fourth node is a node 111 not connected to the ground line.
Fig. 2 is a schematic structural diagram of a closed state of the relay assembly 120 of an alternative matrix switch according to an embodiment of the present application, and fig. 3 is a schematic structural diagram of an open state of the relay assembly 120 of an alternative matrix switch according to an embodiment of the present application. When the relay assembly 120 is closed, the relay assembly 120 is connected to both the first node and the second node, thereby forming a first test loop, and when the relay assembly 120 is opened, the relay assembly 120 is disconnected from both the first node and the second node, and the first test loop is also opened.
It should be noted that, the relay assembly 120 in the embodiment of the present application may be a self-checking relay, when the matrix switch is not self-checked, the relay assembly 120 is in a suspended state, so as to avoid the relay assembly 120 from affecting the function of the matrix switch, and when the matrix switch needs to be self-checked, i.e. the on-off function or the on-resistance of the matrix switch is tested, the relay assembly 120 is connected to the first test loop, so that the matrix switch is self-checked.
In some embodiments of the present application, the rows and columns of the matrix assembly 110 are all greater than or equal to 4, the relay assembly 120 is used for controlling the closing or opening of the loop where the node 111 is located, the analog-to-digital converter 130 is respectively connected to the matrix assembly 110 and the relay assembly 120, and the analog-to-digital converter 130 is used for converting the on voltage or the off voltage of the test loop into the data quantity and outputting the data quantity. According to the matrix switch provided by the embodiment of the invention, the nodes 111 of the matrix can be subjected to fault test without external test equipment, and the problem that the nodes 111 of the high-density matrix switch cannot be subjected to fault test in the related technology is solved.
Fig. 4 is a schematic structural diagram of an alternative mXn matrix switch according to an embodiment of the present application. The row m of the matrix switch is greater than or equal to 4, the column n is greater than or equal to 4, any two nodes 111 of the matrix switch are used as a group to be connected with the relay assembly 120, any two nodes 111 are used as a first node and a second node, the first node and the second node are different nodes 111 on the same column of the matrix, and the first node and the second node are different types of nodes 111. When the first node and the second node need to be subjected to fault test, the relay assembly 120, the first node and the second node are closed, a preset voltage is input into the first test loop, the conducting voltage in the first test loop is detected, the first node and/or the second node is/are disconnected to obtain the disconnecting voltage of the first test loop, when the conducting voltage is equal to a first preset threshold value and the disconnecting voltage is equal to a second preset threshold value, the first node and the second node are judged to have no faults, and when the conducting voltage is not equal to the first preset threshold value and/or the disconnecting voltage is not equal to the second preset threshold value, the first node and the second node are judged to have faults.
In some embodiments of the present application, when the test result of the matrix switch in the foregoing embodiment indicates that the first node and the second node have a fault, a fault node existing in the first node and the second node may be further specifically determined. Any test node group is obtained from the matrix, wherein the test node group can comprise a third node and a fourth node, the third node and the fourth node are different types of nodes 111, and the test node groups are all fault-free nodes. When the first node is subjected to fault test, the first node and the fourth node are closed, the first node and the fourth node are nodes 111 of different types, meanwhile, the relay assembly 120 connected with the first node is closed, the relay assembly 120 connected with the fourth node is closed, a second test loop is formed, a preset voltage is input into the second test loop, the conduction voltage in the second test loop is detected, the third node and/or the fourth node is disconnected, the disconnection voltage in the second test loop is obtained, when the conduction voltage is equal to a first preset threshold value and the disconnection voltage is equal to a second preset threshold value, the first node is judged to have no fault, and when the conduction voltage is not equal to the first preset threshold value and/or the disconnection voltage is not equal to the second preset threshold value, the first node is judged to have the fault. Similarly, when the second node is subjected to fault test, the second node and the third node are closed, the second node and the third node are nodes 111 of different types, meanwhile, the relay assembly 120 connected with the second node is closed, the relay assembly 120 connected with the third node is closed, so that a third test loop is formed, a preset voltage is input into the third test loop, the conduction voltage in the third test loop is detected, the second node and/or the third node is disconnected, the disconnection voltage in the third test loop is obtained, when the conduction voltage is equal to a first preset threshold value and the disconnection voltage is equal to a second preset threshold value, the second node is judged to have no fault, and when the conduction voltage is not equal to the first preset threshold value and/or the disconnection voltage is not equal to the second preset threshold value, the second node is judged to have the fault.
In the above embodiment, the first node and the second node may be different types of nodes 111, the second node may be a node 111 connected to the ground line when the first node is a node 111 not connected to the ground line, and the second node may be a node 111 not connected to the ground line when the first node is a node 111 connected to the ground line. Similarly, the third node and the fourth node may be different types of nodes 111, and when the third node is a node 111 not connected to the ground line, the fourth node is a node 111 connected to the ground line, and when the third node is a node 111 connected to the ground line, the fourth node is a node 111 not connected to the ground line, which is not particularly limited in the embodiment of the present application.
It should be noted that, when the preset voltage is 3.3V, the first preset threshold is 0V, the second preset threshold is 3.3V, and the preset voltage may be the same as the second preset threshold.
It should be noted that, in this embodiment, whether the first node and the second node have faults may be determined according to the preset voltage and the on voltage, when the preset voltage and the on voltage are the same, it may be obtained that the first node and the second node have no faults, and when the preset voltage and the on voltage are different, it may be obtained that at least one node 111 of the first node and the second node has faults, which is not particularly limited in the embodiment of the present application.
It can be understood that after the fault test of the first node and the second node of the matrix switch in the above embodiment is completed, the fault node results existing in the first node and the second node can be output, so that the fault node can be maintained in time, and the accuracy of the matrix switch is improved. After the first node and the second node are tested, the nodes 111 in the matrix that are not tested may be tested for faults until all the nodes in the matrix are tested.
In some embodiments of the present application, the matrix switch may be an 8×256 matrix switch, that is, the row 8 and the column 256 of the matrix, and the rows and the columns of the matrix switch may be the same or different, which is not specifically limited in the embodiments of the present application.
In some embodiments of the present application, the test circuit may further include a resistor 140, and when a predetermined voltage is input to the test circuit of the matrix, a current is generated in the test circuit, so that the analog-to-digital converter 130 may test a contact resistance between the nodes 111 in the test circuit, and determine whether the working performance of the nodes is normal according to the contact resistance. It will be appreciated that when the voltage and current between the nodes 111 of the matrix switch exceed a certain threshold, the contact resistance between the nodes 111 decreases, which affects the closing and opening functions of the nodes 111, so that it can be determined whether the operation performance of the nodes is normal according to the magnitude of the contact resistance between the nodes 111. In some embodiments, the resistor 140 may have a smaller resistance, for example, 10Ω, so that the analog-to-digital converter 130 may more accurately test the contact resistance between the nodes 111, and avoid the influence of the excessive resistance of the resistor 140 on the calculation of the contact resistance.
According to another aspect of the embodiments of the present application, the present application further provides an embodiment of a matrix switch self-checking method, where the matrix switch self-checking method is applied to the matrix switch of the foregoing embodiment, and performs a fault test on a node 111 of the matrix switch.
As shown in fig. 5, in order to provide a flow chart of an alternative matrix switch self-checking method according to an embodiment of the present invention, a plurality of nodes 111 exist on a matrix of the matrix switch self-checking method in this embodiment, and the plurality of nodes 111 are arranged in an array, and the method may include the following steps:
step S210, a first fault test is performed on the first node and the second node to determine whether the first node and the second node have faults, wherein the first node and the second node are different types of nodes 111;
In the embodiment of the application, a first fault test is performed on the first node and the second node of the matrix switch, wherein the first fault test is used for judging whether the first node and the second node have faults, and the first fault test result can be that the faults exist or not.
Note that, the types of the nodes 111 include a node 111 not connected to a ground line and a node 111 connected to a ground line, and in the above embodiment, the first node and the second node may be different types of nodes 111, and when the first node is the node 111 not connected to the ground line, the second node is the node 111 connected to the ground line, and when the first node is the node 111 connected to the ground line, the second node is the node 111 not connected to the ground line, which is not particularly limited in the embodiment of the present application.
Step S220, when the first fault test result is that a fault exists, a test node group is obtained from the matrix, wherein the test node group comprises a third node and a fourth node, and the nodes in the test node group, the first node and the second node are different nodes 111 on the same column of the matrix;
step S230, performing a second fault test on the first node and the second node through the test node group respectively to determine the fault nodes existing in the first node and the second node.
The matrix switch self-checking method provided in this example can be applied to the matrix switch of the above embodiment, so as to perform fault test on the nodes 111 on the matrix.
It should be understood that, the steps S210, S220 and S230 are all automatically executed steps, so that no external test device is needed when the node 111 of the high-density matrix switch performs fault test, which not only solves the problem that the node 111 of the high-density matrix switch cannot be subjected to fault test, but also improves the convenience of fault test operation.
Note that, the types of the nodes 111 include a node 111 not connected to a ground line and a node 111 connected to a ground line, and in the above embodiment, the third node and the fourth node may be different types of nodes 111, and the fourth node may be a node 111 connected to a ground line when the third node is a node 111 not connected to a ground line, and the fourth node may be a node 111 not connected to a ground line when the third node is a node 111 connected to a ground line, which is not particularly limited in the embodiment of the present application.
In the embodiment of the application, a plurality of nodes 111 exist on a matrix, and the plurality of nodes 111 are arranged in an array, and the self-checking method of the matrix switch in the embodiment of the application comprises the steps of performing a first fault test on a first node and a second node to judge whether the first node and the second node have faults or not, wherein the first node and the second node are different types of nodes 111, so that the first node and the second node of the matrix switch can be subjected to the fault test. When the first fault test result is that a fault exists, a test node group is obtained from the matrix, the test node group comprises a third node and a fourth node, and the nodes 111 in the test node group, the first node and the second node are different nodes 111 on the same column of the matrix. According to the matrix switch self-checking method, the first node and the second node are respectively subjected to the second fault test through the test node group, so that the fault nodes in the first node and the second node can be determined, an operator can maintain the fault nodes in time conveniently, and the fault test can be performed on the node 111 of the high-density matrix switch without external test equipment, so that the problem that the fault test cannot be performed on the node 111 of the high-density matrix switch in the related technology is solved, and the convenience of the fault test on the node 111 of the high-density matrix switch is improved.
As shown in fig. 6, specifically, in the step S210, the first fault test is performed on the first node and the second node to determine whether the first node and the second node have faults, which may be implemented by the following steps S310, S320, S330, S340, S350, and S360:
Step S310, a first test loop formed by a first node and a second node is conducted;
In the embodiment of the present application, as shown in fig. 1, the first node and the second node are both closed, and the relay assembly 120 connected to the first node and the second node is also closed, so that the first test loop formed by the first node and the second node is turned on.
Step S320, inputting a preset voltage into the first test loop, and obtaining the voltage in the first test loop as a conduction voltage;
step S330, judging whether the first node and the second node have faults or not according to the on voltage;
step S340, and/or, disconnecting the first test loop formed by the first node and the second node;
step S350, inputting a preset voltage into the first test loop, and acquiring the voltage in the first test loop as an off voltage;
In the embodiment of the present application, the disconnection voltage in the first test loop may be a voltage in the first test loop obtained by disconnecting the first node, disconnecting the second node, and disconnecting both the first node and the second node. When it is not determined that there is a fault node in the first node and the second node, that is, when fault tests need to be performed on the disconnection functions of the first node and the second node, the voltage of the first test loop should be obtained by disconnecting the first node and the second node, and the voltage is used as the disconnection voltage.
Step S360, judging whether the first node and the second node have faults according to the disconnection voltage.
In some embodiments of the present application, whether the first node and the second node have a fault may be determined according to the on voltage or the off voltage, or whether the first node and the second node have a fault may be determined according to the on voltage and the off voltage at the same time.
Specifically, in the embodiment of the application, a first fault test is performed on the first node and the second node to determine whether the first node and the second node have faults, which may be that a first test loop formed by the first node and the second node is conducted, a preset voltage is input into the first test loop, a voltage in the first test loop is obtained as a conducted voltage, and whether the first node and the second node have faults is determined according to the conducted voltage.
In some embodiments of the present application, a first fault test is performed on the first node and the second node to determine whether the first node and the second node have faults, or a first test loop formed by the first node and the second node is disconnected, a preset voltage is input into the first test loop, a voltage in the first test loop is obtained as a disconnection voltage, and whether the first node and the second node have faults is determined according to the disconnection voltage.
In some embodiments of the present application, a first fault test is performed on a first node and a second node to determine whether the first node and the second node have faults, or the first fault test circuit formed by the first node and the second node is conducted, a preset voltage is input to the first test circuit, a voltage in the first test circuit is obtained as a conducted voltage, the first test circuit formed by the first node and the second node is disconnected, a voltage in the first test circuit is obtained as a disconnected voltage, and whether the first node and the second node have faults is determined according to the conducted voltage and the disconnected voltage.
It should be noted that, in this embodiment, whether the first node and the second node have faults may be determined according to the preset voltage and the on voltage, when the preset voltage and the on voltage are the same, it may be obtained that the first node and the second node have no faults, and when the preset voltage and the on voltage are different, it may be obtained that at least one node 111 of the first node and the second node has faults, which is not particularly limited in the embodiment of the present application.
As shown in fig. 7, specifically, in the step S330, it is determined whether the first node and the second node have faults according to the on voltage, and in the step S360, it is determined whether one node and the second node have faults according to the off voltage, which may be implemented in the step S410:
in step S410, when the on voltage is equal to the first preset threshold and the off voltage is equal to the second preset threshold, it is determined that there is no fault in the first node and the second node, and the first fault test result is that there is no fault.
In some embodiments of the present application, when the on voltage is equal to a first preset threshold and the off voltage is equal to a second preset threshold, it may be determined that there is no fault in the first node and the second node, so as to obtain a first fault test result that there is no fault. It should be noted that, when the preset voltage is 3.3V, the first preset threshold is 0V, the second preset threshold is 3.3V, the preset voltage and the second preset threshold may be the same, when the 3.3V voltage is input into the first test loop formed by the first node and the second node, the obtained on voltage is 0V, and when the off voltage obtained after the first node and the second node are disconnected is 3V, it may be determined that no fault exists in both the first node and the second node, so as to obtain the first fault test result that no fault exists.
As shown in fig. 8, specifically, in the step S330, it is determined whether the first node and the second node have faults according to the on voltage, and in the step S360, it is determined whether one node and the second node have faults according to the off voltage, which may be implemented in the step S510:
In step S510, when the on voltage is not equal to the first preset threshold and/or the off voltage is not equal to the second preset threshold, it is determined that at least one node 111 of the first node and the second node has a fault, and the first fault test result is obtained as the fault.
In some embodiments of the present application, when the on voltage is not equal to the first preset threshold or the off voltage is not equal to the second preset threshold, it may be determined that the first fault test result is a fault, and when the on voltage is not equal to the first preset threshold and the off voltage is not equal to the second preset threshold and is satisfied at the same time, it may also be determined that the first fault test result is a fault, and when the first fault test result is a fault, it may be obtained that at least one node 111 of the first node and the second node has a fault, that is, the first node has a fault or the second node has a fault or the first node and the second node have a fault at the same time. It should be noted that, when the preset voltage is 3.3V, the first preset threshold is 0V, and the second preset threshold is 3.3V, the on voltage is not equal to 0V and/or the off voltage is not equal to 3.3V, it is determined that at least one node 111 of the first node and the second node has a fault, and the first fault test result is obtained as the fault.
As shown in fig. 9, specifically, in step S230, the second fault test is performed on the first node and the second node by using the test node group to determine the fault node existing in the first node and the second node, which may be implemented by the following steps S610, S620, S630 and S640:
step S610, a second test loop formed by the first node and a fourth node is conducted, a preset voltage is input to the second test loop, the voltage of the second test loop is obtained and used as the conducted voltage of the second test loop, the first node and the fourth node are different types of nodes 111, and the fourth node is a fault-free node;
step S620, a third test loop formed by the second node and the third node is conducted, a preset voltage is input to the third test loop, the voltage of the third test loop is obtained and used as the conducting voltage of the third test loop, the second node and the third node are different types of nodes 111, and the third node is a fault-free node;
step S630, when the conduction voltage of the second test loop is not equal to the first preset threshold value, determining that the first node has a fault;
In step S640, when the turn-on voltage of the third test loop is not equal to the first preset threshold, it is determined that the second node has a fault.
In some embodiments of the present application, the first node and the second node may be respectively subjected to a second fault test by the test node group, so that a fault node existing in the first node and the second node may be determined. Specifically, when judging whether the first node has a fault, the second test loop formed by the first node and the fourth node is conducted, and a preset voltage is input into the second test loop to obtain the voltage of the second test loop, where the first node and the fourth node are different nodes 111 on the same column of the matrix and are different types of nodes 111, and the fourth node is a fault-free node.
Note that, the types of the nodes 111 include a node 111 not connected to a ground line and a node 111 connected to a ground line, and in the above embodiment, the first node and the fourth node may be different types of nodes 111, and the fourth node may be a node 111 connected to a ground line when the first node is a node 111 not connected to a ground line, and the fourth node may be a node 111 not connected to a ground line when the first node is a node 111 connected to a ground line, which is not particularly limited in the embodiment of the present application.
It should be noted that, the obtaining of the fourth node may include arbitrarily selecting two different types of nodes 111 in the same column on the matrix to perform the first fault test, if the first fault test result indicates that there is no fault, the two nodes 111 may be used as a test node group, one of the nodes 111 in different types with the first node may be used as the fourth node, and may be obtained according to comparison of the different nodes 111, for example, when the result of arbitrarily selecting two different types of nodes 111 in the same column on the matrix to perform the first fault test with the second node is no fault, one node 111 in different types with the first node is arbitrarily selected from the matrix, and performs the first fault test with the first node, and if the obtained first fault test result also indicates that there is no fault, the arbitrarily selected one node 111 is a non-fault node, thereby obtaining the non-fault node required in this embodiment as the fourth node.
In the embodiment of the application, similarly, when judging whether the second node has a fault, a third test loop formed by the second node and a third node is conducted, a preset voltage is input into the third test loop, the voltage of the third test loop is obtained, and the voltage is taken as the conducted voltage of the third test loop, and it is to be noted that the second node and the third node are different nodes 111 on the same column of the matrix and are different types of nodes 111, and the third node is a fault-free node.
Note that, the types of the nodes 111 include a node 111 not connected to a ground line and a node 111 connected to a ground line, and in the above embodiment, the second node and the third node may be different types of nodes 111, and when the second node is the node 111 not connected to the ground line, the third node is the node 111 connected to the ground line, and when the second node is the node 111 connected to the ground line, the third node is the node 111 not connected to the ground line, which is not particularly limited in the embodiment of the present application.
It should be noted that, the obtaining of the third node may include arbitrarily selecting two different types of nodes 111 in the same column on the matrix to perform the first fault test, if the first fault test result indicates that there is no fault, the two nodes 111 may be used as a test node group, one of the nodes 111 with different types from the second node may be used as the third node, and may be obtained according to comparison of the different nodes 111, for example, when the result of arbitrarily selecting two different types of nodes 111 in the same column on the matrix as the first node and the second node to perform the first fault test is no fault, one node 111 with different types from the second node is arbitrarily selected from the matrix, and performs the fault test with the second node, and if the obtained first fault test result also indicates that there is no fault, the arbitrarily selected one node 111 is a no fault node, thereby obtaining the no fault node required in this embodiment as the third node.
As shown in fig. 10, specifically, in step S230, the second fault test is performed on the first node and the second node by using the test node group to determine the fault node existing in the first node and the second node, which may also be implemented by the following steps S710, S720, S730, and S740:
Step S710, disconnecting a second test loop formed by the first node and a fourth node, inputting a preset voltage to the second test loop, obtaining the voltage of the second test loop as the disconnected voltage of the second test loop, wherein the first node and the fourth node are different types of nodes 111, and the fourth node is a fault-free node;
step S720, disconnecting a third test loop formed by the second node and the third node, inputting a preset voltage to the third test loop, obtaining the voltage of the third test loop as the disconnection voltage of the third test loop, wherein the second node and the third node are different types of nodes 111, and the third node is a fault-free node;
step S730, when the open voltage of the second test loop is not equal to the second preset threshold, determining that the first node has a fault;
in step S740, when the open voltage of the third test loop is not equal to the second preset threshold, it is determined that the second node has a fault.
In some embodiments of the present application, the fault node present in the first node and the second node may also be determined by the open voltages of the second test loop and the third test loop. Specifically, a second test loop formed by the first node and the fourth node is disconnected, a preset voltage is input to the second test loop, the voltage of the second test loop is obtained and used as the disconnection voltage of the second test loop, the first node and the fourth node are nodes 111 of different types, the fourth node is a fault-free node, when the disconnection voltage of the second test loop is not equal to a second preset threshold value, the first node is judged to have a fault, a third test loop formed by the second node and the third node is disconnected, a preset voltage is input to the third test loop, the voltage of the third test loop is obtained and used as the disconnection voltage of the third test loop, the second node and the third node are nodes 111 of different types, and when the disconnection voltage of the third test loop is not equal to the second preset threshold value, the second node is judged to have a fault.
As shown in fig. 11, the matrix switch self-checking method may further include the following step S810 after performing a second fault test on the first node and the second node through the test node group to determine a fault node existing in the first node and the second node, respectively:
and step S810, outputting the fault node result in the first node and the second node when the fault node in the first node and the second node is judged.
In some embodiments of the present application, after the second fault test is performed on the first node and the second node by using the test node group to determine the fault node existing in the first node and the second node, the fault node results existing in the first node and the second node obtained in the second fault test may also be output, so that the fault node existing in the matrix switch may be maintained in time, the accuracy of the closing and opening functions of the matrix switch node 111 is improved, and the normal use of the matrix switch is prevented from being affected due to abnormal closing and opening functions of the matrix switch node 111.
As shown in fig. 12, in the step S230, after performing the second fault test on the first node and the second node by using the test node group to determine the fault node existing in the first node and the second node, the matrix switch self-checking method may further include step S910:
In step S910, two untested nodes 111 are selected from the matrix as the first node and the second node for testing, until all nodes 111 of the matrix are tested.
In some embodiments of the present application, after performing a second fault test on the first node and the second node by using the test node group to determine the fault node existing in the first node and the second node, two untested nodes 111 in the matrix may be selected again as the first node and the second node to perform a test until all the nodes 111 in the matrix are tested. Therefore, according to the matrix switch self-checking method provided by the embodiment of the application, all the nodes 111 of the matrix switch can be tested, so that the accuracy of the matrix switch is further improved.
It should be noted that, the number of the nodes 111 of the high-density matrix switch is large, and the fault test cannot be performed on all the nodes 111 of the high-density matrix switch by using the external test equipment, but the matrix switch self-checking method of the embodiment of the application can perform the fault test on all the nodes 111 of the high-density matrix switch, so that the problem that the fault test cannot be performed on the nodes 111 of the high-density matrix switch in the related technology is solved, and the embodiment of the application can perform the fault test on the nodes 111 of the high-density matrix switch without the external test equipment, thereby improving the convenience of performing the fault test on the nodes 111 of the high-density matrix switch.
According to another aspect of the embodiment of the present application, an automatic test system is provided, where the automatic test system includes the matrix switch of any one of the above embodiments, and a controller, where the controller is connected to the matrix switch, and the controller is configured to perform a fault test on the matrix switch 111.
According to another aspect of the embodiment of the present application, an electronic device is provided in an embodiment of the present application, as shown in fig. 13, where the electronic device includes a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus. The electronic device includes, but is not limited to:
A memory for storing a computer program;
The processor is used for executing the program stored in the memory, and when the processor executes the computer program stored in the memory, the processor is used for executing the matrix switch self-checking method.
The memory is used as a non-transitory computer readable storage medium for storing non-transitory software programs and non-transitory computer executable programs, such as the matrix switch self-test method described in the embodiments of the present application. The processor is used for realizing the matrix switch self-checking method by running a non-transient software program and instructions stored in the memory.
The memory may include a memory program area for storing an operating system, an application program required for at least one function, and a memory data area for storing a matrix switch self-checking method as described above. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The non-transitory software programs and instructions required to implement the matrix switch self-test method described above are stored in the memory and when executed by the one or more processors, the matrix switch self-test method described above is performed, for example, method steps S210 through S230 described in fig. 5, method steps S310 through S360 described in fig. 6, method steps S310 through S340 and S410 described in fig. 7, method steps S310 through S340 and S510 described in fig. 8, method steps S210, S220 and S610 through S640 described in fig. 9, method steps S210, S220 and S710 through S740 described in fig. 10, method steps S210 through S230 and S810 described in fig. 11, and method steps S210 through S230 and S910 described in fig. 12.
The memory and the processor in the electronic device communicate with the communication interface through a communication bus. The communication bus may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, or the like. The communication bus may be classified as an address bus, a data bus, a control bus, or the like.
The processor may be a general-purpose processor including a central Processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), a digital signal processor (DIGITAL SIGNAL Processing, DSP), an Application Specific Integrated Circuit (ASIC) SPECIFIC INTEGRATED Circu it, a Field-Programmable GATE ARRAY, or other Programmable logic device, discrete gate or transistor logic device, or discrete hardware component.
The embodiment of the invention also provides a storage medium which stores computer executable instructions for executing the matrix switch self-checking method.
In an embodiment, the storage medium stores computer-executable instructions that are executed by one or more control processors, for example, by one of the processors in the electronic device, and may cause the one or more processors to perform the matrix switch self-checking method described above, for example, performing the method steps S210 to S230 described in fig. 5, the method steps S310 to S360 described in fig. 6, the method steps S310 to S340 and S410 described in fig. 7, the method steps S310 to S340 and S510 described in fig. 8, the method steps S210, S220 and S610 to S640 described in fig. 9, the method steps S210, S220 and S710 to S740 described in fig. 10, the method steps S210 to S230 and S810 described in fig. 11, and the method steps S210 to S230 and S910 described in fig. 12.
The embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, i.e. may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For a hardware implementation, the Processing units may be implemented within one or more Application SP ECIFIC INTEGRATED Circuits (ASICs), digital signal processors (DIGITAL SIGNAL Processing, DS P), digital signal Processing devices (DSP DEVICE, DSPD), programmable logic devices (Programmable Logic De vice, PLD), field-Programmable gate arrays (Field-Programmable GATE ARRAY, FPGA), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units configured to perform the functions described herein, or a combination thereof.
For a software implementation, the techniques described herein may be implemented by means of units that perform the functions described herein. The software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be embodied in essence or a part contributing to the prior art or a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application. The storage medium includes various media capable of storing program codes such as a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk or an optical disk.
It should be noted that, in this document, relational terms such as "first," "second," "third," "fourth," and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
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