CN114256810A

CN114256810A - A battery protection control circuit and related chips

Info

Publication number: CN114256810A
Application number: CN202110266234.0A
Authority: CN
Inventors: 黄洪伟
Original assignee: Shenzhen Injoinic Technology Co Ltd
Current assignee: Shenzhen Injoinic Technology Co Ltd
Priority date: 2020-09-22
Filing date: 2020-09-22
Publication date: 2022-03-29
Anticipated expiration: 2040-09-22
Also published as: CN114256810B; CN111864867A; CN111864867B

Abstract

The present application discloses a battery protection control circuit and related chips. The battery protection control circuit includes a VDD port, GND, R1, a cascaded MOS tube module, N1, N2, R2, a preset protection circuit, an MCU, a CO port, and a DO port. , VM port; VDD port is connected to the first end of R1, the second end of R1 is connected to the cascaded MOS tube module, the cascaded MOS tube module is connected to the gate of N1, the gate of N2 and the first end of R3, the source of N1 The pole, the second end of R3 and the source and drain of N2 are all grounded; the second end of R1 is also connected to the preset protection circuit and the MCU as the VDDA port, and the MCU is connected to the CO port, DO port, and VM port. The battery protection control circuit provided by the present application is beneficial to prevent the battery protection circuit in the battery circuit from being burned due to excessive voltage.

Description

Battery protection control circuit and related chip

Technical Field

The application relates to the technical field of battery chips, in particular to a battery protection control circuit, a chip and an electronic device.

Background

Currently, lithium batteries are widely used in various portable devices, such as mobile phones, camcorders, notebook computers, electrical tools, remote control or electric toys, and other portable electronic devices, due to their excellent characteristics.

The lithium battery can be used repeatedly after charging, usually, charging equipment is used for taking electricity from a power grid to charge the lithium battery, but the voltage of the electricity taken from the power grid is far greater than the working voltage of the lithium battery, so that the voltage is reduced to the working voltage of the lithium battery by using the charging equipment so as to facilitate charging. However, since the voltage of the power grid may change greatly in a transient state, the charging device cannot reduce the transient voltage to the working voltage of the lithium battery, so that the protection circuit of the lithium battery is burnt. Or, in the discharging process of the lithium battery, the output voltage is unstable in the discharging process, so that the lithium battery protection circuit is easily burnt when the voltage is higher than the preset value.

Disclosure of Invention

The application provides a battery protection control circuit, a chip and an electronic device, which aim to avoid the battery protection circuit in a battery circuit from being burnt due to overlarge voltage.

In a first aspect, an embodiment of the present application provides a battery protection control circuit, which includes an anode voltage VDD port, a ground port GND, a first resistor R1, a cascaded MOS transistor module, a first NMOS transistor N1, a second NMOS transistor N2, a second resistor R2, a preset protection circuit, a micro control unit MCU, a charge protection CO port, a discharge protection DO port, and a voltage control VM port;

the positive voltage VDD port is connected with a first end of the resistor R1, a second end of the resistor R1 is connected with the cascaded MOS transistor module, the cascaded MOS transistor module is connected with a grid electrode of the first NMOS transistor N1, a grid electrode of the second NMOS transistor N2 and a first end of the resistor R2, and a source electrode of the first NMOS transistor N1, a second end of the second resistor R2 and a source electrode and a drain electrode of the second NMOS transistor N2 are all grounded;

a second end of the resistor R1 serving as an internal power supply VDDA port is further connected to the preset protection circuit and the MCU, and the MCU is connected to the charging protection CO port, the discharging protection DO port, and the voltage control VM port;

the positive voltage VDD port is used for being combined with the positive electrode of the battery and then is connected with a preset device through an EB + port, the preset device comprises a charger or a preset load, the ground port GND is used for connecting the cathode of the battery, the charging protection CO port is used for connecting the grid of a third NMOS tube N3, the discharging protection DO port is used for connecting the grid N4 of a fourth NMOS tube, the voltage control VM port is used for connecting a first end of a third resistor R3, a second end of the third resistor R3 is combined with the source of the third NMOS transistor N3 and the positive electrode of the first diode D1 and then connected with the preset device through an EB-port, the drain electrode of the third NMOS transistor N3 and the cathode electrode of the first diode D1 are combined and then connected with the drain electrode of the fourth NMOS transistor N4 and the cathode electrode of the second diode D2, the source electrode of the fourth NMOS transistor N4 and the positive electrode of the second diode D2 are connected with the negative electrode of the battery.

In a second aspect, an embodiment of the present application provides a battery protection control chip, where the battery protection control chip includes the battery protection control circuit according to the first aspect.

In a third aspect, an embodiment of the present application provides an electronic device, including the battery protection control chip as described in the first aspect.

It can be seen that in the battery protection control circuit provided by the present application, the resistor R1, the cascaded MOS transistor module, the first NMOS transistor N1, the second NMOS transistor N2, and the second resistor R2 form a clamp circuit for protecting a preset protection circuit at the rear end of the internal power supply VDDA port, when the positive voltage VDD port is in a normal voltage state, the first NMOS transistor N1 and the second NMOS transistor N2 are not conducted, the circuit works normally, when the voltage of the positive electrode voltage VDD port is in an abnormal increasing state, the voltage VDDA of the internal power supply VDDA port is increased, the first NMOS transistor N1 is conducted, the gate-source voltage VGSN1 of N1 is increased, and then the conduction current I2 of N1 increases, the voltage drop VR1 on the first resistor R1 increases due to the increase of the combination current (I2+ the rear-end load circuit I1 of the internal power supply VDDA port), VR1 increases to promote the VDDA to be reduced, and finally the clamping control of VDDA is completed, so that the battery protection circuit in the battery circuit is prevented from being burnt due to the overlarge voltage.

Drawings

Fig. 1 is a schematic circuit diagram of a battery protection control circuit provided in the present application;

FIG. 2 is a schematic diagram of a predetermined protection circuit provided in the present application;

FIG. 3 is a schematic diagram of the components of an overvoltage protection circuit provided by the present application;

FIG. 4 is a schematic diagram illustrating the components of an under-voltage protection circuit according to the present disclosure;

FIG. 5 is a schematic diagram of an over-temperature protection circuit according to the present application;

fig. 6 is a schematic diagram illustrating an over-discharge current protection circuit according to the present application;

FIG. 7 is a schematic diagram of the composition of an over-current protection circuit provided herein;

fig. 8 is a schematic circuit diagram of a cascaded MOS transistor module provided in the present application;

fig. 9 is a schematic circuit diagram of another cascaded MOS transistor module provided in the present application;

fig. 10 is a schematic circuit diagram of a battery protection control chip provided in the present application;

fig. 11 is a schematic diagram illustrating a composition of an electronic device according to the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It is to be understood that the terminology used in the embodiments of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

As shown in fig. 1, an embodiment of the present application provides a battery protection control circuit, which includes an anode voltage VDD port, a ground port GND, a first resistor R1, a cascaded field effect transistor MOS transistor module, a first NMOS transistor N1, a second NMOS transistor N2, a second resistor R2, a preset protection circuit, a micro control unit MCU, a charge protection CO port, a discharge protection DO port, and a voltage control VM port;

the positive voltage VDD port is used for being combined with the positive electrode of the battery and then connected with an EB + port of a preset device, the preset device comprises a charger or a preset load, the ground port GND is used for connecting the cathode of the battery, the charging protection CO port is used for connecting the grid of a third NMOS tube N3, the discharging protection DO port is used for connecting the grid N4 of a fourth NMOS tube, the voltage control VM port is used for connecting a first end of a third resistor R3, a second end of the third resistor R3 is combined with the source of the third NMOS transistor N3 and the anode of the first diode D1 and then connected with the EB-port of the preset device, the drain electrode of the third NMOS transistor N3 and the cathode electrode of the first diode D1 are combined and then connected with the drain electrode of the fourth NMOS transistor N4 and the cathode electrode of the second diode D2, the source electrode of the fourth NMOS transistor N4 and the positive electrode of the second diode D2 are connected with the negative electrode of the battery.

The charger may be an onboard charger in a vehicle battery system, such as a DC-to-DC/DC lithium battery charger, and the preset load may be an in-vehicle load, such as a sound box.

The second NMOS transistor N2 is used as a MOS capacitor, and is mainly used for filtering to prevent the first NMOS transistor N1 from being turned on by voltage glitch.

Wherein the resistance of R2 is greater than a predetermined resistance, such as 10K ohms. The resistance value of the R2 is set to be large enough to make the leakage power consumption of the voltage resistance R1 as small as possible, and reduce the waste of power consumption.

In the present possible example, as shown in fig. 2, the preset protection circuit includes at least one of: the protection circuit comprises an overvoltage protection circuit, an undervoltage protection circuit, an over-temperature protection circuit, an over-discharge current protection circuit and an over-current protection circuit.

The overvoltage protection circuit and the over-current protection circuit are used for protecting the preset protection circuit at the rear end of the internal power supply VDDA port in a charging state when a battery is in the charging state (namely when a preset device is a charger), the over-temperature protection circuit is used for protecting the temperature state of the preset protection circuit at the rear end of the internal power supply VDDA port in the charging or discharging state, and the undervoltage protection circuit and the over-current protection circuit are used for protecting the preset protection circuit at the rear end of the internal power supply VDDA port in the discharging state.

In the present possible example, as shown in fig. 3, the overvoltage protection circuit includes a fifth resistor R5, a sixth resistor R6, and a first voltage comparator Av 1; the positive voltage VDD port is connected to a first end of the fifth resistor R5, a second end of the fifth resistor R5 is connected to a first end of the sixth resistor R6 and a positive electrode port of the first voltage comparator Av1, a second end of the sixth resistor R6 is connected to the ground port GND, and an internal reference voltage port (shown as Vref1) and an output port of the first voltage comparator Av1 are connected to the MCU; the MCU is used for closing the third NMOS tube N3 of the charging protection CO port when the overvoltage protection circuit detects an overvoltage state.

As shown in fig. 4, the undervoltage protection circuit includes a seventh resistor R7, an eighth resistor R8, and a second voltage comparator Av 2; the positive voltage VDD port is connected to a first end of the seventh resistor R7, a second end of the seventh resistor R7 is connected to a first end of the eighth resistor R8 and a positive terminal of the second voltage comparator Av2, a second end of the eighth resistor R8 is connected to the ground terminal GND, and an internal reference voltage port (shown as Vref2) and an output port of the second voltage comparator Av2 are connected to the MCU; the MCU is used for closing the fourth NMOS tube N4 of the discharge protection DO port when the undervoltage protection circuit detects an undervoltage state.

As shown in fig. 5, the over-temperature protection circuit includes a current source, a transistor, and a third voltage comparator Av 3; the positive electrode of the current source is connected with the positive electrode voltage VDD port, the negative electrode of the current source is connected with the emitting electrode of the triode and the positive electrode port of the third voltage comparator Av3, the base electrode and the collector electrode of the triode are both connected with the ground port GND, and the internal reference voltage port (shown as Vref3) and the output port of the first voltage comparator Av1 are connected with the MCU; the MCU is used for closing the third NMOS tube N3 of the charging protection CO port when the over-temperature protection circuit detects that the over-temperature state occurs during charging, and is used for closing the fourth NMOS tube N4 of the discharging protection DO port when the over-temperature protection circuit detects that the over-temperature state occurs during discharging.

As shown in fig. 6, the over-discharge current protection circuit includes a ninth resistor R9 and a second current comparator Ai2, the positive voltage VDD port is connected to the positive port of the second current comparator Ai2, the negative port of the second current comparator Ai2 is connected to the ground GND after being connected in series with the ninth resistor R9, and the output port of the second current comparator Ai2 is connected to the MCU; the MCU is used for closing the fourth NMOS tube N4 of the discharge protection DO port when the over-discharge current protection circuit detects a discharge over-current state.

As shown in fig. 7, the overcharge protection circuit includes a tenth resistor R10 and a third current comparator, a positive electrode of the third current comparator is connected to the ground port GND, a negative electrode of the third current comparator is connected to the voltage control VM port after being connected in series with the tenth resistor R10, and an output port of the third current comparator is connected to the MCU; the MCU is used for closing the third NMOS tube N3 of the discharge protection CO port when a discharge overcurrent state is detected through the over-current protection circuit.

It can be seen that in the battery protection control circuit provided by the present application, the resistor R1, the cascaded fet module, the first NMOS transistor N1, the second NMOS transistor N2, and the second resistor R2 form a clamp circuit for protecting a preset protection circuit at the rear end of the internal power supply VDDA port, when the positive voltage VDD port is in a normal voltage state, the first NMOS transistor N1 and the second NMOS transistor N2 are not conducted, the circuit works normally, when the voltage of the positive electrode voltage VDD port is in an abnormal increasing state, the voltage VDDA of the internal power supply VDDA port is increased, the first NMOS transistor N1 is conducted, the gate-source voltage VGSN1 of N1 is increased, and then the conduction current I2 of N1 increases, the voltage drop VR1 on the first resistor R1 increases due to the increase of the combination current (I2+ the rear-end load circuit I1 of the internal power supply VDDA port), VR1 increases to promote the VDDA to be reduced, and finally the clamping control of VDDA is completed, so that the battery protection circuit in the battery circuit is prevented from being burnt due to the overlarge voltage.

In this possible example, if the preset device is the charger, the MCU is configured to turn on the third NMOS transistor N3 through the charge protection CO port in a normal charge state to implement charging, and turn off the third NMOS transistor N3 through the charge protection CO port in an overcharge state or an over-temperature state to implement stopping charging;

if the preset device is the load, the MCU is configured to turn on the fourth NMOS transistor N4 through the discharge protection DO port to achieve discharge in a normal discharge state, and turn off the fourth NMOS transistor N4 through the discharge protection DO port in an over-discharge state or an over-temperature state, and pull up the voltage at the voltage control VM port to achieve stopping of discharge.

It can be seen that the battery protection control circuit of this example can detect and protect control the voltage and current of charge and discharge state, because signal detection circuit and MCU are supplied power by the circuit that possesses the clamp control function to can avoid abnormal state to be burnt out.

In this possible example, the first NMOS transistor N1 is used to discharge the internal supply VDDA port when turned on to clamp the voltage VDDA at a preset voltage value.

The preset voltage value can be less than or equal to the rated working voltage of the MCU and the preset protection circuit at the rear end of the internal power supply VDDA port.

In this possible example, as shown in fig. 8, the cascode MOS transistor module includes a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3;

the second end of the first resistor R1 is connected with the source electrode of the first PMOS tube P1, the grid electrode and the drain electrode of the first PMOS tube P1 are connected with the source electrode of the second PMOS tube P2, the grid electrode and the drain electrode of the second PMOS tube P3 are connected with the source electrode of the third PMOS tube, and the grid electrode and the drain electrode of the third PMOS tube are connected with the grid electrode of the first NMOS tube N1, the grid electrode of the second NMOS tube N2 and the first end of the second resistor R2.

The number of the MOS in the cascaded MOS tube module is not limited uniquely, and the MOS tube module can be set according to the application requirement of an actual circuit.

The voltage of the positive electrode voltage VDD port is larger than or equal to the sum of the gate-source voltage of all MOS tubes in the cascaded MOS tube module and the gate-source voltage of the first NMOS tube N1.

In this possible example, as shown in fig. 9, the cascode MOS transistor module includes a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7;

the second end of the first resistor R1 is connected to the drain and the gate of the fifth NMOS transistor N5, the source of the fifth NMOS transistor N5 is connected to the drain and the gate of the sixth NMOS transistor N6, the source of the sixth NMOS transistor N6 is connected to the drain and the gate of the seventh NMOS transistor N7, and the source of the seventh NMOS transistor N7 is connected to the gate of the first NMOS transistor N1, the gate of the second NMOS transistor N2, and the first end of the second resistor R2.

The three MOS tubes are connected in cascade, so that the conduction threshold voltage is greater than or equal to the sum of the gate-source voltages of the three MOS tubes.

In this possible example, the resistance value of the first resistor R1 is set by the following formula,

R1＝min(R1max1，R1max2)，

R1max1＝ΔV1÷I1min＝(VDDmax1－VDDA1)÷I1min，

R1max2＝ΔV2÷(I1min+I2)＝(VDDmax2－VDDA2)÷(I1min+I2)，

I2＝(1÷2)×(W÷L)×μ×Cox×(VGSN1－VTH)²，

VDDA2＝VGS1+VGS2+VGS3+VGSN1，

wherein, R1max1 is the maximum reference resistance of the first resistor R1 in the system normal operating state (i.e. the operating state where the first NMOS case N1 is not turned on), and R1max2 is the maximum reference resistance of the first resistor R1 in the system overvoltage operating state (i.e. the operating state where the first NMOS case N1 is turned on);

wherein Δ V1 is the maximum voltage drop of the first resistor R1 in the system normal operation state, I1min is the minimum input current of the internal power supply VDDA port in the system normal operation state, VDDmax1 is the maximum input voltage of the positive voltage VDD port in the system normal operation state, VDDA1 is the input voltage of the internal power supply VDDA port in the system normal operation state;

wherein Δ V2 is the maximum voltage drop of the first resistor R1 in the system overvoltage operating state, I2 is the conduction current of the first NMOS transistor in the system overvoltage operating state, VDDmax2 is the maximum voltage of the positive voltage VDD port in the system overvoltage operating state, VDDA2 is the operating voltage of the internal power supply VDDA port in the system overvoltage operating state;

wherein W is the gate width of the MOS transistor in the physical parameters, L is the channel length of the MOS transistor in the physical parameters, W and L are preset according to empirical values, u is the carrier mobility, VGSN1 is the gate-source voltage of the first NMOS transistor N1, and VTH is the voltage threshold;

VGS1 is a gate-source voltage of the first PMOS transistor P1, VGS2 is a gate-source voltage of the second PMOS transistor P2, VGS3 is a gate-source voltage of the third PMOS transistor P3, or VGS1 is a gate-source voltage of the fifth NMOS transistor N5, VGS2 is a gate-source voltage of the sixth NMOS transistor N6, and VGS3 is a gate-source voltage of the seventh NMOS transistor N7.

Under the normal working state of the battery protection control circuit, as the cascaded MOS tube module, the first NMOS tube N1 and the second NMOS tube N2 are not conducted, the current passing through R1 can directly flow into the rear end load of the internal power supply VDDA port, and an equality relation exists

R1max1 × I1min ═ Δ V1 ═ VDDmax 1-VDDA 1, the formula is obtained after conversion,

R1max1＝ΔV1÷I1min＝(VDDmax1－VDDA1)÷I1min，

the maximum withstand voltage resistance value allowed to be designed by R1 in a normal working state can be determined through a calculation formula (VDDMAx 1-VDDA 1) ÷ I1min, in an overvoltage working state, the resistance value of R2 is set to be large enough to enable the current flowing through the cascaded MOS transistor module and the R2 to be small enough to be ignored, so that the current flowing through R1 is (I1min + I2), the I2 serving as the conduction current of the first NMOS transistor can be determined by calculation based on preset device physical parameters, then the maximum voltage drop and the combination current of the R1 in the overvoltage working state are calculated, and the maximum reference resistance value of the R1 in the overvoltage working state is calculated.

In this example, the developer may preferentially set the first NMOS transistor based on design experience, and then calculate the resistance of R1 according to the formula in this example, so as to improve the stability and efficiency of the battery protection control circuit design.

In this possible example, the value of the voltage resistance R1 can be optimized according to the normal power consumption requirement of the system. If the chip low-voltage module consumes large power, the value of the voltage resistance R1 can be relatively small so as to reduce the voltage drop on the chip low-voltage module, and if the chip low-voltage module consumes small power, the value of R1 can be relatively large so as to ensure that the low-voltage module cannot see high voltage.

The resistance value of the first resistor R1 is optimized by the following formula,

R1’＝α×R1recharge+β×R1discharge

R1recharge＝R1+(P1－P1recharge)÷I1²

R1discharge＝R1+(P1－P1discharge)÷I1²

α＝Trecharge÷(Trecharge+Tdischarge)

β＝Tdischarge÷(Trecharge+Tdischarge)

wherein R1' is an updated resistance value of the first resistor R1, α is a charging weight coefficient, β is a discharging weight coefficient, R1recharge is a reference resistor of the first resistor R1 in a state where the internal power supply VDDA port is powered under a first load condition, the first load condition is a working load of a device at the rear end of the internal power supply VDDA port in a state where a preset device is the charger, R1discharge is a reference resistor of the first resistor R1 in a state where the internal power supply VDDA port is powered under a second load condition, and the second load condition is a working load of a device at the rear end of the internal power supply VDDA port in a state where a preset device is the preset load;

wherein P1recharge is the power consumption of the internal power supply VDDA port in the power supply state for the first load condition, P1 is the reference power consumption of the device at the rear end of the internal power supply VDDA port, and P1discharge is the power consumption of the internal power supply VDDA port in the power supply state for the second load condition;

wherein, Trecharge is the statistical charging reference time length of the system, and Tdischarge is the statistical discharging reference time length of the system.

It can be seen that, in this example, since the battery can dynamically switch between a charging state and a discharging state, the MCU and the pre-protection circuit at the rear end of the internal power supply VDDA port are under a first load condition in the charging state (the pre-protection circuit actually enabled under this condition includes at least one of the over-voltage protection circuit, the over-temperature protection circuit, and the overshoot current protection circuit), and the MCU and the pre-protection circuit at the rear end of the internal power supply VDDA port are under a second load condition in the discharging state (the pre-protection circuit actually enabled under this condition includes at least one of the under-voltage protection circuit, the over-temperature protection circuit, and the overshoot current protection circuit), there is a relatively large difference between the first load condition and the second load condition, and the difference may occur when the R1 organization is not fine enough, there is a case of low energy consumption utilization rate (for example, the resistance of R1 is large, resulting in large voltage drop and large energy consumption loss, the power supply energy consumption efficiency of the internal power supply VDDA port is relatively low, or the overall energy consumption is relatively high, and the like), so that the energy consumption utilization rate of the circuit system can be effectively improved by finely designing the resistance value of R1.

In the possible example, the physical parameters of the first MOS transistor N1 are set by the following formula,

(W÷L)＝(2×I2 max)÷[μ×Cox×(VGSN1－VTH)²]，

I2max＝Imax－I1min，

Imax＝(VDDmax2－VDDA2)÷R1min，

VDDA2＝VGS1+VGS2+VGS3+VGSN1，

R1min＝(VDD min 1－VDDA1)÷I1max，

w is the gate width of an MOS transistor in the physical parameters, L is the channel length of the MOS transistor in the physical parameters, I2max is the maximum on-current of the first NOS transistor N1 in a system overvoltage operating state, u is the carrier mobility, VGSN1 is the gate-source voltage of the first NMOS transistor N1, and VTH is the voltage threshold;

wherein Imax is the maximum input current of the positive voltage VDD port in the system overvoltage working state, and I1min is the minimum input current of the internal power supply VDDA port in the system normal working state;

the VDD max2 is the maximum input voltage of the positive voltage VDD port in the system overvoltage working state, and the VDDA2 is the input voltage of the internal power supply VDDA port in the system overvoltage working state;

VGS1 is a gate-source voltage of the first PMOS transistor P1, VGS2 is a gate-source voltage of the second PMOS transistor P2, VGS3 is a gate-source voltage of the third PMOS transistor P3, or VGS1 is a gate-source voltage of the fifth NMOS transistor N5, VGS2 is a gate-source voltage of the sixth NMOS transistor N6, and VGS3 is a gate-source voltage of the seventh NMOS transistor N7;

VDDMin1 is the minimum input voltage of the positive voltage VDD port in the normal working state of the system, and VDDA1 is the input voltage of the internal power supply VDDA port in the normal working state of the system.

Wherein, under the normal working condition, the minimum resistance value of the battery protection control circuit can be calculated based on the equation R1min × I1max ═ VDD min 1-VDDA 1, under the overvoltage working condition, I2max ═ Imax-I1 min, Imax ═ VDDMAmax 2-VDDA 2/R1 min, VDDA2 ═ VGS1+ VGS2+ VGS3+ VGSN1, thereby calculating I2max, and finally based on the device parameter equivalent relation of the first NMOS tube N1, I2max ═ (1/2) × (W/L) × Cox × (VGSN1-VTH)²The physical parameters of N1 were calculated.

In this example, the resistance value of the voltage resistance R1 in the battery protection control circuit may be set based on the circuit signal relationship in the normal operating state, and then the physical parameters of the first NMOS transistor N1 are further calculated according to the determined resistance value of R1 and the circuit signal relationship in the overvoltage operating state.

As shown in fig. 10, an embodiment of the present application further provides a battery protection control chip, where the battery protection control chip includes the battery protection control circuit according to the above embodiment.

As shown in fig. 11, an electronic device including the battery protection control circuit according to the embodiment is further provided.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims

1. A battery protection control circuit is characterized by comprising an anode voltage VDD port, a ground port GND, a first resistor R1, a cascade MOS tube circuit, a first NMOS tube N1, a second NMOS tube N2, a second resistor R2, a preset protection circuit, a micro control unit MCU, a charging protection CO port, a discharging protection DO port and a voltage control VM port;

the positive voltage VDD port is connected to a first end of the resistor R1, a second end of the resistor R1 is connected to the cascode MOS transistor circuit, the cascode MOS transistor circuit is connected to a gate of the first NMOS transistor N1, a gate of the second NMOS transistor N2, and a first end of the resistor R2, and a source of the first NMOS transistor N1, a second end of the second resistor R2, and a source and a drain of the second NMOS transistor N2 are all grounded;

2. The battery protection control circuit of claim 1, wherein the preset protection circuit comprises at least one of: the protection circuit comprises an overvoltage protection circuit, an undervoltage protection circuit, an over-temperature protection circuit, an over-discharge current protection circuit and an over-current protection circuit.

3. The battery protection control circuit of claim 2,

the overvoltage protection circuit comprises a fifth resistor R5, a sixth resistor R6 and a first voltage comparator Av 1; the positive voltage VDD port is connected to a first end of the fifth resistor R5, a second end of the fifth resistor R5 is connected to a first end of the sixth resistor R6 and a positive electrode port of the first voltage comparator Av1, a second end of the sixth resistor R6 is connected to the ground port GND, and an internal reference voltage port and an output port of the first voltage comparator Av1 are connected to the MCU; the MCU is used for closing the third NMOS tube N3 of the charging protection CO port when the overvoltage protection circuit detects an overvoltage state;

the undervoltage protection circuit comprises a seventh resistor R7, an eighth resistor R8 and a second voltage comparator Av 2; the positive voltage VDD port is connected to a first end of the seventh resistor R7, a second end of the seventh resistor R7 is connected to a first end of the eighth resistor R8 and a positive electrode port of the second voltage comparator Av2, a second end of the eighth resistor R8 is connected to the ground port GND, and an internal reference voltage port and an output port of the second voltage comparator Av2 are connected to the MCU; the MCU is used for closing the fourth NMOS tube N4 of the discharge protection DO port when the undervoltage protection circuit detects an undervoltage state;

the over-temperature protection circuit comprises a current source, a triode and a third voltage comparator Av 3; the positive electrode of the current source is connected with the positive electrode voltage VDD port, the negative electrode of the current source is connected with the emitting electrode of the triode and the positive electrode port of the first current comparator Ai1, the base electrode and the collector electrode of the triode are both connected with the grounding port GND, and the internal reference voltage port and the output port of the first voltage comparator Av1 are connected with the MCU; the MCU is used for closing the third NMOS tube N3 of the charging protection CO port when the over-temperature protection circuit detects that the charging state is over-temperature and closing the fourth NMOS tube N4 of the discharging protection DO port when the over-temperature protection circuit detects that the discharging state is over-temperature;

the over-discharge current protection circuit comprises a ninth resistor R9 and a second current comparator Ai2, wherein the positive voltage VDD port is connected with the positive electrode port of the second current comparator Ai2, the negative electrode port of the second current comparator Ai2 is connected with the ground port GND after being connected with the ninth resistor R9 in series, and the output port of the second current comparator Ai2 is connected with the MCU; the MCU is used for closing the fourth NMOS tube N4 of the discharge protection DO port when the over-discharge current protection circuit detects a discharge over-current state;

the overcharge current protection circuit comprises a tenth resistor R10 and a third current comparator, wherein the anode of the third current comparator is connected with the ground port GND, the cathode of the third current comparator is connected with the voltage control VM port after being connected with the tenth resistor R10 in series, and the output port of the third current comparator is connected with the MCU; the MCU is used for closing the third NMOS tube N3 of the discharge protection CO port when a discharge overcurrent state is detected through the over-current protection circuit.

4. The battery protection control circuit of claim 3,

if the preset device is the charger, the MCU is configured to turn on the third NMOS transistor N3 through the charging protection CO port in a normal charging state to implement charging, and turn off the third NMOS transistor N3 through the charging protection CO port in an overcharge state or an over-temperature state to implement stopping charging;

5. The battery protection control circuit of claim 4, wherein the first NMOS transistor N1 is configured to discharge the internal power supply VDDA port when turned on to clamp the voltage VDDA at a preset voltage value.

6. The battery protection control circuit of claim 5, wherein the cascade MOS transistor circuit comprises a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3;

7. The battery protection control circuit of claim 5, wherein the cascade MOS transistor circuit comprises a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7;

8. The battery protection control circuit of claim 6, wherein the resistance value of the first resistor R1 is set by the following formula,

R1＝min(R1max1，R1max2)，

R1max1＝ΔV1÷I1min＝(VDDmax1－VDDA1)÷I1min，

R1max2＝ΔV2÷(I1min+I2)＝(VDDmax2－VDDA2)÷(I1min+I2)，

I2＝(1÷2)×(W÷L)×μ×Cox×(VGSN1－VTH)²，

VDDA2＝VGS1+VGS2+VGS3+VGSN1，

wherein, R1max1 is the maximum reference resistance of the first resistor R1 in the normal system operating state, and R1max2 is the maximum reference resistance of the first resistor R1 in the system overvoltage operating state;

VGS1 is the gate-source voltage of the first PMOS transistor P1, VGS2 is the gate-source voltage of the second PMOS transistor P2, and VGS3 is the gate-source voltage of the third PMOS transistor P3.

9. The battery protection control circuit of claim 6, wherein the physical parameters of the first MOS transistor N1 are set by the following formula,

(W÷L)＝(2×I2 max)÷[μ×Cox×(VGSN1－VTH)²]，

I2max＝Imax－I1min，

Imax＝(VDDmax2－VDDA2)÷R1min，

VDDA2＝VGS1+VGS2+VGS3+VGSN1，

R1min＝(VDD min 1－VDDA1)÷I1max，

VGS1 is the gate-source voltage of the first PMOS transistor P1, VGS2 is the gate-source voltage of the second PMOS transistor P2, and VGS3 is the gate-source voltage of the third PMOS transistor P3;

10. A battery protection control chip, characterized in that the battery protection control chip comprises a battery protection control circuit according to any one of claims 1 to 9.