CN114256167A

CN114256167A - Semiconductor structure and forming method thereof

Info

Publication number: CN114256167A
Application number: CN202011023503.2A
Authority: CN
Inventors: 凃顺财
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2020-09-25
Filing date: 2020-09-25
Publication date: 2022-03-29

Abstract

The present invention provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a wiring layer including an insulating layer and a wiring arranged in the insulating layer, the wiring comprising a nano-twinned copper material, the wiring layer having a first surface; a die arranged above the first surface; a first conductive connection , connected between the wiring and the die, a first bonding surface is provided between the first conductive connecting piece and the wiring, and the first bonding surface is the interface where the first conductive connecting piece and the nano-twinned copper material are electrically connected. There is no transition layer formed during the growth of the nanotwinned copper material at the first joint surface, and the transition layer has an irregular crystal orientation. The above technical solutions of the present invention can improve the bonding strength and electrical connectivity of the junction between the nano-twinned copper and the first conductive connector.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

The Die (Die) and the wafer or substrate may be directly electrically connected using Hybrid bonding. In hybrid bonding, the copper material is bonded to the copper material, but the copper-to-copper bonding requires a high annealing temperature (annealing temperature), which may reach 300 ℃. Such high temperatures may be detrimental to processes that require low temperatures. For example, HBM (High Bandwidth Memory) die, which are not suitable for low temperature processing, use hybrid bonding.

As shown in fig. 1, a wiring layer 12 may be added between the die 20 and the wafer or substrate 10, with the wires 14 in the wiring layer 12 being made of nano-twinned copper (NT-Cu) material. Die 20 and wafer 10 are bonded to wiring layer 12 by a connection 30 comprising a seed layer 31 and copper 32. When the die 20 is bonded to the wafer 10, the wires 14 of nano-twinned copper material are bonded to the copper 32 of the connector 30, and the bonding temperature of nano-twinned copper and copper is lower than the bonding temperature of copper and copper. However, in the process of manufacturing the wiring layer 12 including the nano-twin copper material, the nano-twin copper grows on the seed layer above the carrier substrate, a transition layer 40 is generated at the bottom of the nano-twin copper material, and a gap (void) is formed between the transition layer 40 and the seed layer on the carrier substrate, so that after the carrier substrate is removed, a problem of poor bonding strength and poor electrical connection effect is generated at the bonding surface of the nano-twin copper and the copper.

Disclosure of Invention

In view of the above technical problems, the present invention provides a semiconductor structure and a method for forming the same, which can improve the bonding strength and electrical connectivity at the junction of nano twin crystal copper and a conductive connecting member.

According to an aspect of the present invention, there is provided a semiconductor structure comprising: a wiring layer including an insulating layer and a wiring provided in the insulating layer, the wiring including a nano-twin copper material, the wiring layer having a first surface; a die disposed over the first surface; and a first conductive connection connected between the wire and the die. The first conductive connecting piece and the wiring are provided with a first joint surface, the first joint surface is an interface for electrically connecting the first conductive connecting piece and the nanometer twin crystal copper material, the first joint surface is not provided with a transition layer formed in the process of growing the nanometer twin crystal copper material, and the transition layer has irregular crystal orientation.

In some embodiments, the first conductive connecting member includes a metal layer electrically connected to the nano-twin copper material; and a seed layer disposed between the metal layer and the die.

In some embodiments, the material of the metal layer comprises copper or nano-twinned copper.

In some embodiments, the semiconductor structure further includes a substrate disposed below a second surface of the wiring layer, the second surface disposed opposite the first surface. The wiring layer further comprises a second conductive connecting piece, the second conductive connecting piece is used for connecting the wiring to the substrate, a second joint surface is arranged between the second conductive connecting piece and the wiring, and the second joint surface is an interface for electrically connecting the second conductive connecting piece and the nano twin crystal copper material of the wiring.

In some embodiments, the semiconductor structure further includes an interposer layer disposed below a second surface of the wiring layer, the second surface disposed opposite the first surface. The wiring layer further comprises a second conductive connecting piece, the second conductive connecting piece is used for connecting the wiring to the insertion layer, a second joint surface is arranged between the second conductive connecting piece and the wiring, and the second joint surface is an interface of the second conductive connecting piece and a nanometer twin crystal copper material of the wiring in physical contact;

in some embodiments, the routing comprises: the first wiring part is electrically connected with the first conductive connecting piece; a second wiring portion connected to the first wiring portion; and a third wiring portion connected to the second wiring portion. The first wiring portion and the third wiring portion are made of nano-twin copper, and the second wiring portion is made of a metal different from the first wiring portion and the third wiring portion.

In some embodiments, the entirety of the wiring is made of nano-twinned copper material.

In some embodiments, the wiring comprises a redistribution line, the material of the redistribution line comprising copper or nano-twinned copper.

In some embodiments, the nano twinned copper material has a (111) crystal orientation.

According to another aspect of the present invention, a method of forming a semiconductor structure includes forming an insulating layer and a wiring in the insulating layer. Wherein forming the wiring includes: forming a first seed layer on a first carrier substrate; an insulating layer having an opening is formed on the first seed layer, and first nano-twin copper is grown on the first seed layer under the opening. Wherein a first transition layer is formed between the grown first nanometer twin crystal copper and the first seed crystal layer. The method of forming a semiconductor structure further comprises: removing the first carrier substrate; removing the first seed layer and the first transition layer, and exposing the wiring; the wires are connected to the die by forming first conductive connections on exposed surfaces of the wires. The first conductive connecting piece is electrically connected with the first nanometer twin crystal copper of the wiring to form a first joint surface.

In some embodiments, prior to removing the first carrier substrate, further comprising: and forming a second conductive connecting piece on the grown first nanometer twin crystal copper, and connecting the wiring to the insertion layer through the second conductive connecting piece, wherein the second conductive connecting piece is electrically connected with the first nanometer twin crystal copper of the wiring to form a second joint surface.

In some embodiments, the method of forming a semiconductor structure further comprises: the die is connected to the interposer by a second conductive connection. The second conductive connecting piece is electrically connected with the first nano twinned crystal copper to form a second joint surface between the tube core and the insertion layer.

In some embodiments, the first nano twinned copper is formed as a first wiring portion of the wiring, the forming the wiring further comprising: forming a further wiring portion before removing the first carrier substrate; the first wiring portion is bonded to the other wiring portion to form a wiring.

In some embodiments, the additional wire segment includes a second wire segment joined to the first wire segment and a third wire segment joined to the second wire segment, the forming the additional wire segment including: forming a second seed layer on the second carrier substrate, and growing second nano-twin copper on the second seed layer, wherein a second transition layer is formed between the grown second nano-twin copper and the second seed layer, and the second nano-twin copper is formed as a second wiring portion; forming a third seed layer on the third carrier substrate, and growing third nano-twin copper on the third seed layer, the third nano-twin copper being formed as a third wiring portion; removing the third carrier substrate; removing the third seed layer and the third transition layer, and exposing the third wiring portion; bonding the second wiring portion on the second carrier substrate and the second seed layer with the third wiring portion; removing the second carrier substrate; the second seed layer and the second transition layer are removed, and the second wiring portion is exposed to be bonded with the first wiring portion.

In some embodiments, forming the additional wire portion includes: forming a redistribution line on the first wiring portion, the redistribution line being formed of a material different from the nano-twin copper; forming a second seed layer on the second carrier substrate, and growing second nano-twin copper on the second seed layer, wherein a second transition layer is formed between the grown second nano-twin copper and the second seed layer; removing the second carrier substrate; the second seed layer and the second transition layer are removed and the second nano-twinned copper is exposed to bond with the redistribution line.

In some embodiments, removing the first seed layer and the first transition layer comprises: a chemical mechanical polishing process is performed to remove the first seed layer and the first transition layer.

In some embodiments, forming the first conductive connection comprises: forming a metal layer electrically connected with the first nanometer twin crystal copper; and forming an additional seed layer overlying the metal layer.

In some embodiments, the first nano-twinned copper has a (111) crystal orientation and the first transition layer has an irregular crystal orientation.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 is a schematic diagram of a conventional semiconductor structure.

Fig. 2 is a schematic diagram of a semiconductor structure according to an embodiment of the invention.

Fig. 3A-3M illustrate schematic diagrams of intermediate stages of a process for forming a semiconductor structure, in accordance with an embodiment of the present invention.

Fig. 4 is a schematic diagram of a semiconductor structure according to another embodiment of the invention.

Fig. 5A-5M illustrate schematic diagrams of intermediate stages in a process of forming a semiconductor structure according to another embodiment of the invention.

Fig. 6 is a schematic diagram of a semiconductor structure according to another embodiment of the invention.

Fig. 7A-7J illustrate schematic diagrams of intermediate stages in a process of forming a semiconductor structure according to another embodiment of the invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Fig. 2 is a schematic diagram of a semiconductor structure according to an embodiment of the invention. The semiconductor structure includes a die 160 and a routing layer 190. The die 160 is disposed above an upper surface of the routing layer 190. The wiring layer 190 includes the insulating layer 108 and the wiring 122 provided in the insulating layer 108. The material of the wiring 122 includes nano twinned copper. The nano-twin copper refers to a pure copper material with a high-density coherent twin boundary in the crystal grain and a nano-scale (for example, less than 100nm) twin copper layer thickness. Conductive connection 130 (first conductive connection) connects between wire 122 and die 160 to electrically connect the wire to die 160. Die 160 may be, for example, an HBM die or other type of die.

The interface where the conductive connecting member 130 is electrically connected to the wiring 122 of the nano twinned copper material forms a first joint surface 125 between the conductive connecting member 130 and the wiring 122. During the growth of the nano-twinned copper material of the wiring 122, a transition layer 124 having an irregular crystal orientation will be formed at the end of the wiring 122. The transition layer 124 is removed before the nano-twinned copper material of the wire 122 is joined with the conductive connection 130. Therefore, there is no transition layer 124 formed during the growth of the nano-twinned copper material of the wiring at the first junction surface 125. The transition layer 124 having the void causes a problem of poor bonding strength and electrical connectivity at the interface of the wiring 122 and the conductive connection member 130, and since the transition layer is not provided at the first junction surface 125 between the conductive connection member 130 and the wiring 122, the bonding strength and electrical connectivity can be improved.

With continued reference to fig. 2, the conductive connection 130 may include a metal layer 132 and a seed layer 131, the seed layer 131 being disposed between the metal layer 132 and the die 160. The metal layer 132 is electrically connected to the nano-twin copper material of the wiring 122. In some embodiments, the material of metal layer 132 may include a metal such as copper. In other embodiments, the material of the metal layer 132 may include nano-twinned copper. The entirety of the wiring 122 may be made of a nano twinned copper material. The nano-twin copper material has a (111) crystal orientation, and the nano-twin copper material having a (111) crystal orientation for wiring of interconnection can improve electromigration resistance characteristics.

The semiconductor structure further includes an Interposer (Interposer)140 disposed below a lower surface of the wiring layer 190. The wiring layer 190 further includes a conductive connector (second conductive connector) 150, and the conductive connector 150 connects the wiring 122 to the insertion layer 140. The insertion layer 140 includes an insertion layer substrate 141 and a through hole 142(TSV) passing through the insertion layer substrate 141. The semiconductor structure may also include a wafer or substrate 200 disposed below the interposer 140. The interposer 140 may be connected to the substrate 200 through the pads 181 and the connectors 182. The connections 182 may be Ball Grid Array (BGA) connections, solder balls, metal posts, controlled collapse chip connection (C4) bumps, micro bumps, or the like.

The interface of the conductive connection element 150 electrically connected to the nano-twinned copper material of the wiring 122 forms a second bonding surface 126 between the conductive connection element 150 and the wiring 122. There is no transition layer formed during growth of the nano-twinned copper material of the wiring at this second interface 126.

Fig. 3A-3M are schematic diagrams illustrating intermediate stages in a process of forming the semiconductor structure shown in fig. 2. First, as shown in fig. 3A, a first carrier substrate 102, a release layer 104 over the first carrier substrate 102, and a first seed layer 106 over the release layer 104 are provided. The release layer 104 may be removed together with the first carrier substrate 102 from a structure to be formed in a subsequent step.

As shown in fig. 3B, an insulating layer 108 is formed over the first seed layer 106. The insulating layer 108 may be deposited by Chemical Vapor Deposition (CVD). The material of the insulating layer 108 may be an oxide.

As shown in fig. 3C, a patterned photoresist layer 212 is formed over the insulating layer 108 to pattern the insulating layer 108 with the patterned photoresist layer 212.

As shown in fig. 3D, the insulating layer 108 is patterned with a patterned photoresist layer 212, forming an opening 105 in the insulating layer 108. The opening 105 may be formed by an etching process, for example, using a dry etching process.

As shown in fig. 3E, first nano-twin copper 122 is formed within the opening in the insulating layer and on the seed layer. The first nano twinned copper 122 may be formed, for example, by an electroplating (plating) process. A first transition layer 124 is formed between the formed first nano twinned copper 122 and the first seed layer. In some embodiments, the first nano-twinned copper 122 has a (111) crystal orientation and the first transition layer 124 has an irregular crystal orientation.

As shown in fig. 3F, the photoresist layer 212 is stripped and a planarization process is performed so that the wiring 122 is flush with the top surface of the insulating layer 108. The first nano twinned copper 122 is formed as the wiring 122.

As shown in fig. 3G, a conductive connection member 150 (i.e., a second conductive connection member) is formed on the wiring 122 to connect the wiring 122 to the insertion layer 140 through the conductive connection member 150. The conductive connection 150 includes a metal layer 152 electrically connected to the wiring 122 and a seed layer 151 covering the metal layer 152. In some embodiments, the material of metal layer 152 may include copper. In other embodiments, the material of the metal layer 152 may include nano-twinned copper.

As shown in fig. 3H, the release layer 104 and the first carrier substrate 102 are removed, the resulting structure is flipped, and the first seed layer 106 is removed. In some embodiments, light, such as laser or UV light, may be projected on the release layer 104 such that the release layer 104 decomposes under the heat of the light and the first carrier substrate 102 may be removed. Thus, the first transition layer 124 may be exposed.

As shown in fig. 3I, the first transition layer 124 is removed and the wiring 122 is exposed. In some embodiments, a chemical mechanical polishing process is performed to remove the first transition layer 124.

As shown in fig. 3J, the wire 122 is connected to the die 160 by forming a conductive connection 130 (i.e., a first conductive connection) on an exposed surface of the wire 122. The conductive connection 130 includes a metal layer 132 electrically connected to the wiring 122 and a seed layer 131 covering the metal layer 132. In some embodiments, the material of metal layer 132 may include copper. In other embodiments, the material of the metal layer 132 may include nano-twinned copper.

As shown in fig. 3K, an encapsulation material 170 is formed overlying the die 160, for example, by a molding process.

As shown in fig. 3L, the structure shown in fig. 3K is inverted and a planarization process, such as a grinding or chemical mechanical polishing process, is performed. After the planarization process, the through hole 142 in the insertion layer 140 is exposed.

As shown in fig. 3M, a dielectric layer 180 is formed over the exposed through via 142, the dielectric layer 180 having an opening over the through via 142. A connection piece 182 connected to the through hole 142 is formed through the opening. The structure shown in fig. 3M may then be inverted and bonded to substrate 200 to form the semiconductor structure shown in fig. 2.

Fig. 4 is a schematic diagram of a semiconductor structure according to another embodiment of the invention. The semiconductor structure includes a die 160 and a routing layer 190, the die 160 being disposed above the routing layer 190. There is no transition layer formed during the growth of the nano-twin copper material of the wire at the first junction surface 125 where the conductive connector 130 is electrically connected with the wire 122 and the second junction surface 126 where the conductive connector 150 is electrically connected with the wire 122.

The difference from the embodiment shown in fig. 2 is that the wiring 122 in the wiring layer 190 includes a first wiring portion 1221, a second wiring portion 1222, and a third wiring portion 1223. The first wiring portion 1221 is electrically connected to the conductive connection member 150, the second wiring portion 1222 is connected to the first wiring portion 1221, and the third wiring portion 1223 is connected to the second wiring portion 1222. The second wiring portion 1222 is a metal the same as the material of the first wiring portion 1221 and the third wiring portion 1223. The materials of the first wiring portion 1221, the second wiring portion 1222, and the third wiring portion 1223 each include nano-twin copper.

Fig. 5A-5M are schematic diagrams illustrating intermediate stages in a process of forming the semiconductor structure shown in fig. 4. First, as shown in fig. 5A, a first carrier substrate 102, a release layer 104 over the first carrier substrate 102, and a first seed layer 106 over the release layer 104 are provided. An insulating layer 108 is formed over the first seed layer 106. A patterned photoresist layer 212 is also formed over the insulating layer 108.

As shown in fig. 5B, the insulating layer 108 is patterned with a patterned photoresist layer 212, forming an opening 105 in the insulating layer 108. As shown in fig. 5C, a first nano-twin copper 1221 is formed within the opening 105 in the insulating layer 108 and on the first seed layer 106. A first transition layer 124 is formed between the formed first nano-twin copper 1221 and the first seed layer 106.

As shown in fig. 5D, the photoresist layer 212 is stripped and a planarization process is performed such that the first nano-twin copper 1221 is flush with the top surface of the insulating layer 108. The first nano twinned copper 1221 is formed as the first wiring portion 1221 of the wiring 122. As shown in fig. 5E, a conductive connection 150 (i.e., a second conductive connection) is formed on the grown first wiring portion 1221. The conductive connection 150 includes a metal layer 152 electrically connected to the first wiring portion 1221 and a seed layer 151 covering the metal layer 152. In some embodiments, the material of the metal layer 152 may include copper or nano-twinned copper.

As shown in fig. 5F, the release layer 104 and the first carrier substrate 102 are removed, the resulting structure is flipped, and the first seed layer 106 is removed. Thus, the first transition layer 124 may be exposed. As shown in fig. 5G, the first transition layer 124 is removed and the first wiring portion 1221 is exposed.

As shown in fig. 5H, the second wiring portion 1222 that has been formed is bonded to the first wiring portion 1221. The process of forming the second wiring portion 1222 may be similar to the process of forming the first wiring portion 1221 described above. A second wiring portion 1222 may be formed by forming a release layer 204 on the second carrier substrate 202, forming a second seed layer 206 on the release layer 204, and growing a second nano-twin copper 1222 on the second seed layer 206. The second wiring portion 1222 is bonded to the first wiring portion 1221. Similarly, a second transition layer 134 is formed between the grown second wiring portion 1222 and the second seed layer 206.

As shown in fig. 5I, the release layer 204 and the second carrier substrate 202 are removed, and the second seed layer 206 is removed. Thus, the second transition layer 134 may be exposed. As shown in fig. 5J, the second transition layer 134 is removed and the second wiring portion 1222 is exposed.

As shown in fig. 5K, the third wiring portion 1223 which has been formed is bonded to the second wiring portion 1222. The process of forming the third wiring portion 1223 can be similar to the process of forming the first wiring portion 1221 and the second wiring portion 1222 described above. A third wiring portion 1223 may be formed by forming a release layer 304 on the third carrier substrate 302, forming a third seed layer 306 on the release layer 304, and growing third nano-twin copper 1223 on the third seed layer 306. The third wiring portion 1223 is bonded to the second wiring portion 1222. Similarly, a third transition layer 144 is formed between the third wiring portion 1223 of the nano-twinned copper material and the third seed layer 306.

As shown in fig. 5L, the release layer 304, the third carrier substrate 302 are removed, and the third seed layer 306 is removed. Thus, the third transition layer 144 may be exposed. The third transition layer 144 is removed and the third wire portion 1223 is exposed, then the wire 122 including the first wire portion 1221, the second wire portion 1222, and the third wire portion 1223 is connected to the die 160 by forming the conductive connection 130 (i.e., the first conductive connection) on the third wire portion 1223 of the wire 122. The conductive connection member 130 includes a metal layer 132 electrically connected to the third wiring portion 1223 and a seed layer 131 covering the metal layer 132. In some embodiments, the material of metal layer 132 may include copper. In other embodiments, the material of the metal layer 132 may include nano-twinned copper.

As shown in fig. 5M, an encapsulation material 170 is formed overlying the die 160, for example, by a molding process. The resulting structure is inverted and a planarization process is performed, exposing the through-holes 142 in the insertion layer 140. A dielectric layer 180 and pads 181 and connectors 182 connected to the through holes 142 are formed over the insertion layer 140. The structure shown in fig. 5M may then be inverted and bonded to substrate 200 to form the semiconductor structure shown in fig. 4.

Fig. 6 is a schematic diagram of a semiconductor structure according to an embodiment of the invention. Similar to the embodiment shown in fig. 4, the semiconductor structure includes a die 160 and a routing layer 190, the die 160 being disposed above the routing layer 190. There is no transition layer formed during the growth of the nano-twin copper material of the wire at the first junction surface 125 where the conductive connector 130 is electrically connected with the wire 122 and the second junction surface 126 where the conductive connector 150 is electrically connected with the wire 122.

The difference from the embodiment shown in fig. 4 is that the wiring 122 in the wiring layer 190 includes a first wiring portion 1221, a second wiring portion 1222, and a third wiring portion 1223. The material of the first and

third wiring portions

1221 and 1223 may be nano-twinned copper. The second wiring portion 1222 is a metal different from the materials of the first wiring portion 1221 and the third wiring portion 1223. The second wiring portion 1222 includes a seed layer 1227 and a metal layer 1228, and a material of the metal layer 1228 may include copper.

Fig. 7A-7J are schematic diagrams illustrating intermediate stages in a process of forming the semiconductor structure shown in fig. 6. First, as shown in fig. 7A, a first carrier substrate 102, a release layer 104 over the first carrier substrate 102, and a first seed layer 106 over the release layer 104 are provided. An insulating layer 108 is formed over the first seed layer 106. A patterned photoresist layer 212 is also formed over the insulating layer 108. The insulating layer 108 is patterned with a patterned photoresist layer 212, forming an opening 105 in the insulating layer 108. Nano-twinned copper 1223 is formed within the opening 105 in the insulating layer 108 and on the first seed layer 106. The nano-twin copper 1223 is formed as the third wiring portion 1223. The first transition layer 124 is formed between the formed third wiring portion 1223 and the first seed layer 106.

As shown in fig. 7B, the photoresist layer 212 is stripped and a planarization process is performed such that the third wiring portion 1223 is flush with the top surface of the insulating layer 108. The second wiring portion 1222 is formed on the third wiring portion 1223. The second wiring portion 1222 may include a seed layer 1227 and a metal layer 1228. The material of the metal layer 1228 may include copper. The second wiring portion 1222 may be a redistribution line of a redistribution layer (RDL).

As shown in fig. 7C, the insulating layer 108 is formed covering the seed layer 1227 and the metal layer 1228. And a patterned photoresist layer 212 is formed on the insulating layer 108. As shown in fig. 7D, the insulating layer 108 over the metal layer 1228 is patterned using the patterned photoresist layer 212, and the opening 205 over the metal layer 1228 is formed in the insulating layer 108.

As shown in fig. 7E, a metal material 1229 such as copper is formed within the opening 205 in the insulating layer 108, the metal material 1229 being formed as part of the second wiring portion 1222. The metal material 1229 is formed as a second wiring portion together with the seed layer 1227 and the metal layer 1228.

As shown in fig. 7F, the photoresist layer 212 is stripped. The first wiring portion 1221 which has been formed is bonded to the second wiring portion 1222. The process of forming the first wiring portion 1221 may be similar to the process of forming the third wiring portion 1223 described above. A seed layer (not shown) may be formed on the carrier substrate, and nano-twin copper may be grown on the seed layer to form the first wiring portion 1221. A conductive connection (i.e., a second conductive connection) 150 is formed on the first wiring portion 1221 to connect the wiring 122 including the first wiring portion 1221, the second wiring portion 1222, and the third wiring portion 1223 to the interposer 140. The conductive connection 150 includes a metal layer 152 electrically connected to the first wiring portion 1221 and a seed layer 151 covering the metal layer 152. In some embodiments, the material of metal layer 152 may include copper. In other embodiments, the material of the metal layer 152 may include nano-twinned copper.

Similarly, a second transition layer will be formed during the growth of the first wire portion 1221. The second transition layer has been removed prior to connecting the wire 122 to the interposer 140, and thus is not present, nor shown, at the interface where the first wire portion 1221 contacts the conductive connection 150 in fig. 7F.

As shown in fig. 7G, the structure shown in fig. 7F is inverted and the first carrier substrate 102, the release layer 104, and the first seed layer 106 are removed, exposing the first transition layer 124.

As shown in fig. 7H, the first transition layer 124 is removed, and a conductive connector (i.e., a first conductive connector) 130 including the seed layer 131 and the metal layer 132 is formed on the third wiring portion 1223 to connect the wiring 122 to the die 160.

As shown in fig. 7I, an encapsulation material 170 is molded covering the die 160.

As shown in fig. 7J, the structure shown in fig. 7I is inverted and a planarization process is performed, exposing the through-holes 142 in the insertion layer 140. A dielectric layer 180 and pads 181 and connectors 182 connected to the through holes 142 are formed over the insertion layer 140.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, comprising:

a wiring layer including an insulating layer and a wiring disposed in the insulating layer, the wiring including a nano-twin copper material, the wiring layer having a first surface;

a die disposed over the first surface; and

the first conductive connecting piece is connected between the wiring and the tube core, a first joint surface is arranged between the first conductive connecting piece and the wiring, the first joint surface is an interface of the first conductive connecting piece and the nano twin crystal copper material, a transition layer formed during the growth of the nano twin crystal copper material is not arranged at the first joint surface, and the transition layer has irregular crystal orientation.

2. The semiconductor structure of claim 1, wherein the first conductive connection comprises:

the metal layer is electrically connected with the nanometer twin crystal copper material; and

a seed layer disposed between the metal layer and the die.

3. The semiconductor structure of claim 1, further comprising:

a substrate disposed below a second surface of the wiring layer, the second surface being disposed opposite the first surface;

the wiring layer further comprises a second conductive connecting piece, the second conductive connecting piece is used for connecting the wiring to the substrate, a second joint surface is arranged between the second conductive connecting piece and the wiring, and the second joint surface is an interface of the second conductive connecting piece and the nano twin crystal copper material of the wiring, wherein the nano twin crystal copper material is electrically connected with the second conductive connecting piece.

4. The semiconductor structure of claim 1, wherein the wiring comprises:

a first wiring portion electrically connected to the first conductive connecting member;

a second wiring portion connected to the first wiring portion; and

a third wiring portion connected to the second wiring portion;

the first wiring portion and the third wiring portion are made of nano twin crystal copper, and the second wiring portion is made of metal different from the first wiring portion and the third wiring portion.

5. A method of forming a semiconductor structure, comprising:

forming an insulating layer and a wiring in the insulating layer, wherein forming the wiring includes:

forming a first seed layer on a first carrier substrate; and

forming the insulating layer with an opening on the first seed layer, and growing first nanometer twin copper on the first seed layer below the opening, wherein a first transition layer is formed between the grown first nanometer twin copper and the first seed layer;

removing the first carrier substrate;

removing the first seed layer and the first transition layer and exposing the wiring; and

connecting the wire to a die by forming a first conductive connector on an exposed surface of the wire, wherein the first conductive connector is electrically connected to the first nano-twinned copper of the wire to form a first bonding surface.

6. The method of forming a semiconductor structure of claim 5, further comprising, prior to removing the first carrier substrate:

and forming a second conductive connecting piece on the grown first nano-twin crystal copper, and connecting the wiring to an insertion layer through the second conductive connecting piece, wherein the second conductive connecting piece is electrically connected with the first nano-twin crystal copper of the wiring to form a second joint surface.

7. The method of forming a semiconductor structure of claim 5, further comprising:

connecting the die to an interposer via a second conductive connector, wherein the second conductive connector is electrically connected to the first nano-twin copper to form a second interface between the die and the interposer.

8. The method of forming a semiconductor structure of claim 5, wherein forming the first conductive connection comprises:

forming a metal layer electrically connected with the first nanometer twin crystal copper; and

an additional seed layer is formed overlying the metal layer.

9. The method of forming a semiconductor structure of claim 8,

the material of the metal layer comprises copper or nano twinned copper.

10. The method of forming a semiconductor structure of claim 5,

the first nano twinned copper has a (111) crystal orientation, and the first transition layer has an irregular crystal orientation.