CN114256165A

CN114256165A - Semiconductor packaging structure

Info

Publication number: CN114256165A
Application number: CN202011012626.6A
Authority: CN
Inventors: 吕文隆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2020-09-23
Filing date: 2020-09-23
Publication date: 2022-03-29

Abstract

The present invention provides a semiconductor packaging structure and a method for forming the same. The semiconductor package structure includes: a first encapsulation body; a first pad disposed on the same side of the substrate laterally spaced apart from the first encapsulation body; and a second encapsulation body disposed around the first pad and exposing the first pad s surface. The roughness of the upper surface of the second sealing body is greater than the roughness of the surface of the first pad. The embodiments of the present invention can at least avoid the problems existing in the existing film sealing methods, and can avoid the warpage problem of the packaging structure at the same time.

Description

Semiconductor packaging structure

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor package structure and a method for forming the same.

Background

System in Package (System in Package) offers more options for the end product in terms of multi-functionality, and can be protected safely and without losing functionality using, for example, encapsulation (Molding) or Coating (Coating). Wherein, the film coating mode has the direction selection characteristic so that the film coating mode is not easy to process on a fault plane or a complex structure; the film encapsulation method has the advantage of being able to operate several non-coplanar devices at one time, so the film encapsulation method is mostly used in the system level packaging at present.

However, the film sealing method must make an expensive Mold (Mold), thereby deriving the following problems: (1) special designs of the embossing (Pressing) at the stitching location must be considered, for example, the problem of damage to the circuit pattern, which can only be large and/or does not affect the circuit function. Such as when a large mold shift or exposure to the liquid on the substrate is desired, pattern damage and/or cracking; (2) due to the arrangement, demolding or position exposure of the mold, the electronic element is easy to be damaged by the mold; (3) the bevel edge of the molding compound formed requires increased space (or bottom area) and occupies more substrate area problems due to the draft angle required for demolding. Therefore, it is very challenging to apply the film sealing process to system-level packaging with complex structure.

In addition, the conventional film sealing process is to form a Mold cavity (Mold chase) at a high cost or to remove the Mold cavity after the Mold chase is formed (at a low cost). Therefore, it is also desirable to provide a low-cost operation method.

Disclosure of Invention

In view of the above problems in the related art, the present invention provides a semiconductor package structure and a method for forming the same, which can avoid the problems of the conventional film sealing method and the warpage of the package structure.

An embodiment of the present invention provides a semiconductor package structure, including: a first sealing body; the first bonding pad is arranged on the same side of the substrate at a distance from the first sealing body in the transverse direction; and a second sealing body disposed around the first pad and exposing a surface of the first pad. The roughness of the upper surface of the second sealing body is larger than that of the surface of the first bonding pad.

In some embodiments, a trench is formed in the first seal.

In some embodiments, the trench includes a through hole exposing the second pad covered by the first sealing body and a groove disposed in the first sealing body with the first sealing body between a bottom of the groove and the substrate.

In some embodiments, the roughness of the hole sidewall of the through-hole and the roughness of the groove wall of the groove are the same as the roughness of the upper surface of the second sealing body.

In some embodiments, the semiconductor package structure further comprises: and the shielding layer is positioned on the first sealing body and covers at least part of the surface of the first sealing body, the groove wall of the groove and the hole side wall of the through hole.

In some embodiments, the thickness of the second encapsulant is less than or equal to the thickness of the first pad.

In some embodiments, the roughness of the peripheral side surface of the first encapsulant is equal to the roughness of the upper surface of the second encapsulant.

In some embodiments, the semiconductor package structure further comprises: and a conductive element disposed on a surface of the first pad in direct physical contact.

In some embodiments, the semiconductor package structure further comprises: the first electronic element is electrically connected to the substrate, and the first sealing body covers the first electronic element.

In some embodiments, the semiconductor package structure further comprises: the second electronic element is arranged on the other side of the substrate and is respectively positioned on two opposite sides of the substrate with the first electronic element.

In some embodiments, a third pad is disposed between the second electronic component and the substrate.

In some embodiments, the semiconductor package structure further comprises: and a third sealing body covering the second electronic element and the third pad.

In some embodiments, the first and second seals are the same material and are a single piece.

Embodiments of the present invention also provide a method of forming a semiconductor package structure, including: forming a patterned layer on a first sealing material layer on a first side of a substrate, wherein the first sealing material layer covers the group of component devices on the first side; and performing dry blasting on the first sealing material layer by using the patterned layer as a mask to expose at least a first bonding pad in the component device group, wherein the roughness of the exposed surface of the first bonding pad is smaller than that of the surface of the first sealing material layer formed by the dry blasting treatment.

In some embodiments, the first sealing material layer is configured by dry blasting to include a first sealing body and a second sealing body surrounding the first pad, wherein a surface roughness of the second sealing body formed by dry blasting is larger than a roughness of an exposed surface of the first pad.

In some embodiments, the dry blasting forms a trench in the first sealing material layer, the trench comprising a recess and a through-via spaced apart in the first sealing body, wherein the recess is a blind via and the through-via exposes the second pad in the component device group.

In some embodiments, the dry blasting uses blasting comprising: one or more of ceramic powder, resin powder, glass powder, steel ball powder, iron ball powder, oxide powder or plastic powder.

In some embodiments, the pressure is 2kg/cm²To 10kg/cm²Dry blasting is performed at a temperature in the range of-30 ℃ to-60 ℃.

In some embodiments, the exposed surface of the first pad is physically connected to a solder ball.

In some embodiments, before the dry blasting treatment, a second sealing material layer is formed on a second side of the substrate opposite to the first side, the second sealing material layer is used for covering the component device group on the second side, and before the dry blasting treatment, the equivalent thermal expansion coefficient of the semiconductor packaging structure on the first side is larger than that on the second side.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-14 are schematic diagrams of various stages of a method of forming a semiconductor package structure, according to an embodiment of the invention.

Fig. 15A and 15B are schematic views of PoP and post-SMT semiconductor package structures according to embodiments of the present invention.

Fig. 16-22 are schematic diagrams of stages of a method of forming a semiconductor package structure according to another embodiment of the invention.

Fig. 23A to 24 are schematic views of semiconductor package structures according to other embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The invention provides a semiconductor packaging structure and a forming method thereof, which can avoid the problems in the existing film sealing mode by performing dry sand blasting treatment on a sealing material of the semiconductor packaging structure to form a rough surface on the surfaces of the exposed sealing material and a metal layer.

As shown in fig. 1, a method of forming a semiconductor package structure first provides a substrate 102. The substrate has a first side 111 and a second side 112 opposite the first side 111. A patterned metal layer 114 has been formed on the first side 111 and the second side 112 of the substrate 102. In some embodiments, the substrate 102 may be an organic substrate, such as a BT resin substrate, a polypropylene (PP) substrate, or an ajinomoto build-up film (ABF) substrate. In some embodiments, the substrate 102 may be an inorganic substrate, such as a glass substrate, a silicon substrate, a ceramic substrate, or a metal substrate. The substrate 102 may be a square, circular, or other shaped substrate.

Then, as shown in fig. 2, a component device group bonded to the patterned metal layer 114 is formed on the first side 111 of the substrate 102. The component device group on the first side 111 comprises a plurality of first electronic components 120. The plurality of first electronic components 120 may be bonded to the first side 111 of the substrate 102, for example by a SMT (surface mount technology) die process.

As shown in fig. 3, a first sealing material layer 122 is injected on the first side 111 of the substrate 102 using a mold 124. The resulting structure is inverted after the first sealing material layer 122 is injected. The injected first sealing material layer 122 is formed as a first sealing body 181, as shown in fig. 4. The first encapsulant 181 covers the plurality of first electronic components 120 on the first side 111 of the substrate 102. The material of the first sealing body 181 may be a Molding Compound (Molding Compound). In fig. 4, a component device group is formed on the second side 112 of the substrate 102, bonded to a patterned metal layer 114. The component device group on the second side 112 includes a plurality of second electronic components 140. A plurality of second electronic components 140 may be bonded to second side 112 of substrate 102, for example, by an SMT pick and place process.

As shown in fig. 5, a second sealing material layer 146 is injected on the second side 112 of the substrate using a mold 144, the second sealing material layer 146 covering the plurality of second electronic components 140 on the second side 112 of the substrate 102. The second sealing material layer 146 may cover the entire surface of the second side 112. The material of the second sealing material layer 146 may be a molding compound. The first sealing material layer 122 and the second sealing material layer 146 may be the same material or different materials. The first sealing material layer 122 and the second sealing material layer 146 may also be referred to as a protective layer. The first and second

sealing material layers

122 and 146 may be formed using processes such as molding, printing, potting, dipping, laminating, and the like.

As shown in fig. 6, a first photoresist layer 152 is formed on the second sealing material layer 146. An exposure and development process is performed on the first photoresist layer 152 to form a patterned first photoresist layer 152, as shown in fig. 7. Subsequently, as shown in fig. 8, a second photoresist layer 154 is formed on the patterned first photoresist layer 152. An exposure and development process is performed on the second photoresist layer 154 to pattern the second photoresist layer 154, forming a patterned second photoresist layer 154 as shown in fig. 9A. The patterned first and second photoresist layers 152 and 154 will act as a mask to selectively remove portions of the second sealing material layer 146. The process of patterning the first and second photoresist layers 152 and 154 to form a mask is exemplary, and any other suitable mask may be formed and used as needed to remove the portion of the second sealing material layer 146.

In some embodiments, the CTE (coefficient of thermal expansion) of the semiconductor package structure at the second side 112 is greater than the equivalent coefficient of thermal expansion of the first side 111. The second side 112 with larger equivalent CTE is warped to bend toward the second side 112 after the package structure is cooled (cooling), so that the package structure has a smiley face-like shape.

As shown in fig. 9A, dry blasting 220 is performed on the formed second sealing material layer 146. As shown in fig. 9B, in the dry blasting process 220, nitrogen gas is supplied while the blasting 222 is dropped, and the high-pressure nitrogen gas ejects the dropped blasting 222 to the surface of the second sealing material layer 146, so that a part of the second sealing material layer 146 can be removed. In some embodiments, the nitrogen temperature may be below-20 ℃, which may embrittle the second layer of sealing material 146. In some embodiments, the nitrogen gas temperature may be less than-30 ℃, which may vitrify the second sealing material layer 146. In some embodiments, a pressure of 2kg/cm is provided²To 10kg/cm²High pressure nitrogen in the range of-30 ℃ to-60 ℃.

In some embodiments, the blasting used by the dry blasting process 220 includes: one or more of ceramic powder, resin powder, glass powder, steel ball powder, iron ball powder, oxide powder or plastic powder. In some embodiments, the particle size of the blasting powder may be in the range of 2 μm to 10 μm.

Different grit blasting powders of different particle sizes produce different roughness of the rough surface. When the ceramic powder having a particle diameter in the range of 5 to 10 μm is used, the roughness of the surface of the formed molding compound is in the range of 4 to 12 μm, and the roughness of the surface of the formed copper is in the range of 3 to 8 μm. When the resin powder having a particle diameter in the range of 1 μm to 3 μm is used, the roughness of the surface of the formed molding compound is in the range of 0.5 μm to 5 μm, and the roughness of the surface of the formed copper is in the range of 0.5 μm to 3 μm. When the glass powder having a particle diameter in the range of 3 to 7 μm is used, the roughness of the surface of the formed molding compound is in the range of 2 to 7 μm, and the roughness of the surface of the formed copper is in the range of 1 to 5 μm.

Fig. 10A is a side view of the semiconductor structure after performing dry blasting. Fig. 10B is a top view at the plane of line a-a 'of fig. 10A, and fig. 10A is a side view at the section of line a-a' of fig. 10B. As shown in fig. 10A and 10B, after the dry blasting 220, the dry blasting 220 removes a portion of the second sealing material layer 146 while also exposing at least the first pads 168 on the second side 112. The remaining second encapsulant layer 146 includes a second encapsulant 162 encapsulating the plurality of second electronic components 140 and a third encapsulant 164 surrounding the first pads 168 and exposing the first pads. Due to the dry blasting 220, the surfaces of the processed second sealing body 162, third sealing body 164, and first pad 168 will be formed as rough surfaces having a certain roughness. Higher roughness and facilitates subsequent bonding. The second seal 162 is the same material as the third seal 164. In the illustrated embodiment, the second sealing body 162 and the third sealing body 164 are interconnected to form a unitary piece.

In one embodiment, the thickness of the first pad 168 may be greater than the thickness of the third encapsulant. In one embodiment, the thickness of the first pad 168 may be equal to the thickness of the third encapsulant. In one embodiment, the material of the first pad 168 may be a metal material, such as an alloy of any one or more of copper (Cu), silver (Ag), gold (Au), and palladium (Pb). In some embodiments, the first pads 168 may include a metal formed using, for example, sputtering, electroplating, or electroless plating processes. In some embodiments, the first pads 168 may include a compound formed, for example, using printing, potting, and dipping processes.

Since the surfaces of the non-metallic material of the second and

third seals

162, 168 are more brittle than the metallic material of the first pad 168 (e.g., copper), the roughness of the grit blasted surfaces of the second and

third seals

162, 168 is greater than the roughness of the surface of the first pad 168. In some embodiments, the roughness of the sides of the second seal 162 may be equal to the roughness of the upper surface of the third seal 164. In some embodiments, after performing the dry blasting, the roughness of the side surface of the second seal 162 is in the range of 0.5 μm to 12 μm, and the roughness of the upper surface of the third seal 164 is in the range of 0.5 μm to 12 μm. The roughness of the upper surface of the first pad 168 is in the range of 0.5 μm to 8 μm. The rough surface of the first pad 168 provides better adhesion than a smooth surface. In addition, the roughened surface provides a larger bonding area that can prevent solder from penetrating to the interface between the first pad 168 and the substrate.

With continued reference to fig. 10A and 10B. The dry blasting also forms trenches in the second seal 162, including spaced apart recesses 172 and through holes 174 in the second seal 162. It should be understood that although the roughened surface of the second sealing body 162 formed by grit blasting is not explicitly shown in fig. 10B for clarity in illustrating the shape of the grooves 172 and through-holes 174, the surface of the second sealing body 162 defining the grooves 172 and through-holes 174 is roughened and has the same roughness as the side surfaces of the second sealing body 162. The recess 172 is disposed in the second sealing body 162, and the recess 172 is a blind hole that does not penetrate the second sealing body 162. A second seal 162 is provided between the bottom of the recess 172 and the substrate 102. The through hole 174 penetrates the second sealing body 162 and exposes the second pad 161. The roughness of the hole side wall of the through hole 174 and the roughness of the groove wall of the recessed groove are the same as the roughness of the side surface of the second sealing body 162 or the upper surface of the third sealing body 164.

The through-hole 174 and the groove 172 having a small size can be formed by using dry blasting. In some embodiments, the through-holes 174 are less than 70 μm in diameter. The width of the groove 172 is less than 30 μm. And it is difficult to form small-sized through holes and grooves by the laser process and the molding process, compared to the laser process and the molding process.

As shown in fig. 10A, the seed layer 182 is commonly covered on the second sealing body 162, the third sealing body 164, the first bonding pad 168, the groove 172, and the through hole 174. As shown in fig. 11, a third photoresist layer 179 is formed on the second sealing body 162, the third sealing body 164, and the first pads 168. A third photoresist layer 179 fills the recess 172 and the through hole 174. As shown in fig. 12, the third photoresist layer 179 is patterned to form an opening 177 in the third photoresist layer 179. The opening 177 leaves a portion of the second sealing body 162 covering the plurality of second electronic components 140, and exposes the recess 172 and the through-hole 174. A patterned third photoresist layer 179 overlies the first pads 168.

In some embodiments, the material of any of the first seal 181, the second seal 162, and the third seal 164 can be organic, oxide (e.g., silicon oxide, SiO)_xSilicon nitride SiN_xTaO, tantalum oxide_x) And/or inorganic (e.g., polyamide PA, polyimide PI, epoxy, polyphenylene benzole PBO, molding compound).

In some embodiments, the overall shape of the second and

third seal bodies

162, 164 may be variously shaped, such as trapezoidal, triangular, square, circular, rectangular, cross-shaped, polygonal, and/or irregular.

In one embodiment, each of the second and third sealing

bodies

162, 164 may include a first layer of sealing body and a second layer of sealing body covering the first layer of sealing body. In other embodiments, each of the second and third encapsulants can also include a greater number of layers. In one embodiment, the thickness of the second encapsulant may be different.

As shown in fig. 12, a shield layer 184 is formed in the opening 177. The material of the shielding layer 184 may be a metal. The third photoresist layer 179 is then removed. After removing the third photoresist layer 179, the shielding layer 184 is located on the second sealing body 162, and the shielding layer 184 covers at least a part of the surface of the second sealing body 162, and the shielding layer 184 also covers the groove walls of the recess 172 and the hole sidewalls of the through holes 174. As shown in fig. 13, the third photoresist layer 179 is removed, and the seed layer 182 not covered by the shield layer 184 is removed.

As shown in fig. 14, a conductive element 195 is placed on the first pad 168 and dicing may be performed to obtain a final package structure. The upper surface of the first pad 168 is in physical connection, i.e., in direct contact, with the conductive element 195. In some embodiments, the conductive elements 195 may be solder balls. In some embodiments, the Conductive element 195 may include Conductive glue, epoxy, Anisotropic Conductive Film (ACF), or Anisotropic Conductive adhesive (adhesive). In some embodiments, the conductive elements 195 may be formed, for example, using printing, potting, and dipping processes.

The present invention provides several benefits by using dry blasting: the problem of oxidation of the metal (e.g. copper) can be avoided and the generation of waste liquids, e.g. from etching or wet blasting processes, can be avoided; the grit blasting may generate compressive stress to resist warping of the stress on the second side, the rough surface of the side of the second encapsulant may overcome the warped lateral stress; the sealing body is formed without mould pressing, so that no crack damage is generated, and no damage is caused to the circuit on the surface of the substrate/PCB; low cost and no need of grinding or CMP. In addition, it also allows for subsequent PoP (package on package) structure (as in fig. 15A) or/and post SMT (as in fig. 15B) manufacturing designs. As shown in fig. 15B, additional electronic components 1506 are bonded on the exposed pads 1502 by an SMT process.

Fig. 16-22 are schematic diagrams of stages of a method of forming a semiconductor package structure according to another embodiment of the invention. The method of this embodiment begins with the steps shown in fig. 16. The steps described above with respect to fig. 1-3 may be performed before the steps shown in fig. 16.

As shown in fig. 16, the method of forming a semiconductor package structure first provides a substrate 102. The substrate 102 has a first side 111 and a second side 112 opposite the first side 111. A patterned metal layer 114 has been formed on the first side 111 and the second side 112 of the substrate 102. A plurality of first electronic components 120 are formed on the first side 111 of the substrate 102, bonded to the patterned metal layer 114. Forming a first encapsulant 181. The first encapsulant 181 covers the plurality of first electronic components 120 on the first side 111 of the substrate 102. The resulting structure is then inverted to perform the steps shown in fig. 16.

In fig. 16, a plurality of second electronic components 140 are formed on the second side 112 of the substrate 102, bonded to the patterned metal layer 114. As shown in fig. 17, a second sealing material layer 146 is injected on the second side 112 of the substrate 102 using a mold 144, the second sealing material layer 146 covering the plurality of second electronic components 140 on the second side 112 of the substrate 102. The second sealing material layer 146 may cover the entire surface of the second side 112.

As shown in fig. 18, dry blasting 220 is performed on the formed second sealing material layer 146. The dry blasting removes portions of the second sealing material layer 146, and the remaining second sealing material layer 146 includes a second sealing body 162 that seals the plurality of second electronic components 140. The second seal 162 exposes the metal layer 114 on the second side 112. Due to the dry blasting 220, the side surfaces of the treated second sealing body 162 and the upper surface of the metal layer 114 are formed as rough surfaces.

Then, as shown in fig. 19, a photoresist layer 151 is formed over the second sealing body 162 and the exposed metal layer 114. An exposure and development process is performed on the photoresist layer 151 to pattern the photoresist layer 151. As shown in fig. 20, the patterned photoresist layer 151 exposes the second seal 162 and a portion of the metal layer 114. The metal layer 114 is patterned to form first pads 168 by performing an etching process using the openings 153 in the patterned photoresist layer 151, as shown in fig. 21. The first pads 168 are laterally spaced from the second encapsulant 162, and no encapsulant is formed between the first pads 168 and the second encapsulant 162 and between adjacent first pads 168.

As shown in fig. 22, a conductive element 195 is placed on the first pad 168 and dicing may be performed to obtain a final package structure. The upper surface of the first pad 168 is physically connected to the conductive element 195. As shown in fig. 22, the second sealing body 162 may not have a through hole or a groove. In some embodiments, a shielding layer (not shown) may be formed on the second seal 162. In some embodiments, a shielding layer (not shown) may not be formed.

Fig. 23A to 23C are schematic views of semiconductor package structures according to other embodiments of the present invention. As shown in fig. 23A, the semiconductor package structure may include a substrate 102, the substrate 102 having a first side 111 and a second side 112 disposed opposite to each other. The first encapsulant 181 is disposed over the first side 111 and the second encapsulant 162 is disposed over the second side 112 of the substrate 102. The first pads 168 are disposed on the second side 112 of the substrate 102 laterally spaced apart from the second seal 162. The semiconductor package structure further includes a third sealing body 164, the third sealing body 164 being disposed around the first pad 168 and exposing a surface of the first pad 168. The roughness of the upper surface of the third sealing body 164 is greater than the roughness of the surface of the first pad 168.

As shown in fig. 23A, dry blasting may also be performed on the first seal 181 on the first side 11 of the substrate 102. The side surface of the first sealing body 181 after the treatment is formed into a rough surface. As shown in fig. 23B and 23C, the electronic components and the seal 166 may be formed on a single side of the substrate 102 without forming the electronic components and the seal on the other side. The seal 166 formed on a single side may not have a trench, as shown in FIG. 23B. The seal 166 formed on a single side may have a trench 172 as shown in fig. 23C.

In one embodiment, as shown in fig. 24, a bonding wire 191 is used to connect to the first pad 168. A bonding wire 191 may connect the first pad 168 to a connection 197 on the second encapsulant 162.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package structure, comprising:

a first sealing body;

a first pad disposed on the same side of the substrate laterally spaced from the first encapsulant;

a second sealing body disposed around the first pad and exposing a surface of the first pad;

wherein the roughness of the upper surface of the second sealing body is greater than the roughness of the surface of the first bonding pad.

2. The semiconductor package structure of claim 1,

a trench is formed in the first seal.

3. The semiconductor package structure of claim 2,

the groove comprises a through hole and a groove,

the through hole exposes the second pad covered by the first sealing body, the groove is arranged in the first sealing body, and the first sealing body is arranged between the bottom of the groove and the substrate.

4. The semiconductor package structure of claim 3,

the roughness of the hole side wall of the through hole and the roughness of the groove wall of the groove are both the same as the roughness of the upper surface of the second sealing body.

5. The semiconductor package structure of claim 3, further comprising:

and the shielding layer is positioned on the first sealing body and covers at least part of the surface of the first sealing body, the groove wall of the groove and the hole side wall of the through hole.

6. The semiconductor package structure of claim 1 or 4,

the roughness of the outer peripheral side surface of the first sealing body is equal to the roughness of the upper surface of the second sealing body.

7. The semiconductor package structure of claim 1, further comprising:

a conductive element disposed in direct physical contact on the surface of the first pad.

8. The semiconductor package structure of claim 1, further comprising:

a first electronic component electrically connected to the substrate, the first sealing body covering the first electronic component.

9. The semiconductor package structure of claim 8, further comprising:

and the second electronic element is arranged on the other side of the substrate and is respectively positioned on two opposite sides of the substrate together with the first electronic element.

10. The semiconductor package structure of claim 9,

a third pad is arranged between the second electronic element and the substrate.