CN114242726A - Flash memory and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 105
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 238000000034 method Methods 0.000 claims description 81
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- 230000008569 process Effects 0.000 claims description 52
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 41
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 23
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 238000006243 chemical reaction Methods 0.000 claims description 14
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- 229910052734 helium Inorganic materials 0.000 claims description 14
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 14
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 8
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
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Abstract
In the flash memory and the manufacturing method thereof provided by the invention, the angle between the bottom wall and the side wall of the isolation groove formed in the substrate is 98-102 degrees, so that the contact surface between the shallow groove isolation structure and the substrate can be increased, the effective supporting volume of the substrate can be increased, the stress born in unit volume can be reduced, the lattice dislocation of the substrate can be reduced, and the leakage current in the flash memory can be reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor preparation, in particular to a flash memory and a manufacturing method thereof.
Background
In flash memory technology, the quality of the Shallow Trench Isolation (STI) in a flash memory device determines the basic electrical performance of the flash memory device. With the rapid development of semiconductor manufacturing processes, the feature size of flash memories is significantly reduced, and in order to achieve higher circuit density, not only the feature size of flash memories is reduced, but also the size of shallow trench isolation structures in flash memories is correspondingly reduced. However, in practical applications, it is found that an angle between a sidewall and a bottom wall of the trench in the substrate is generally small, for example, smaller than 92 °, that is, an inclination angle of the sidewall of the trench is small, and as a film layer (for example, a floating gate structure) on the substrate is thickened, accordingly, the substrate is subjected to a larger mechanical stress (for example, compressive stress) and the angle between the sidewall and the bottom wall of the trench is smaller than 92 °, which results in a smaller effective supporting volume of the substrate and a larger stress per unit volume, thus resulting in a lattice dislocation in the substrate, and thus causing a defect of dislocation and increased leakage in the flash memory.
Disclosure of Invention
The invention aims to provide a flash memory and a manufacturing method thereof, which aim to solve the problems of dislocation and electric leakage increase in the flash memory.
To solve the above technical problem, the present invention provides a flash memory, comprising:
providing a substrate, wherein a floating gate structure layer is formed on the substrate;
sequentially etching the floating gate structure layer and the substrate to form an isolation trench, wherein the angle between the side wall and the bottom wall of the isolation trench is 98-102 degrees, wherein, the gas for etching the floating gate structure layer comprises chlorine and hydrogen bromide, the gas flow of the chlorine is 75 sccm-85 sccm, the gas flow of the hydrogen bromide is 150 sccm-170 sccm, the gas for etching the substrate comprises chlorine, helium, oxygen, hydrogen bromide, carbon tetrafluoride and nitrogen, in the process of etching the substrate, the gas flow of the chlorine gas is 5sccm-15sccm, the gas flow rate of the helium gas and the oxygen gas is 15sccm-25sccm, the gas flow of the hydrogen bromide is 120sccm-160sccm, the gas flow of the carbon tetrafluoride is 10 sccm-15sccm, and the gas flow of the nitrogen is 5 sccm-10 sccm; and the number of the first and second groups,
and filling an isolation layer in the isolation groove to form a shallow groove isolation structure.
Optionally, in the method for manufacturing the flash memory, the method for sequentially etching the floating gate structure layer and the substrate to form the isolation trench includes:
sequentially forming a hard mask layer, an anti-reflection layer and a graphical photoresist layer on the floating gate structure layer;
sequentially etching the anti-reflection layer, the hard mask layer, the floating gate structure layer and the substrate by taking the patterned photoresist layer as a mask to form the isolation groove; and the number of the first and second groups,
and removing the patterned photoresist layer and the anti-reflection layer.
Optionally, in the method for manufacturing a flash memory, the hard mask layer, the anti-reflection layer, the floating gate structure layer and the substrate are etched by a plasma etching process, wherein a gas for etching the anti-reflection layer includes hydrogen bromide and carbon tetrafluoride, and a gas flow rate of the hydrogen bromide is 25 seem to 35 seem and a gas flow rate of the carbon tetrafluoride is 35 seem to 45 seem in a process of etching the anti-reflection layer; the gas for etching the hard mask layer comprises helium, carbon tetrafluoride and difluoromethane, and in the process of etching the hard mask layer, the gas flow of the helium is 180 sccm-200 sccm, the gas flow of the carbon tetrafluoride is 35 sccm-45 sccm, and the gas flow of the difluoromethane is 5 sccm-10 sccm.
Optionally, in the method for manufacturing the flash memory, during the process of etching the anti-reflection layer, the pressure in the reaction chamber is 7mT to 12mT, the radio frequency power of the upper electrode is 245W to 255W, and the voltage of the lower electrode is-405V to-395V; in the process of etching the hard mask layer, the pressure in the reaction chamber is 7 mT-12 mT, the radio frequency power of the upper electrode is 595W-605W, and the voltage of the lower electrode is-295V-305V; in the process of etching the floating gate structure layer, the pressure in the reaction chamber is 15 mT-30 mT, the radio frequency power of the upper electrode is 295W-305W, and the voltage of the lower electrode is-95V-105V; in the process of etching the substrate, the pressure in the reaction chamber is 20 mT-25 mT, the radio frequency power of the upper electrode is 595W-605W, and the voltage of the lower electrode is-165V-155V.
Optionally, in the method for manufacturing a flash memory, before the isolation layer is filled in the isolation trench, annealing is performed on the substrate, where the annealing temperature is 800 ℃ to 1100 ℃.
Optionally, in the method for manufacturing a flash memory, the isolation layer includes a first oxide layer and a second oxide layer, the first oxide layer covers a sidewall and a bottom wall of the isolation trench, and the second oxide layer covers the first isolation layer and fills the isolation trench.
Optionally, in the method for manufacturing a flash memory, the first oxide layer and the second oxide layer are made of silicon dioxide, the first oxide layer is formed by a furnace tube oxidation process, and the second oxide layer is formed by a high aspect ratio process or a high density plasma chemical vapor deposition process.
Optionally, in the method for manufacturing a flash memory, the depth of the isolation trench is 3000 to 6000 angstroms, and the aspect ratio of the isolation trench is 4: 1-1: 1.
based on the same inventive concept, the present invention also provides a flash memory, comprising:
a substrate;
a floating gate structure layer formed on the substrate;
an isolation trench penetrating through the floating gate structure layer and extending into the substrate, wherein an angle between a side wall and a bottom wall of the isolation trench is 98-102 degrees;
and the isolation layer and the isolation groove form a shallow groove isolation structure.
In the flash memory and the manufacturing method thereof provided by the invention, the angle between the bottom wall and the side wall of the isolation groove formed in the substrate is 98-102 degrees, compared with the prior art, the contact surface between the shallow groove isolation structure and the substrate can be increased, meanwhile, the effective supporting volume of the substrate can be increased, the stress born in unit volume can be reduced, the lattice dislocation of the substrate can be reduced, the problem of dislocation defect in the flash memory can be solved, and the leakage current in the flash memory can be reduced.
Drawings
FIG. 1 is a flow chart illustrating a method for manufacturing a flash memory according to an embodiment of the present invention;
FIGS. 2 to 7 are schematic cross-sectional views of structures formed in a method for manufacturing a flash memory according to an embodiment of the present invention;
wherein the reference numerals are as follows:
100-a substrate; 110-floating gate structure layer; 120-hard mask layer; 130-a reflective layer; 140-isolation trenches; 150-an isolation layer; 151-first oxide layer; 152-second oxide layer.
Detailed Description
The flash memory and the method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1 is a flow chart illustrating a method for manufacturing a flash memory according to the present invention. As shown in fig. 1, the method for manufacturing the flash memory includes:
step S1: providing a substrate, wherein a floating gate structure layer is formed on the substrate;
step S2: sequentially etching the floating gate structure layer and the substrate to form an isolation trench, wherein the angle between the side wall and the bottom wall of the isolation trench is 98-102 degrees, wherein, the gas for etching the floating gate structure layer comprises chlorine and hydrogen bromide, the gas flow of the chlorine is 75 sccm-85 sccm, the gas flow of the hydrogen bromide is 150 sccm-170 sccm, the gas for etching the substrate comprises chlorine, helium, oxygen, hydrogen bromide, carbon tetrafluoride and nitrogen, in the process of etching the floating gate structure layer, the gas flow of the chlorine gas is 5sccm-15sccm, the gas flow rate of the helium gas and the oxygen gas is 15sccm-25sccm, the gas flow of the hydrogen bromide is 120sccm-160sccm, the gas flow of the carbon tetrafluoride is 10 sccm-15sccm, and the gas flow of the nitrogen is 5 sccm-10 sccm; and the number of the first and second groups,
step S3: and filling an isolation layer in the isolation groove to form a shallow groove isolation structure.
Fig. 2 to 7 are schematic cross-sectional views of structures formed in the method for manufacturing a flash memory according to an embodiment of the invention. The following describes the manufacturing method of the flash memory provided by the present invention in more detail with reference to fig. 2 to 7.
First, as shown in fig. 2, step S1 is performed to provide a substrate 100, and a floating gate structure layer 110 is formed on the substrate 100. The material of the substrate 100 may include silicon, germanium, silicon carbide, or the like, and the substrate 100 in this embodiment is a silicon substrate. The floating gate structure layer 110 may include a floating gate oxide layer (not shown) and a floating gate layer (not shown) on the floating gate oxide layer, wherein the floating gate oxide layer may be made of silicon dioxide and may have a thickness of 90 angstroms to 110 angstroms. The floating gate layer may be made of polysilicon and may have a thickness of 800 to 900 angstroms, for example 825 angstroms.
Then, as shown in fig. 3 to 5, step S2 is performed to sequentially etch the floating gate structure layer 110 and the substrate 100 to form an isolation trench 140, where an angle α between a sidewall and a bottom wall of the isolation trench 140 is 98 ° to 102 °. The method for sequentially etching the floating gate structure layer 110 and the substrate 100 includes: first, as shown in fig. 3 to 4, a hard mask layer 120, an anti-reflection layer 130 and a patterned photoresist layer (not shown) are sequentially formed on the floating gate structure layer. Specifically, the hard mask layer 120 may be made of silicon nitride or silicon oxynitride, and the thickness may be 1000 to 1100 angstroms, and the hard mask layer 120 may be formed by a chemical vapor deposition process. The anti-reflective layer 130 may be made of organic material, and the thickness thereof may be 800 to 850 angstroms, and the anti-reflective layer 130 may reduce a standing wave effect generated in the process of forming the patterned photoresist layer. The patterned photoresist layer has an opening therein exposing a portion of the anti-reflective layer 130, the opening defining the location of the isolation trench 140.
Then, as shown in fig. 5, the anti-reflection layer 130, the hard mask layer 120, the floating gate structure layer 110, and the substrate 100 are sequentially etched using the patterned photoresist layer as a mask to form the isolation trench 140, where the width of the isolation trench 140 may be 3000 angstroms to 6000 angstroms, such as 3000 angstroms, 3500 angstroms, 4000 angstroms, 5000 angstroms, 5500 angstroms, or 6000 angstroms. After the isolation trench 140 is formed, an angle α between a bottom wall and a sidewall of the isolation trench 140 is 98 ° to 102 °, for example, 98 °, 99 °, 100 °, 101 ° or 102 °, and compared with the prior art, the contact area between the substrate 100 and a subsequently formed shallow trench isolation structure can be increased, and meanwhile, the effective support volume of the substrate 100 can be increased, so that the stress borne in a unit volume is reduced, thereby reducing the lattice dislocation of the substrate 100, further reducing the leakage current in the flash memory 100, and improving the breakdown voltage.
In a preferred embodiment, the hard mask layer 120, the anti-reflection layer 130, the floating gate structure layer 110 and the substrate 100 are etched by a plasma etching process. Since there is a certain requirement for the angle between the sidewall and the bottom wall of the isolation trench 140, that is, the sidewall of the isolation trench 140 needs to be inclined by a certain angle, different lateral and longitudinal etches (i.e., anisotropic etches) need to be performed, and the inclination of the sidewall of the isolation trench 140 (i.e., the angle α between the sidewall and the bottom wall of the isolation trench 140) needs to be controlled during the etching process, while the plasma etching process realizes the etching based on the physical and chemical interactions between the etched structures by the ions or activities in the plasma, so that the etching amount can be better controlled, and preferably, the plasma etching method can be selected for etching.
In this embodiment, in the process of etching the anti-reflective layer by the plasma etching process, the gas used includes hydrogen bromide (HBr) and carbon tetrafluoride (CF)4) In the process of etching the anti-reflection layer 130, the gas flow of the hydrogen bromide is 25sccm to 35sccm, and the gas flow of the carbon tetrafluoride is 35sccm to 45 sccm; the gas for etching the hard mask layer 120 includes helium (He) and carbon tetrafluoride (CF)4) And difluoromethane (CH)2F2) In the process of etching the hard mask layer 120, the gas flow of the helium gas is 180sccm to 200sccm, the gas flow of the carbon tetrafluoride is 35sccm to 45sccm, and the gas flow of the difluoromethane is 5sccm to 10 sccm.
In this embodiment, the anti-reflection layer 130, the hard mask layer 120, the floating gate structure layer 110 and the substrate 100 may be etched in one process chamber. Furthermore, after finishing the etching of the anti-reflection layer, the gas in the process chamber is replaced, namely chlorine (Cl) is introduced into the process chamber2) And hydrogen bromide (HBr) to etch the floating gate junctionA layer 110 is formed. In the process of etching the floating gate structure layer 110, the gas flow rate of the chlorine gas is 75sccm to 85sccm, and the gas flow rate of the hydrogen bromide is 150sccm to 170 sccm. The gas for etching the substrate 100 includes chlorine gas, helium gas (He), and oxygen gas (O)2) Hydrogen bromide (HBr), carbon tetrafluoride (CF)4) And nitrogen (N)2) In the process of etching the substrate, the gas flow of the chlorine gas is 5sccm-15sccm, the gas flow of the helium gas and the oxygen gas is 15sccm-25sccm, the gas flow of the hydrogen bromide is 120sccm-160sccm, the gas flow of the carbon tetrafluoride is 10 sccm-15sccm, the gas flow of the nitrogen gas is 5 sccm-10 sccm, and in addition, the volume ratio of the helium gas to the oxygen gas is 7:3, so that the appearance of the isolation trench can be better controlled. In this embodiment, when different films are etched, the flow rate of the etching gas is adjusted for the currently etched film, so that the angle between the sidewall and the bottom wall of the isolation trench can be better controlled, and the angle between the sidewall and the bottom wall of the isolation trench is between 98 ° and 102 °.
In addition, the process parameters (reflecting the pressure in the chamber, the rf power of the upper electrode, and the voltage of the lower electrode) are different when the anti-reflection layer 130, the hard mask layer 120, the floating gate structure layer 110, and the substrate 100 are etched, so as to control the angle between the bottom wall and the sidewall of the isolation trench 140. Specifically, in the process of etching the anti-reflection layer 130, the pressure in the reaction chamber is 7 mT-12 mT, the radio frequency power of the upper electrode is 245W-255W, such as 250W, and the voltage of the lower electrode is-405V-395V, such as-400V. In the process of etching the hard mask layer 120, the pressure in the reaction chamber is 7 mT-12 mT, the radio frequency power of the upper electrode is 595W-605W, such as 600W, and the voltage of the lower electrode is-295V-305V, such as 300V; in the process of etching the floating gate structure layer, the pressure in the reaction chamber is 15 mT-30 mT, the radio frequency power of the upper electrode is 295W-305W, and the voltage of the lower electrode is-95V-105V; in the process of etching the substrate 100, the pressure in the reaction chamber is 20 mT-25 mT, the radio frequency power of the upper electrode is 595W-605W, and the voltage of the lower electrode is-165V-155V.
In this embodiment, in the process of etching the hard mask layer 120 and the anti-reflection layer 130, an emission spectroscopy (OES) method is used to detect an etching end point, and receive an optical signal reflected by the anti-reflection layer 130 or the hard mask layer 120, and characterize the etching process according to the intensity change of the received optical signal, so as to control the depth of the formed isolation trench 140, the thickness of the anti-reflection layer 130, or the thickness of the hard mask layer 120, and further control the depth-to-width ratio of the isolation trench. The depth-to-width ratio of the isolation trench can be 4:1 to 1:1, for example. Further, when the floating gate structure layer 110 and the substrate 100 are etched, the etching is controlled by using a method of stopping arrival time, the time for etching the floating gate structure layer 110 may be 23s to 25s, for example, 25s, the time for etching the substrate 100 may be 70s to 95s, and the morphology of the isolation trench 140 formed in the substrate 100 can be better controlled by using the method of stopping arrival time to control the etching, so that the angle α between the bottom wall and the side wall of the formed isolation trench is controlled.
As shown in fig. 6, after the isolation trench 140 is formed, the patterned photoresist layer, the hard mask layer 120 and the anti-reflection layer 130 are removed using an ashing process and/or a wet cleaning.
Next, as shown in fig. 7, step S3 is performed to fill the isolation trench 140 with an isolation layer 150 to form a shallow trench isolation structure. The isolation layer 150 includes a first oxide layer 151 and a second oxide layer 152, the first oxide layer 151 covers the sidewall and the bottom wall of the isolation trench 140 (i.e., the inner wall of the isolation trench 140), and the second oxide layer 152 covers the first isolation layer 150 and fills the isolation trench 140.
In this embodiment, the first oxide layer 151 is made of silicon dioxide, the first oxide layer 151 is formed by a furnace oxidation process, and the first oxide layer 151 can play a role of buffering stress, so as to further reduce the probability of dislocation defects of the substrate 100.
In this embodiment, the material of the second oxide layer 152 includes silicon dioxide, that is, the material of the second oxide layer 152 is the same as that of the first oxide layer 151. The isolation trench 140 may be filled with the second oxide layer 152, that is, the surface of the second oxide layer 152 is flush with the surface of the hard mask layer 120, that is, the surface of the second oxide layer 152 is higher than the surface of the floating gate structure layer 110, so that the surface of the subsequently formed shallow trench isolation structure may be higher than the surface of the floating gate structure layer 110, thereby increasing the isolation performance between the active region and the floating gate structure layer 110.
In this embodiment, the second oxide layer 152 may be formed by a high aspect ratio process or a high density plasma chemical vapor deposition process. If the second oxide layer 152 is formed by a high-density plasma chemical vapor deposition process, deposition (silane and oxygen reaction) and etching (argon and oxygen sputtering) processes can be performed simultaneously in the same reaction chamber to effectively fill the isolation trench 140 at a lower temperature. If the second oxide layer 152 is formed by a high aspect ratio process, the tetraethoxysilane and the ozone can be used as precursors to react, and a good filling capability can be obtained by adjusting the ratio of the tetraethoxysilane to the ozone and the slow increasing rate of the tetraethoxysilane, so that the second oxide layer 152 is better filled in the isolation trench 140, and the air gap of the second oxide layer 152 in the isolation trench is reduced.
Alternatively, before the isolation layer 150 is filled in the isolation trench 140, an annealing process may be performed on the substrate 100. The temperature range of the annealing treatment may be 800 ℃ to 1100 ℃ (for example, 800 ℃, 900 ℃, 1000 ℃, etc.), the annealing treatment is performed in an atmosphere of inert gas, and the inert gas may be one or more of nitrogen, argon, krypton, and xenon. Annealing the substrate 100 may relieve stress, i.e., stress in the substrate 100, thereby further reducing the probability of dislocations in the crystal lattice of the substrate 100.
In addition, after the second oxide layer 152 is formed, a planarization process may be performed on the second oxide layer 152, so that the surface of the second oxide layer 152 is a flat surface, thereby making the surface of the shallow trench isolation structure flat.
Based on the same inventive concept, the invention also provides a flash memory, which comprises a substrate 100; a floating gate structure layer 110 formed on the substrate 100; an isolation trench 140 penetrating through the floating gate structure layer 110 and extending into the substrate 100, wherein an angle α between a sidewall and a bottom wall of the isolation trench 140 is 98 ° to 102 °; and an isolation layer 150 filled in the shallow trench, wherein the isolation layer 150 and the isolation trench 140 form a shallow trench isolation structure. Because the angle alpha between the bottom wall and the side wall of the isolation trench 140 is 98-102 degrees, compared with the prior art, the contact surface between the subsequently formed shallow trench isolation structure and the substrate 100 can be increased, meanwhile, the effective supporting volume of the substrate 100 can be increased, the stress born in the unit volume is reduced, the lattice dislocation of the substrate 100 is reduced, the problem of dislocation defect in the flash memory is solved, and the leakage current in the flash memory is reduced.
In this embodiment, the flash memory may be a flash memory, for example.
In summary, in the flash memory and the manufacturing method thereof provided by the invention, the angle between the bottom wall and the side wall of the isolation trench formed in the substrate is 98-102 °, compared with the prior art, the contact surface between the subsequently formed shallow trench isolation structure and the substrate can be increased, meanwhile, the effective support volume of the substrate can be increased, the stress born in the unit volume can be reduced, the lattice dislocation of the substrate can be reduced, the problem of dislocation defect in the flash memory can be solved, and the leakage current in the flash memory can be reduced.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
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| CN115172256A (en) * | 2022-06-29 | 2022-10-11 | 上海华虹宏力半导体制造有限公司 | STI etching method for forming positive deviation CD value |
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