CN114203698A - Semiconductor structure and method for forming semiconductor structure - Google Patents
Semiconductor structure and method for forming semiconductor structure Download PDFInfo
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- CN114203698A CN114203698A CN202010988486.XA CN202010988486A CN114203698A CN 114203698 A CN114203698 A CN 114203698A CN 202010988486 A CN202010988486 A CN 202010988486A CN 114203698 A CN114203698 A CN 114203698A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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Abstract
A semiconductor structure, comprising: a substrate comprising first regions and second regions, the second regions being located between adjacent first regions; a first fin structure and a second fin structure on the substrate, the first fin structure spanning the second region, the second fin structure parallel to the first fin structure; the first anti-diffusion structure and the second anti-diffusion structure are located on the second area, part of the first anti-diffusion structure is located in the first fin portion structure, part of the second anti-diffusion structure is located in the second fin portion structure, and the first anti-diffusion structure is connected with at least two second anti-diffusion structures. The performance of the semiconductor structure is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the increase of the integration level of semiconductor devices, the critical dimensions of transistors are continuously shrinking. However, with the rapid decrease of the transistor size, the thickness of the gate dielectric layer and the operating voltage cannot be changed correspondingly, so that the difficulty of suppressing the short channel effect is increased, and the channel leakage current of the transistor is increased.
The gate of a Fin-Field-Effect Transistor (FinFET) is a fork-shaped 3D structure similar to a Fin. A fin part is formed by the protrusion of the channel of the FinFET out of the surface of the substrate, and the grid electrode covers the top surface and the side wall of the fin part, so that an inversion layer is formed on each side of the channel, and the connection and disconnection of circuits can be controlled on two sides of the fin part. The design can increase the control of the gate to the channel region, thereby well inhibiting the short-channel effect of the transistor. However, the short channel effect still exists in the fin field effect transistor.
In addition, in order to further reduce the influence of the short channel effect on the semiconductor device, the channel leakage current is reduced. The technical field of semiconductors introduces a strained silicon technology, and the method of the strained silicon technology comprises the following steps: forming grooves in the fin parts on two sides of the grid structure; and forming a source drain doped region in the groove by an epitaxial growth process.
In order to prevent the source-drain doped regions of different transistors from being connected with each other, an isolation layer needs to be formed in the fin portion, and meanwhile, in order to reduce the area of the isolation layer, the integration level of the formed semiconductor structure is improved. The prior art introduces sdb (single Diffusion break) and ddb (double Diffusion break) techniques.
However, the performance of the semiconductor structure formed by the existing method is poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising first regions and second regions, the second regions being located between adjacent first regions; a first fin structure and a second fin structure on the substrate, the first fin structure spanning the second region, the second fin structure parallel to the first fin structure; the first anti-diffusion structure and the second anti-diffusion structure are located on the second area, part of the first anti-diffusion structure is located in the first fin portion structure, part of the second anti-diffusion structure is located in the second fin portion structure, and the first anti-diffusion structure is connected with at least two second anti-diffusion structures.
Optionally, the method further includes: a third gate structure on the first region, the third gate structure spanning the first and second fin structures.
Optionally, the method further includes: the first source-drain doping regions are located in the first fin portion structures on two sides of the first diffusion preventing structure and the first fin portion structures on two sides of the third grid structure, and the second source-drain doping regions are located in the second fin portion structures on two sides of the second diffusion preventing structure and the second fin portion structures on two sides of the third grid structure.
Optionally, the material of the first diffusion prevention structure comprises silicon nitride; the material of the second anti-diffusion structure comprises silicon nitride.
Optionally, the first fin structure is used to form an NMOS device, and the second fin structure is used to form a PMOS device.
Correspondingly, the technical scheme of the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate comprising first regions and second regions, the second regions being located between adjacent first regions; forming a first fin structure and a second fin structure on the substrate, wherein the first fin structure crosses the second region, and the second fin structure is parallel to the first fin structure; forming a first grid structure, a second grid structure and a dielectric layer on the second area, wherein the dielectric layer is positioned on the side wall of the first grid structure and the side wall of the second grid structure, the first grid structure crosses over the first fin structure, the second grid structure crosses over the second fin structure, and one first grid structure is connected with at least two second grid structures; removing the first gate structure and the second gate structure, and forming a first opening in the dielectric layer on the second region, wherein part of the first fin structure and part of the second fin structure are exposed by the first opening; removing part of the first fin structure and part of the second fin structure exposed by the first opening, and forming a second opening in the first fin structure and the second fin structure on the second region; and forming a first anti-diffusion structure and a second anti-diffusion structure in the first opening and the second opening, wherein part of the first anti-diffusion structure is positioned in the first fin part structure, part of the second anti-diffusion structure is positioned in the second fin part structure, and the first anti-diffusion structure is connected with at least two second anti-diffusion structures.
Optionally, the method for forming the first opening includes: forming a mask layer on the substrate, wherein the mask layer exposes the surface of the second grid structure of the first grid structure on the second area; and etching the first gate structure and the second gate structure by taking the mask layer as a mask to form the first opening.
Optionally, the process for etching the first gate structure and the second gate structure includes one or more of a wet etching process and a dry etching process.
Optionally, the process of removing a portion of the first fin structure and a portion of the second fin structure exposed by the first opening includes a dry etching process.
Optionally, the method for forming the first gate structure and the second gate structure includes: forming a first dummy gate structure crossing the first fin structure and a second dummy gate structure crossing the second fin structure on the second region, wherein one first dummy gate structure is connected with at least two second dummy gate structures; forming a dielectric layer on the substrate, wherein the dielectric layer is positioned on the side wall of the first dummy gate structure and the side wall of the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure, and forming a third opening in the dielectric layer; and forming a first gate structure and a second gate structure in the third opening.
Optionally, before removing the first gate structure and the second gate structure, the method further includes: and forming a third gate structure on the first region, wherein the third gate structure spans the first fin structure and the second fin structure.
Optionally, before removing the first gate structure and the second gate structure, the method further includes: and forming a first source drain doping region and a second source drain doping region, wherein the first source drain doping region is positioned in the first fin part structures at two sides of the first grid structure and the first fin part structures at two sides of the third grid structure, and the second source drain doping region is positioned in the second fin part structures at two sides of the second grid structure and the second fin part structures at two sides of the third grid structure.
Optionally, the third gate structure is formed simultaneously with the first gate structure and the second gate structure.
Optionally, the material of the first diffusion prevention structure comprises a dielectric material, and the dielectric material comprises silicon nitride; the material of the second anti-diffusion structure comprises a dielectric material, and the dielectric material comprises silicon nitride.
Optionally, the method for forming the first diffusion preventing structure and the second diffusion preventing structure includes: forming a diffusion-proof material layer in the first opening, the second opening and on the dielectric layer; and flattening the anti-diffusion material layer until the surface of the medium layer is exposed to form the first anti-diffusion structure and the second anti-diffusion structure.
Optionally, the process of forming the diffusion-preventing material layer includes an atomic layer deposition process.
Optionally, the first fin structure is used to form an NMOS device, and the second fin structure is used to form a PMOS device.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the semiconductor structure in the technical scheme, the first anti-diffusion structure is connected with at least two second anti-diffusion structures, the damage of the process for forming the first anti-diffusion structure to the first fin portion structure is small, the anti-diffusion effect of the first anti-diffusion structure to the first fin portion structure is good, and therefore the performance of the semiconductor structure is improved.
The method for forming the semiconductor structure comprises the steps of forming a first fin structure and a second fin structure which cross over the second region, forming a first grid structure which crosses over the first fin structure on the second region, and forming a second gate structure on the second region and crossing the second fin structure, the first gate structure being connected to at least two second gate structures, then removing the first gate structure and the second gate structure to form a first opening in the dielectric layer, removing part of the first fin structure and part of the second fin structure exposed by the first opening, and forming a second opening in the first fin part structure and the second fin part structure, and finally forming a first anti-diffusion structure and a second anti-diffusion structure in the first opening and the second opening, wherein the first anti-diffusion structure is connected with at least two second anti-diffusion structures. According to the method, a first grid structure and a second grid structure are formed firstly, the formed first grid structure is connected with at least two second grid structures, and then in the process of forming a first anti-diffusion structure, the first grid structure is removed and then part of the first fin part structure is removed, so that the formed first fin part structure meets the design requirement, the damage of the process for removing the first grid structure to the first fin part structure is small, the formed first anti-diffusion structure has a good anti-diffusion effect on the first fin part structure, and the performance of the semiconductor structure is improved.
Drawings
FIGS. 1-3 are cross-sectional views illustrating a semiconductor structure forming process according to an embodiment;
fig. 4 to 12 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of semiconductor structures formed by existing methods is poor. The analysis will now be described with reference to specific examples.
Fig. 1 to 3 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes first regions I and second regions II located between the first regions I; forming a first fin structure 101 on a substrate, wherein the first fin structure 101 spans the first region I and the second region II, and forming a plurality of discrete second fin structures 102 on the first region I of the substrate, wherein the second fin structures 102 are parallel to the first fin structure 101; forming a plurality of gate structures 103, first source-drain doped regions 104 located in the first fin structures 101 on two sides of the gate structures 103, second source-drain doped regions 105 located in the second fin structures 102 on two sides of the gate structures 103, and a dielectric layer 106 (shown in fig. 3) located on the side walls of the gate structures 103, wherein the gate structures 103 are located on the substrate, and the gate structures 103 cross the first fin structures 101 and the second fin structures 102.
Referring to fig. 2 and fig. 3, fig. 3 is a schematic cross-sectional view taken along a section line AA1 in fig. 2, fig. 2 is a top view of fig. 3, the gate structure 103 on the second region II is removed, and a first opening (not shown) is formed in the dielectric layer 106, the first opening exposing a portion of the first fin structure 101 and a portion of one end of the second fin structure 102 adjacent to the second region II; removing the first fin structure 101 and the second fin structure 102 exposed by the first opening until the surface of the substrate 100 is exposed, and forming a second opening (not shown) in the dielectric layer 106; an anti-diffusion structure 107 is formed within the second opening.
In the forming process of the semiconductor structure, because the second fin structure 102 is located on the first region I, one end of the second fin structure 102 is located at a position where the second region II is connected with the first region I, and the gate structure 103 on the second region II is also located on the second fin structure 102, the sidewall of the formed first opening exposes the surface of the second fin structure 102. When the first opening is formed, the gate structure 103 on the second region II is usually removed by using a wet etching process, so that the wet etching process is likely to damage the second source/drain doped region 105 in the second fin structure 102 (as shown in a region C in fig. 3) from the surface of the second fin structure 102 exposed from the sidewall of the first opening, and even damage the gate structure 103 on the first region I adjacent to the second region II, thereby affecting the performance of the formed semiconductor structure. Furthermore, when the first fin structure 101 and the second fin structure 102 exposed by the first opening are removed, a SiCoNi process is required to remove a natural oxide layer on the surfaces of the first fin structure 101 and the second fin structure 102, and since the first opening exposes the sidewall of the second fin structure 102, the SiCoNi process is likely to damage the second source/drain doped region 105 and the gate structure 103 from the sidewall of the second fin structure 102 along the extending direction of the second fin structure 102, thereby affecting the performance of the formed semiconductor structure.
In order to solve the above problems, a technical solution of the present invention provides a semiconductor structure and a method for forming the semiconductor structure, in which a first gate structure and a second gate structure are formed first, and the formed first gate structure is connected to at least two second gate structures, and then, in a process of forming a first anti-diffusion structure, a portion of the first fin structure is removed after the first gate structure is removed, so that the formed first fin structure meets design requirements, and thus, the process for removing the first gate structure has less damage to the first fin structure, and the formed first anti-diffusion structure has a better anti-diffusion effect on the first fin structure, thereby improving performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 12 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, where the substrate 200 includes a first region I and a second region II, and the second region II is located between adjacent first regions I.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
With continued reference to fig. 4, a first fin structure 201 and a second fin structure 202 are formed on the substrate 200, the first fin structure 201 crossing the second region II, and the second fin structure 202 being parallel to the first fin structure 201.
The first fin structure 201 is used to form an NMOS device and the second fin structure 202 is used to form a PMOS device.
In this embodiment, the material of the first fin structure and the second fin structure includes silicon.
In other embodiments, the material of the first fin structure 201 and the second fin structure 202 includes silicon carbide, silicon germanium, and a multi-element semiconductor material made of iii-v elements.
In this embodiment, the method further includes: an isolation layer (not shown) is formed on the substrate 200, wherein the isolation layer is located on partial sidewalls of the first fin structure 201 and the second fin structure 202, and a top surface of the isolation layer is lower than top surfaces of the first fin structure 201 and the second fin structure 202.
The material of the isolation layer comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the isolation layer includes silicon oxide.
Referring to fig. 5 and fig. 6, fig. 5 is a top view of fig. 6 without the dielectric layer 205, fig. 6 is a schematic cross-sectional view of fig. 5 along a section line BB1, a first gate structure 203, a second gate structure 204 and a dielectric layer 205 are formed on the second region II, the dielectric layer 205 is located on a sidewall of the first gate structure 203 and a sidewall of the second gate structure 204, the first gate structure 203 crosses the first fin structure 201, the second gate structure 204 crosses the second fin structure 202, and one of the first gate structures 203 is connected to at least two of the second gate structures 204.
In this embodiment, the method further includes: a third gate structure 206 is formed on the first region I, and the third gate structure 206 spans the first fin structure 201 and the second fin structure 202.
The third gate structure 206 is formed simultaneously with the first gate structure 203 and the second gate structure 204.
Please refer to fig. 5 and fig. 6, further comprising: forming a first source-drain doped region 207 and a second source-drain doped region 208, wherein the first source-drain doped region 207 is located in the first fin structures 201 on two sides of the first gate structure 203 and the first fin structures 201 on two sides of the third gate structure 206, and the second source-drain doped region 208 is located in the second fin structures 202 on two sides of the second gate structure 204 and the second fin structures 202 on two sides of the third gate structure 206.
The forming method of the first gate structure 203, the second gate structure 204, the third gate structure 206, the first source-drain doped region 207, the second source-drain doped region 208 and the dielectric layer 205 includes: forming first dummy gate structures (not shown) crossing the first fin structures 201, second dummy gate structures (not shown) crossing the second fin structures 202 on the second region II, and third dummy gate structures (not shown) crossing the first fin structures 201 and the second fin structures 202 on the first region I, wherein one first dummy gate structure is connected with at least two second dummy gate structures; forming first source-drain doped regions 207 in the first fin structures 201 on two sides of the first gate structure 203 and the first fin structures 201 on two sides of the third gate structure 206; forming second source-drain doped regions 208 in the second fin structures 202 on two sides of the second gate structure 204 and in the second fin structures 202 on two sides of the third gate structure 206; forming a dielectric layer 205 on the substrate 200, where the dielectric layer 205 is located on the sidewall of the first dummy gate structure, the sidewall of the second dummy gate structure, and the sidewall of the third dummy gate structure, and the dielectric layer 205 is located on the first source-drain doped region 207 and the second source-drain doped region 208; removing the first dummy gate structure, the second dummy gate structure and the third dummy gate structure, and forming a third opening (not shown) in the dielectric layer 205; a first gate structure 203, a second gate structure 204, and a third gate structure 206 are formed within the third opening.
The first, second and third dummy gate structures include a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) on the dummy gate dielectric layer. The material of the pseudo gate dielectric layer comprises silicon oxide or low-K (K is less than 3.9) material; the material of the dummy gate layer comprises polysilicon.
The first gate structure 203, the second gate structure 204, and the third gate structure 206 include: a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer. In this embodiment, the first gate structure 203, the second gate structure 204, and the third gate structure 206 further include a work function layer (not shown), and the work function layer is located between the gate dielectric layer and the gate layer.
The gate dielectric layer comprises a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material comprises aluminum oxide or hafnium oxide; the material of the gate layer comprises a metal, and the metal comprises tungsten; the material of the work function layer comprises an N-type work function material or a P-type work function material, the N-type work function material comprises titanium aluminum, and the P-type work function material comprises titanium nitride or tantalum nitride.
Doped ions are arranged in the first source-drain doped region 207 and the second source-drain doped region 208, and the type of the doped ions is N type or P type; the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.
In this embodiment, the first source-drain doped region 207 has N-type ions therein, and the material of the first source-drain doped region 207 includes carbon silicon; the second source-drain doped region 208 has P-type ions therein, and the material of the second source-drain doped region 208 includes silicon germanium.
The material of the dielectric layer 205 comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the dielectric layer 205 includes silicon oxide.
Referring to fig. 7 and 8, fig. 7 is a top view of fig. 8, and fig. 8 is a schematic cross-sectional view of fig. 7 along a sectional line CC1, the first gate structure 203 and the second gate structure 204 are removed, a first opening 209 is formed in the dielectric layer 205 on the second region, and a portion of the first fin structure 201 and a portion of the second fin structure 202 are exposed by the first opening 209.
The method of forming the first opening 209 includes: forming a mask layer (not shown) on the substrate 200, wherein the mask layer exposes the surfaces of the first gate structures 203 and the second gate structures 204 on the second region II; and etching the first gate structure 203 and the second gate structure 204 by using the mask layer as a mask to form the first opening 209.
The process for etching the first gate structure 203 and the second gate structure 204 includes one or more of a wet etching process and a dry etching process.
In this embodiment, the process for etching the first gate structure 203 and the second gate structure 204 includes a wet etching process, and an etching solution of the wet etching process includes a phosphoric acid solution or a sulfuric acid solution.
Referring to fig. 9 and 10, fig. 9 is a top view of fig. 10, and fig. 10 is a cross-sectional view of fig. 9 taken along a sectional line DD1, wherein a portion of the first fin structure 201 and a portion of the second fin structure 202 exposed by the first opening 209 are removed, and a second opening 210 is formed in the first fin structure 201 and the second fin structure 202 in the second region II.
The process of removing the portion of the first fin structure 201 and the portion of the second fin structure 202 exposed by the first opening 209 includes a dry etching process.
The gas of the dry etching process comprises the following steps: chlorine, hydrogen bromide or sulfur hexafluoride, oxygen, and a mixture of argon or helium.
Referring to fig. 11 and 12, fig. 11 is a top view of fig. 12, fig. 12 is a schematic cross-sectional structure view of fig. 11 along a sectional line EE1, a first anti-diffusion structure 211 and a second anti-diffusion structure 212 are formed in the first opening 209 and the second opening 210, a portion of the first anti-diffusion structure 211 is located in the first fin structure 201, a portion of the second anti-diffusion structure 212 is located in the second fin structure 202, and the first anti-diffusion structure 211 is connected to at least two second anti-diffusion structures 212.
The material of the first diffusion prevention structure 211 comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride in combination; the material of the second diffusion prevention structure 212 includes a dielectric material including one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the material of the first diffusion preventing structure 211 includes silicon nitride; the material of the second anti-diffusion structure 212 includes silicon nitride. The silicon nitride material has a compact structure, and can effectively block ion diffusion in the first fin structure 201 and the second fin structure 202.
The method for forming the first and second diffusion prevention structures 211 and 212 includes: forming a diffusion-preventing material layer (not shown) in the first opening 209, in the second opening 210 and on the dielectric layer 205; and flattening the diffusion-proof material layer until the surface of the dielectric layer 205 is exposed to form the first diffusion-proof structure 211 and the second diffusion-proof structure 212.
The process for forming the diffusion-preventing material layer includes an atomic layer deposition process or a chemical vapor deposition process. In this embodiment, the process of forming the diffusion-prevention material layer includes an atomic layer deposition process, and the atomic layer deposition process can form a first diffusion-prevention structure 211 and a second diffusion-prevention structure 212 with dense structures in the first opening 209 and the second opening 210, so that the first diffusion-prevention structure 211 and the second diffusion-prevention structure 212 have a better diffusion-prevention effect.
According to the semiconductor structure formed by the method, the first gate structure 203 and the second gate structure 204 are formed firstly, and the formed first gate structure 203 is connected with at least two second gate structures 204, so that in the process of forming the first diffusion prevention structure 211, the first gate structure 203 is removed, and then part of the first fin portion structure 201 is removed, so that the formed first fin portion structure 201 meets the design requirement, the damage of the process for removing the first gate structure 203 to the first fin portion structure 201 is small, the diffusion prevention effect of the formed first diffusion prevention structure 211 to the first fin portion structure 201 is good, and the performance of the semiconductor structure is improved.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please refer to fig. 11 and 12, which includes:
a substrate 200, the substrate 200 comprising a first region I and a second region II, the second region II being located between adjacent first regions I;
a first fin structure 201 and a second fin structure 202 on the substrate 200, the first fin structure 201 crossing the second region II, the second fin structure 202 being parallel to the first fin structure 201;
the first diffusion preventing structure 211 and the second diffusion preventing structure 212 are located on the second region II, a part of the first diffusion preventing structure 211 is located in the first fin structure 201, a part of the second diffusion preventing structure 212 is located in the second fin structure 202, and the first diffusion preventing structure 211 is connected with at least two second diffusion preventing structures 212.
In this embodiment, the method further includes: a third gate structure 206 located on the first region I, the third gate structure 206 spanning the first fin structure 201 and the second fin structure 202.
In this embodiment, the method further includes: the first source-drain doping region 207 is located in the first fin structures 201 on two sides of the first diffusion-preventing structure 211 and in the first fin structures 201 on two sides of the third gate structure 206, and the second source-drain doping region 208 is located in the second fin structures 202 on two sides of the second diffusion-preventing structure 212 and in the second fin structures 202 on two sides of the third gate structure 206.
In this embodiment, the material of the first diffusion preventing structure 211 includes silicon nitride; the material of the second anti-diffusion structure 212 includes silicon nitride.
In this embodiment, the first fin structure 201 is used to form an NMOS device, and the second fin structure 202 is used to form a PMOS device.
In the semiconductor structure, the first anti-diffusion structure 211 is at least connected with the two second anti-diffusion structures 212, the damage of the process for forming the first anti-diffusion structure 211 to the first fin portion structure 201 is small, and the anti-diffusion effect of the first anti-diffusion structure 211 to the first fin portion structure 201 is good, so that the performance of the semiconductor structure is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A semiconductor structure, comprising:
a substrate comprising first regions and second regions, the second regions being located between adjacent first regions;
a first fin structure and a second fin structure on the substrate, the first fin structure spanning the second region, the second fin structure parallel to the first fin structure;
the first anti-diffusion structure and the second anti-diffusion structure are located on the second area, part of the first anti-diffusion structure is located in the first fin portion structure, part of the second anti-diffusion structure is located in the second fin portion structure, and the first anti-diffusion structure is connected with at least two second anti-diffusion structures.
2. The semiconductor structure of claim 1, further comprising: a third gate structure on the first region, the third gate structure spanning the first and second fin structures.
3. The semiconductor structure of claim 2, further comprising: the first source-drain doping regions are located in the first fin portion structures on two sides of the first diffusion preventing structure and the first fin portion structures on two sides of the third grid structure, and the second source-drain doping regions are located in the second fin portion structures on two sides of the second diffusion preventing structure and the second fin portion structures on two sides of the third grid structure.
4. The semiconductor structure of claim 1, wherein the material of the first diffusion prevention structure comprises silicon nitride; the material of the second anti-diffusion structure comprises silicon nitride.
5. The semiconductor structure of claim 1, wherein the first fin structure is used to form an NMOS device and the second fin structure is used to form a PMOS device.
6. A method of forming a semiconductor structure, comprising:
providing a substrate comprising first regions and second regions, the second regions being located between adjacent first regions;
forming a first fin structure and a second fin structure on the substrate, wherein the first fin structure crosses the second region, and the second fin structure is parallel to the first fin structure;
forming a first grid structure, a second grid structure and a dielectric layer on the second area, wherein the dielectric layer is positioned on the side wall of the first grid structure and the side wall of the second grid structure, the first grid structure crosses over the first fin structure, the second grid structure crosses over the second fin structure, and one first grid structure is connected with at least two second grid structures;
removing the first gate structure and the second gate structure, and forming a first opening in the dielectric layer on the second region, wherein part of the first fin structure and part of the second fin structure are exposed by the first opening;
removing part of the first fin structure and part of the second fin structure exposed by the first opening, and forming a second opening in the first fin structure and the second fin structure on the second region;
and forming a first anti-diffusion structure and a second anti-diffusion structure in the first opening and the second opening, wherein part of the first anti-diffusion structure is positioned in the first fin part structure, part of the second anti-diffusion structure is positioned in the second fin part structure, and the first anti-diffusion structure is connected with at least two second anti-diffusion structures.
7. The method of forming a semiconductor structure of claim 6, wherein the method of forming the first opening comprises: forming a mask layer on the substrate, wherein the mask layer exposes the surface of the second grid structure of the first grid structure on the second area; and etching the first gate structure and the second gate structure by taking the mask layer as a mask to form the first opening.
8. The method of claim 7, wherein the process of etching the first gate structure and the second gate structure comprises a combination of one or more of a wet etch process and a dry etch process.
9. The method of claim 6, wherein the removing the portion of the first fin structure and the portion of the second fin structure exposed by the first opening comprises a dry etching process.
10. The method of forming a semiconductor structure of claim 6, wherein the method of forming the first and second gate structures comprises: forming a first dummy gate structure crossing the first fin structure and a second dummy gate structure crossing the second fin structure on the second region, wherein one first dummy gate structure is connected with at least two second dummy gate structures; forming a dielectric layer on the substrate, wherein the dielectric layer is positioned on the side wall of the first dummy gate structure and the side wall of the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure, and forming a third opening in the dielectric layer; and forming a first gate structure and a second gate structure in the third opening.
11. The method of forming a semiconductor structure of claim 6, wherein removing the first and second gate structures further comprises: and forming a third gate structure on the first region, wherein the third gate structure spans the first fin structure and the second fin structure.
12. The method of forming a semiconductor structure of claim 11, wherein removing the first and second gate structures further comprises: and forming a first source drain doping region and a second source drain doping region, wherein the first source drain doping region is positioned in the first fin part structures at two sides of the first grid structure and the first fin part structures at two sides of the third grid structure, and the second source drain doping region is positioned in the second fin part structures at two sides of the second grid structure and the second fin part structures at two sides of the third grid structure.
13. The method of forming a semiconductor structure of claim 11, wherein the third gate structure is formed simultaneously with the first gate structure and the second gate structure.
14. The method of forming a semiconductor structure of claim 6, wherein the material of the first diffusion prevention structure comprises a dielectric material comprising silicon nitride; the material of the second anti-diffusion structure comprises a dielectric material, and the dielectric material comprises silicon nitride.
15. The method of forming a semiconductor structure of claim 6, wherein the method of forming the first and second anti-diffusion structures comprises: forming a diffusion-proof material layer in the first opening, the second opening and on the dielectric layer; and flattening the anti-diffusion material layer until the surface of the medium layer is exposed to form the first anti-diffusion structure and the second anti-diffusion structure.
16. The method of forming a semiconductor structure of claim 15, wherein the process of forming the diffusion-prevention material layer comprises an atomic layer deposition process.
17. The method of claim 6, wherein the first fin structure is used to form an NMOS device and the second fin structure is used to form a PMOS device.
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