CN114203569A - High-broadband memory packaging method and packaging structure - Google Patents
High-broadband memory packaging method and packaging structure Download PDFInfo
- Publication number
- CN114203569A CN114203569A CN202111496879.XA CN202111496879A CN114203569A CN 114203569 A CN114203569 A CN 114203569A CN 202111496879 A CN202111496879 A CN 202111496879A CN 114203569 A CN114203569 A CN 114203569A
- Authority
- CN
- China
- Prior art keywords
- memory
- memory chip
- chip
- layer
- packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H10W90/00—
-
- H10W20/20—
-
- H10W40/226—
-
- H10W40/228—
-
- H10W74/117—
-
- H10W72/07232—
Landscapes
- Semiconductor Memories (AREA)
Abstract
本发明提供一种高宽带存储器封装方法及封装结构，该方法包括：在第一存储器芯片内预设位置处形成多个切割痕；在相邻两个所述切割痕之间将多个第二存储器芯片依次混合键合堆叠设置在第一存储器芯片上；形成第一塑封层；将塑封完成的第一存储器芯片贴在贴片膜上，在对应多个切割痕的位置处切割第一塑封层，形成多个独立的第二存储器芯片组；沿多个切割痕，对第一存储器芯片进行切割，形成多个独立存储器堆叠模块；将多个存储器堆叠模块与缓冲芯片进行热压键合；形成第二塑封层；对第二塑封层和缓冲芯片进行切割，形成独立存储器封装结构。本发明的高宽带存储器封装方法，可实现超细间距互连，增加垂直互连的数量，可提高数据吞吐量，增加容量。
The present invention provides a high-bandwidth memory packaging method and packaging structure. The method includes: forming a plurality of cutting marks at preset positions in a first memory chip; placing a plurality of second cutting marks between two adjacent cutting marks The memory chips are sequentially mixed and bonded and stacked on the first memory chip; a first plastic sealing layer is formed; the first memory chip after plastic sealing is pasted on the patch film, and the first plastic sealing layer is cut at the positions corresponding to the plurality of cutting marks , forming a plurality of independent second memory chip groups; cutting the first memory chip along a plurality of cutting marks to form a plurality of independent memory stacking modules; thermally bonding the plurality of memory stacking modules and the buffer chips; forming The second plastic packaging layer; the second plastic packaging layer and the buffer chip are cut to form an independent memory packaging structure. The high-bandwidth memory packaging method of the present invention can realize ultra-fine pitch interconnection, increase the number of vertical interconnections, improve data throughput, and increase capacity.
Description
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a packaging method and a packaging structure of a high-bandwidth memory.
Background
For enterprise-level applications such as data centers, high-speed storage of large volumes becomes an essential item. To meet this demand, a High Bandwidth Memory (HBM) has come to be used. As shown in fig. 1, the HBM vertically interconnects a plurality of memory chips 11 using Through Silicon Vias (TSVs) 12, and performs data interaction with the outside Through a buffer chip 10 on a bottom layer.
Currently, the HBM multi-layer chip multi-stack employs a Thermal Compression Bonding (TCB) process to connect the microbumps 14 with the chip back pads 13 and the chip back pads 13 with the through-silicon vias 12 of the chip by rapid heating. At present, the composition of the microbumps 14 is mainly a copper-tin structure, and the main composition of the chip back pads 13 is a nickel-gold structure. The final stacked structure is protected by a molding layer 15.
In the case of using copper-tin micro-bumps, the pitch between the micro-bumps and the height of the tin need to be strictly controlled in order to prevent short-circuiting between the micro-bumps due to the deformability of the tin during reflow. At present, the distance is more than 40um, and when the distance is reduced to be less than 25um, the tin is excessively small, so that the tin is comprehensively converted into intermetallic compounds under the condition of hot load, and the reliability is failed.
In order to increase the memory capacity and data throughput speed, the number of chip stacks and the number of pins need to be increased, but in the current micro-bump mechanism, the space for continuous improvement is limited due to the limitation of bump height and space.
In view of the above problems, there is a need for a method and a structure for packaging a high bandwidth memory, which are reasonable in design and can effectively solve the above problems.
Disclosure of Invention
The present invention is directed to at least one of the technical problems of the prior art, and provides a method and a structure for packaging a high bandwidth memory.
One aspect of the invention provides a high-bandwidth memory packaging method, comprising:
forming a plurality of cutting marks at preset positions in the first memory chip;
sequentially mixing, bonding and stacking a plurality of second memory chips with first conductive through holes on the first memory chip between two adjacent cutting marks;
plastically packaging the first memory chip and the plurality of second memory chips to form a first plastic packaging layer;
adhering the first memory chip subjected to plastic packaging to a film, and cutting the first plastic packaging layer at positions corresponding to the plurality of cutting marks to form a plurality of independent second memory chip groups;
cutting the first memory chip along the plurality of cutting marks to form a plurality of independent memory stacking modules;
carrying out hot-press bonding on the plurality of memory stacking modules and a buffer chip, wherein the buffer chip is provided with a second conductive through hole;
plastically packaging the buffer chip and the memory stacking module to form a second plastic packaging layer;
and cutting the second plastic packaging layer and the buffer chip to form an independent memory packaging structure.
Optionally, a first passivation layer and a first metal pad are disposed on a surface of the second memory chip facing the first memory chip, a second passivation layer and a second metal pad are disposed on a surface of the second memory chip facing away from the first memory chip, and a third passivation layer and a third metal pad are disposed on a surface of the first memory chip facing the second memory chip;
the sequentially hybrid bonding and stacking a plurality of second memory chips having conductive vias on the first memory chip comprises:
bonding the first passivation layer of the second memory chip at the bottom layer with the third passivation layer of the first memory chip, and bonding the first metal pad on the second memory chip at the bottom layer with the third metal pad on the first memory chip;
sequentially and mixedly bonding and stacking the rest layers of second memory chips on the bottom layer of second memory chips, wherein the first passivation layer and the second passivation layer in every two adjacent layers of second memory chips are bonded; and the first metal bonding pad and the second metal bonding pad in every two adjacent layers of the second memory chips are bonded.
Optionally, before the plastically packaged first memory chip is attached to a die attach film, the method further includes:
forming a first bump on the surface of the second memory chip on the top layer and the surface of the first plastic packaging layer, which is far away from the first memory chip, wherein the first bump corresponds to the second conductive through hole;
and forming a non-conductive adhesive film on the first salient points.
Optionally, before forming the first bump, the method further includes:
forming a dielectric layer on the surface, away from the first memory chip, of the second memory chip and the first plastic packaging layer on the top layer;
and forming a rewiring layer on the dielectric layer.
Optionally, a fourth passivation layer and a fourth metal pad are disposed on a surface of the buffer chip facing the memory stack module;
the thermocompression bonding the plurality of memory stack modules and the buffer chip includes:
and carrying out hot-pressing bonding on the first salient point and the fourth metal pad.
Optionally, the forming a plurality of cutting marks at preset positions in the first memory chip includes:
and forming a plurality of cutting marks in the preset position of the first memory chip by a laser invisible cutting method.
Optionally, the cutting the first memory chip to form a plurality of independent memory stack modules includes:
and stretching the film under a preset low-temperature condition to enlarge a plurality of cutting marks in the first memory chip so as to form a plurality of independent memory stacking modules.
Optionally, before the second molding compound layer and the buffer chip are cut, the method further includes:
and forming a second bump on the surface of the buffer chip departing from the memory stacking module, wherein the second bump corresponds to the second conductive through hole.
Optionally, the first conductive through hole and the second conductive through hole are all silicon through holes.
Another aspect of the present invention provides a high-bandwidth memory package structure, which is packaged by the aforementioned high-bandwidth memory packaging method.
According to the packaging method and the packaging structure of the high-broadband memory, the second memory chips with the first conductive through holes are sequentially mixed, bonded and stacked on the first memory chip in a stacking mode, interconnection with ultrafine intervals can be achieved, the number of vertical interconnections is increased, the number of data channels is increased, data throughput can be improved, and meanwhile due to the fact that the second memory chips and the first memory chip and the second memory chip are mixed and bonded, bonding height is reduced, the number of layers of the memory chips can be increased, and capacity is increased.
Drawings
FIG. 1 is a diagram of a prior art high bandwidth memory package;
FIG. 2 is a flow chart illustrating a method for packaging a high-bandwidth memory according to another embodiment of the present invention;
fig. 3 to 15 are schematic views illustrating a packaging process of a high bandwidth memory packaging method according to another embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 2, an aspect of the present invention provides a high-bandwidth memory packaging method S100, where the packaging method S100 includes:
s110, forming a plurality of cutting marks at predetermined positions in the first memory chip.
Specifically, as shown in fig. 3, in the present embodiment, a plurality of scribe lines 111 are formed in predetermined positions of the first memory chip 110 by a laser stealth dicing method. The scribe line 111 is also a laser damage layer in the first memory chip 110. As shown in fig. 3 and 4, in the present embodiment, laser stealth dicing is performed on the surface of the first memory chip 110 facing away from the second memory chip 120. Adopt the stealthy cutting method of laser can avoid the piece that produces when the blade cutting on the one hand, on the other hand, when using stealthy cutting, the tool mark width is almost zero, can reduce the width of cutting way, further reduces the interval between the first memory chip.
And S120, sequentially mixing, bonding and stacking a plurality of second memory chips with first conductive through holes on the first memory chip between two adjacent cutting marks.
Specifically, as shown in fig. 3 and 4, between two adjacent dicing cuts 111, a plurality of second memory chips 120 having first conductive vias 121 are sequentially hybrid-bonded and stacked on the first memory chip 110.
Illustratively, as shown in fig. 4, the second memory chip 120 is provided with a plurality of first conductive vias 121, and the first conductive vias 121 may be further optimized as through-silicon vias, and vertical electrical interconnection of the through-silicon vias is achieved by using a through-silicon via technology, so that the package height is reduced.
As shown in fig. 4, a surface of the second memory chip 120 facing the first memory chip 110 is provided with a first passivation layer 122 and a first metal pad 123, a surface of the second memory chip 120 facing away from the first memory chip 110 is provided with a second passivation layer 124 and a second metal pad 125, and a surface of the first memory chip 110 facing the second memory chip 120 is provided with a third passivation layer 112 and a third metal pad 113.
It should be noted that in this embodiment, the materials of the first passivation layer 122, the second passivation layer 124 and the third passivation layer 112 may be silicon dioxide materials, and the first metal pad 123, the second metal pad 125 and the third metal pad 113 may be copper pads. In this embodiment, the first memory chip 110 and the second memory chip 120 may be dynamic random access memory chips, or may be other memory chips, and this embodiment is not particularly limited.
The sequentially hybrid bonding and stacking a plurality of second memory chips having conductive vias on the first memory chip comprises:
first, as shown in fig. 4, between two adjacent scribe lines 111, that is, along two sides of the two adjacent scribe lines 111, the first passivation layer 122 of the bottom second memory chip is bonded to the third passivation layer 112 of the first memory chip 110, and then baking is performed at a temperature of 200 ℃ or higher, so that the first metal pad 123 on the bottom second memory chip 120 is bonded to the third metal pad 113 on the first memory chip 110, that is, the first copper pad on the bottom second memory chip 120 and the third copper pad on the first memory chip 110 are thermally expanded by copper to form a bond.
Next, as shown in fig. 5, the remaining layers of second memory chips 120 are sequentially mixed, bonded and stacked on the bottom layer of second memory chips 120, wherein the first passivation layer 122 and the second passivation layer 124 in every two adjacent layers of second memory chips 120 are bonded; and, the first metal pads 123 and the second metal pads 125 in every two adjacent layers of the second memory chips 120 are bonded.
That is, as shown in fig. 5, on both sides of the plurality of cutting traces 111, the bottom layer second memory chip 120 is hybrid-bonded to the first memory chip 110, the second layer second memory chip 120 is disposed on the bottom layer second memory chip 120 and hybrid-bonded to the bottom layer second memory chip 120, the third layer second memory chip 120 is disposed on the second layer second memory chip 120 and hybrid-bonded to the second layer second memory chip 120, and so on, the remaining layers of second memory chips 120 are sequentially hybrid-bonded and stacked on the bottom layer second memory chip 120.
S130, carrying out plastic package on the first memory chip and the plurality of second memory chips to form a first plastic package layer.
Specifically, as shown in fig. 6, the first memory chip 110 and the plurality of second memory chips 120 stacked on the first memory chip 110 are molded to form a first molding layer 140. The first molding layer 140 wraps the first memory chip 110 and the plurality of second memory chips 120 stacked on the first memory chip 110. Then, the surface of the first molding layer 140 is polished to expose the second passivation layer 124 and the second metal pad 125 of the surface of the second memory chip 120 facing away from the first memory chip 110. The plastic packaging method may be vacuum lamination of the film layer or a conventional plastic packaging process, and this embodiment is not particularly limited.
S140, the first memory chip after plastic packaging is attached to a film, and the first plastic packaging layer is cut at the position corresponding to the cutting marks to form a plurality of independent second memory chip groups.
For example, before the first memory chip subjected to plastic molding is attached to a die attach film, in this embodiment, the method further includes:
and forming a first bump on the surface of the second memory chip on the top layer and the surface of the first plastic packaging layer departing from the first memory chip, wherein the first bump is electrically connected with the second conductive through hole.
Further preferably, before the first bump is formed, a dielectric layer is first formed on the surface of the second memory chip and the first molding layer on the top layer, which face away from the first memory chip.
Specifically, as shown in fig. 7, a dielectric layer 170 is coated on the top surfaces of the second memory chip and the first molding layer 140, which are away from the first memory chip 110, the material of the dielectric layer 170 may be Polyimide (PI), Polybenzoxazole (PBO), or the like, the coating method is usually wafer spin coating, and the embodiment is not limited in particular.
Next, a rewiring layer is formed on the dielectric layer. Specifically, as shown in fig. 7, the dielectric layer 170 is patterned by a photolithography process to form a plurality of first openings (not shown), and a redistribution layer 180 is deposited at the plurality of first openings, the deposition method is sputtering, electroplating, and the like, the material of the redistribution layer 180 is usually titanium and copper, and the deposition method and the metal material are not particularly limited in this embodiment. The redistribution layer 180 is formed on the dielectric layer 170, so that high-density interconnection requirements can be well met, and the yield is improved.
And thirdly, forming a first bump on the rewiring layer, wherein the first bump corresponds to the second conductive through hole. Specifically, as shown in fig. 7, the redistribution layer 180 is patterned by using a photolithography process, a plurality of second openings (not labeled) are formed on the redistribution layer 180, and a plurality of first bumps 190 are formed at the plurality of second openings. The plurality of first bumps 190 are electrically connected to the plurality of second conductive vias 131 on the buffer chip 130. In this embodiment, the first bump 190 may be a copper-tin bump.
In this embodiment, since the first memory chip 110 is thick, after the plurality of first bumps 190 are formed, as shown in fig. 8, the side of the first memory chip 110 away from the second memory chip 120 needs to be thinned.
And finally, forming a non-conductive adhesive film on the first salient points. Specifically, as shown in fig. 9, after thinning the side of the first memory chip 110 away from the second memory chip 120, a non-conductive adhesive film 200 is formed on the plurality of first bumps 190, and the non-conductive adhesive film 200 wraps the plurality of first bumps 190 to protect the plurality of first bumps 190.
It should be noted that, in step S140, it is optional to sequentially form the dielectric layer 170 and the redistribution layer 180 on the surfaces of the top second memory chip and the first plastic package layer 140 away from the first memory chip 110, or directly form a plurality of first bumps 190 on the surfaces of the top second memory chip and the first plastic package layer 140 away from the first memory chip 110, which is not specifically limited in this embodiment.
After the above steps are completed, as shown in fig. 10, the first memory chip 110 after plastic encapsulation is attached to the die attach film 150, and the first plastic encapsulation layer 140 is cut at the position corresponding to the plurality of cutting traces 111 to form a cutting street 161, so that the plurality of second memory chips 120 stacked in sequence form a plurality of independent second memory chip sets 160. When the first molding compound layer 140 is cut, the cutting path 161 is stopped from the surface of the first memory chip 110 facing the second memory chip 120.
S150, cutting the first memory chip along the plurality of cutting marks to form a plurality of independent memory stacking modules.
Illustratively, as shown in fig. 11, the patch film 150 is stretched under a predetermined low temperature condition, so that the plurality of cutting traces 111 (i.e., laser damage layers) in the first memory chip 110 are enlarged under the stretching force, and finally the separation of the first memory chip 110 is achieved, thereby forming a plurality of independent memory stack modules 210 as shown in fig. 12, wherein each independent memory stack module 210 includes the first memory chip 110 and a plurality of second memory chips 120. It should be noted that stretching the patch film is feasible at room temperature or within a certain range below room temperature, as long as the state strength of the patch film itself is not affected by the temperature being not so high.
And S160, carrying out hot-press bonding on the plurality of memory stacking modules and a buffer chip, wherein the buffer chip is provided with a second conductive through hole.
Illustratively, as shown in fig. 13, the buffer chip 130 is provided with a plurality of second conductive vias 131, and a surface of the buffer chip 130 facing the memory stack module 210 is provided with a fourth passivation layer 132 and a fourth metal pad 133. The plurality of memory stack modules 210 and the buffer chip 130 are thermally and pressure bonded, specifically, the first bump 190 and the fourth metal pad 133 are thermally and pressure bonded. That is, the plurality of memory stack modules 210 are attached on the buffer chip 130 through a thermocompression bonding process. The plurality of first bumps 190 are electrically connected to the plurality of second conductive vias 131 through the plurality of fourth pads 133 on the buffer chip 130, so as to realize signal propagation between the memory stack module 210 and the substrate 130.
It should be noted that, when the plurality of memory stack modules 210 and the fourth metal pads 132 are bonded by hot pressing, a pre-soldering process may be performed to pre-position the memory stack modules 210 relative to the buffer chip 130 for facilitating a subsequent packaging process. The first bumps 190 or the fourth pads 133 may be coated with solder, and the relative position of the memory stack module 210 on the buffer chip 130 is fixed in advance through the hot pressing of the hot pressing process, but the pre-soldering process may also be performed by melting the solder on the first bumps 190 and the fourth pads 132 with a soldering pen to fix the relative position of the memory stack module 210 on the buffer chip 130 in advance.
It should be further noted that the solder may be a copper-zinc alloy material, a silver-copper alloy material, a tin-lead alloy material, or the like, and is capable of being melted in a protective gas atmosphere at a preset temperature, and the solder that is convenient for the bump 190 or the fourth pad 133 to dip may be the solder described in this embodiment, which is not limited herein.
It should be noted that, in this embodiment, the positions of the fourth pads 133 correspond to the positions of the first bumps 190 and have the same number, if the buffer chip 130 is not a dedicated buffer chip adapted to the second memory chip 120 and the first memory chip 110, but the buffer chip in the chip package manufacturing process may be a general-purpose buffer chip, the number of the fourth pads 133 on the buffer chip 130 may be greater than the number of the first bumps 190 on the second memory chip 120, as long as it can be ensured that the first bumps 190 on the second memory chip 120 have the corresponding fourth pads 133 connected in a matching manner therewith, and that an adequate information transmission channel between the second memory chip 120 and the buffer chip 130 is ensured, the number of the first bumps 190 is determined according to the number of the information transmission channels between the second memory chip 120 and the buffer chip 130, which is intended to ensure that the second memory chip 120 and the buffer chip 130 have an adequate information transmission channel, the operation efficiency of the second memory chip 120 is ensured. In this embodiment, the material of the fourth metal pad 133 may be a metal copper material, and the material of the first bump 190 may be a copper-tin material, which is not specifically limited in this embodiment.
Note that, the plurality of memory stack modules may be thermocompression bonded to the substrate, that is, the plurality of memory stack modules may be stacked on the substrate.
S170, carrying out plastic package on the buffer chip and the memory stacking module to form a second plastic package layer.
Specifically, as shown in fig. 13, the buffer chip 130 and the memory stack module 210 are molded to form a second molding compound layer 220, and the second molding compound layer 220 wraps the buffer chip 130 and the memory stack module 210. The plastic packaging method may be vacuum lamination of the film layer or a conventional plastic packaging process, and this embodiment is not particularly limited.
And S180, cutting the second plastic packaging layer and the buffer chip to form an independent memory packaging structure.
Illustratively, before the dicing of the second molding compound layer and the buffer chip, the method further includes:
as shown in fig. 14, a second bump 134 is formed on a surface of the buffer chip 130 facing away from the memory stack module 210, and the second bump 134 corresponds to the second conductive via 131. In this embodiment, the second bump 134 may be a copper-tin bump.
After the second bumps 134 are formed, the second molding compound layer 220 and the buffer chip 130 are cut to form the individual memory package structure shown in fig. 15.
As shown in fig. 15, another aspect of the present invention provides a high-bandwidth memory package structure 100, where the package structure 100 is packaged by the packaging method S100 described above, and the package structure 100 includes a buffer chip 130, a first memory chip 110, a plurality of second memory chips 120, a first molding compound layer 140, and a second molding compound layer 220.
The plurality of second memory chips 120 are sequentially stacked on the buffer chip 130, wherein every two adjacent layers of the second memory chips 120 are in hybrid bonding connection, and the buffer chip 130 is in thermal compression bonding connection with the bottom layer of the second memory chips.
The first memory chip 110 is disposed on a side of the plurality of second memory chips 120 facing away from the buffer chip 130, and the first memory chip 110 is connected with the top second memory chip by hybrid bonding.
The first plastic package layer 140 is disposed on the first memory chip 110 and covers the plurality of second memory chips 120, that is, the first plastic package layer 140 only covers two sides of the plurality of second memory chips 120 stacked. The second molding compound layer 220 is disposed on the buffer chip 130 and sleeved outside the first molding compound layer 140 and the first memory chip 110. And, the second memory chip 120 is provided with a first conductive via 121, and the buffer chip 130 is provided with a second conductive via 131 corresponding to and electrically connected to the first conductive via 121.
Illustratively, as shown in fig. 15, a surface of the second memory chip 120 facing the first memory chip 110 is provided with a first passivation layer 122 and a first metal pad 123, a surface of the second memory chip 120 facing away from the first memory chip 110 is provided with a second passivation layer 124 and a second metal pad 125, and a surface of the first memory chip 110 facing the second memory chip 120 is provided with a third passivation layer 112 and a third metal pad 113. In this embodiment, the materials of the first passivation layer 122, the second passivation layer 124 and the third passivation layer 112 may be silicon dioxide materials, and the first metal pad 123, the second metal pad 125 and the third metal pad 113 may be copper pads.
Wherein the first passivation layer 122 of one of the two adjacent layers of the second memory chips 120 is bonded to the second passivation layer 124 of the other one of the two adjacent layers of the second memory chips 120, and the first metal pad 123 of one of the two adjacent layers of the second memory chips 120 is bonded to the second metal pad 125 of the other one of the two adjacent layers of the second memory chips 120.
The third passivation layer 112 of the first memory chip 110 is in bonding connection with the first passivation layer 122 of the second memory chip 120, and the third metal pad 113 of the first memory chip 110 is in bonding connection with the first metal pad 123 of the second memory chip 120.
Illustratively, as shown in fig. 15, a surface of the buffer chip 130 facing the second memory chip 120 is provided with a fourth passivation layer 132 and a fourth metal pad 133, and the second passivation layer 124 of the second memory chip 120 facing the buffer chip 130 is provided with a first bump 190 and a non-conductive adhesive film 200. Further preferably, a dielectric layer 170 is disposed on the second passivation layer 124 of the second memory chip 120 facing the buffer chip 130, a redistribution layer 180 is disposed on the dielectric layer 170, and a first bump 190 and a non-conductive adhesive film 200 are disposed on the redistribution layer 180. That is, the dielectric layer 170 and the redistribution layer 180 are disposed on the second passivation layer 124 of the second memory chip 120 facing the buffer chip 130, which is optional, and the embodiment is not limited in particular. The fourth metal pad 133 is thermally compression-bonded to the first bump 190 of the buffer chip 130.
In this embodiment, the material of the dielectric layer 170 may be Polyimide (PI), Polybenzoxazole (PBO), or the like. The material of the fourth passivation layer 132 may be a silicon oxide material, and the fourth metal pad 133 may be a copper pad. The material of the redistribution layer 180 is typically titanium and copper. The first bump 190 may be a copper-tin bump.
Illustratively, as shown in fig. 15, a surface of the buffer chip 130 facing away from the second memory chip 120 is provided with a second bump 134, wherein the second bump 134 corresponds to and is electrically connected to the second conductive via 131. In this embodiment, the second bump 134 may be a copper-tin bump.
According to the high-broadband memory packaging structure, the plurality of second memory chips are sequentially stacked on the buffer chip, wherein every two adjacent layers of the second memory chips are in hybrid bonding connection, and the buffer chip is in hot-press bonding connection with the bottom layer of the second memory chips. The first memory chip is arranged on one side, away from the buffer chip, of the second memory chips, the first memory chip is connected with the second memory chip on the top layer through hybrid bonding, a first conductive through hole is formed in the second memory chip, and the buffer chip is provided with a second conductive through hole corresponding to and electrically connected with the first conductive through hole. The packaging structure can realize smaller spacing (below 10 um), increase the number of vertical interconnections, increase the number of data channels and improve data throughput, and meanwhile, because the plurality of second memory chips and the first memory chip and the second memory chip are mixed and bonded, the bonding height is reduced, the layer number of the memory chips can be increased, and the capacity is increased.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. A method of high bandwidth memory encapsulation, the method comprising:
forming a plurality of cutting marks at preset positions in the first memory chip;
sequentially mixing, bonding and stacking a plurality of second memory chips with first conductive through holes on the first memory chip between two adjacent cutting marks;
plastically packaging the first memory chip and the plurality of second memory chips to form a first plastic packaging layer;
adhering the first memory chip subjected to plastic packaging to a film, and cutting the first plastic packaging layer at positions corresponding to the plurality of cutting marks to form a plurality of independent second memory chip groups;
cutting the first memory chip along the plurality of cutting marks to form a plurality of independent memory stacking modules;
carrying out hot-press bonding on the plurality of memory stacking modules and a buffer chip, wherein the buffer chip is provided with a second conductive through hole;
plastically packaging the buffer chip and the memory stacking module to form a second plastic packaging layer;
and cutting the second plastic packaging layer and the buffer chip to form an independent memory packaging structure.
2. The packaging method according to claim 1, wherein a surface of the second memory chip facing the first memory chip is provided with a first passivation layer and a first metal pad, a surface of the second memory chip facing away from the first memory chip is provided with a second passivation layer and a second metal pad, and a surface of the first memory chip facing the second memory chip is provided with a third passivation layer and a third metal pad;
the sequentially hybrid bonding and stacking a plurality of second memory chips having conductive vias on the first memory chip comprises:
bonding the first passivation layer of the second memory chip at the bottom layer with the third passivation layer of the first memory chip, and bonding the first metal pad on the second memory chip at the bottom layer with the third metal pad on the first memory chip;
sequentially and mixedly bonding and stacking the rest layers of second memory chips on the bottom layer of second memory chips, wherein the first passivation layer and the second passivation layer in every two adjacent layers of second memory chips are bonded; and the first metal bonding pad and the second metal bonding pad in every two adjacent layers of the second memory chips are bonded.
3. The packaging method according to claim 1, wherein before the plastically packaged first memory chip is attached to a die attach film, the method further comprises:
forming a first bump on the surface of the second memory chip on the top layer and the surface of the first plastic packaging layer, which is far away from the first memory chip, wherein the first bump corresponds to the second conductive through hole;
and forming a non-conductive adhesive film on the first salient points.
4. The method of packaging of claim 3, wherein prior to forming the first bump, the method further comprises:
forming a dielectric layer on the surface, away from the first memory chip, of the second memory chip and the first plastic packaging layer on the top layer;
and forming a rewiring layer on the dielectric layer.
5. The packaging method according to claim 3, wherein a surface of the buffer chip facing the memory stack module is provided with a fourth passivation layer and a fourth metal pad;
the thermocompression bonding the plurality of memory stack modules and the buffer chip includes:
and carrying out hot-pressing bonding on the first salient point and the fourth metal pad.
6. The method of packaging according to claim 1, wherein forming a plurality of scribe lines at predetermined locations within the first memory chip comprises:
and forming a plurality of cutting marks in the preset position of the first memory chip by a laser invisible cutting method.
7. The method of packaging of claim 6, wherein the dicing the first memory chip to form a plurality of individual memory stack modules comprises:
and stretching the film under a preset low-temperature condition to enlarge a plurality of cutting marks in the first memory chip so as to form a plurality of independent memory stacking modules.
8. The packaging method according to any one of claims 1 to 7, wherein before the dicing of the second molding compound and the buffer chip, the method further comprises:
and forming a second bump on the surface of the buffer chip departing from the memory stacking module, wherein the second bump corresponds to the second conductive through hole.
9. The packaging method according to any one of claims 1 to 7, wherein the first conductive via and the second conductive via are both through silicon vias.
10. A high bandwidth memory package structure, characterized by being manufactured by the packaging method of any one of claims 1 to 9.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111496879.XA CN114203569A (en) | 2021-12-08 | 2021-12-08 | High-broadband memory packaging method and packaging structure |
| PCT/CN2022/137244 WO2023104093A1 (en) | 2021-12-08 | 2022-12-07 | Packaging method and packaging structure of multi-layer stacked high-bandwidth memory |
| US18/680,321 US20240321853A1 (en) | 2021-12-08 | 2024-05-31 | Packaging method and packaging structure of multi-layer stacked high-bandwidth memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111496879.XA CN114203569A (en) | 2021-12-08 | 2021-12-08 | High-broadband memory packaging method and packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114203569A true CN114203569A (en) | 2022-03-18 |
Family
ID=80651497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111496879.XA Pending CN114203569A (en) | 2021-12-08 | 2021-12-08 | High-broadband memory packaging method and packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114203569A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023104093A1 (en) * | 2021-12-08 | 2023-06-15 | Tongfu Microelectronics Co., Ltd. | Packaging method and packaging structure of multi-layer stacked high-bandwidth memory |
| CN119364776A (en) * | 2024-12-20 | 2025-01-24 | 合肥沛顿存储科技有限公司 | Multi-chip stacking packaging structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102224584A (en) * | 2008-11-25 | 2011-10-19 | 住友电木株式会社 | Electronic component package and electronic component package manufacturing method |
| US20200135698A1 (en) * | 2018-10-30 | 2020-04-30 | Samsung Electronics Co., Ltd. | Die stack structure, semiconductor package having the same and method of manufacturing the same |
| CN113628984A (en) * | 2021-08-26 | 2021-11-09 | 西安紫光国芯半导体有限公司 | 3DIC chip and preparation method thereof |
-
2021
- 2021-12-08 CN CN202111496879.XA patent/CN114203569A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102224584A (en) * | 2008-11-25 | 2011-10-19 | 住友电木株式会社 | Electronic component package and electronic component package manufacturing method |
| US20200135698A1 (en) * | 2018-10-30 | 2020-04-30 | Samsung Electronics Co., Ltd. | Die stack structure, semiconductor package having the same and method of manufacturing the same |
| CN113628984A (en) * | 2021-08-26 | 2021-11-09 | 西安紫光国芯半导体有限公司 | 3DIC chip and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023104093A1 (en) * | 2021-12-08 | 2023-06-15 | Tongfu Microelectronics Co., Ltd. | Packaging method and packaging structure of multi-layer stacked high-bandwidth memory |
| CN119364776A (en) * | 2024-12-20 | 2025-01-24 | 合肥沛顿存储科技有限公司 | Multi-chip stacking packaging structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20240379614A1 (en) | Multi-level stacking of wafers and chips | |
| US20240379602A1 (en) | Methods of forming integrated circuit packages | |
| CN114171506A (en) | Multilayer stacked memory packaging structure and packaging method | |
| US10593647B2 (en) | Package structure and manufacturing method thereof | |
| US9343429B2 (en) | Semiconductor device and method of forming double-sided through vias in saw streets | |
| US8343803B2 (en) | Lightweight and compact through-silicon via stack package with excellent electrical connections and method for manufacturing the same | |
| US9953907B2 (en) | PoP device | |
| US20070216008A1 (en) | Low profile semiconductor package-on-package | |
| US12046573B2 (en) | Semiconductor die, a semiconductor die stack, and a semiconductor module | |
| US20230343737A1 (en) | Semiconductor packages and methods of forming the same | |
| CN114171505A (en) | Multi-layer stacked high-broadband memory packaging structure and packaging method | |
| CN114464542B (en) | Packaging method and packaging structure of multilayer stacked high-broadband memory | |
| US20240321821A1 (en) | Packaging method and packaging structure of multi-layer stacked memory | |
| CN114203569A (en) | High-broadband memory packaging method and packaging structure | |
| US10354978B1 (en) | Stacked package including exterior conductive element and a manufacturing method of the same | |
| CN113990815A (en) | Silicon-based micro-module plastic package structure and preparation method thereof | |
| CN114203564B (en) | A packaging method and packaging structure for a multi-layer stacked high-bandwidth memory | |
| US20240321853A1 (en) | Packaging method and packaging structure of multi-layer stacked high-bandwidth memory | |
| CN114203565B (en) | Multi-layer stacked high-bandwidth memory packaging method and packaging structure | |
| US20240413026A1 (en) | Semiconductor package and method of manufacturing the semiconductor package | |
| US12170252B2 (en) | Electronic substrate stacking | |
| CN117316907A (en) | A wafer-level non-TSV 3D stacked packaging structure and method | |
| CN114203562A (en) | Packaging method and packaging structure of multilayer stacked high-bandwidth memory | |
| US20250266398A1 (en) | Semiconductor package and method of manufacturing the semiconductor package | |
| US20240153919A1 (en) | Semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |