CN114203557A - Semiconductor device manufacturing method, semiconductor device manufacturing apparatus and storage medium - Google Patents
Semiconductor device manufacturing method, semiconductor device manufacturing apparatus and storage medium Download PDFInfo
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- CN114203557A CN114203557A CN202111398314.8A CN202111398314A CN114203557A CN 114203557 A CN114203557 A CN 114203557A CN 202111398314 A CN202111398314 A CN 202111398314A CN 114203557 A CN114203557 A CN 114203557A
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Abstract
本申请公开了一种半导体器件制作方法、装置和存储介质，涉及半导体技术领域，所述方法包括：在单晶基底表面沉积绝缘介质层；在所述绝缘介质层的上层涂覆光刻胶；在涂覆所述光刻胶之后在所述绝缘介质层上进行光刻和刻蚀，得到随着深度增加宽度减小的开口；去除光刻胶，并在所述开口中填充金属。解决了现有技术中由于开口尺寸较小而导致的金属填充后的半导体器件的形貌较差会出现空洞的问题，达到了即使开口尺寸较小也可以较好的填充金属的效果。The present application discloses a semiconductor device fabrication method, device and storage medium, and relates to the technical field of semiconductors. The method includes: depositing an insulating medium layer on the surface of a single crystal substrate; coating a photoresist on the upper layer of the insulating medium layer; After coating the photoresist, photolithography and etching are performed on the insulating medium layer to obtain an opening whose width decreases as the depth increases; the photoresist is removed, and metal is filled in the opening. The problem in the prior art that the shape of the metal-filled semiconductor device is poor due to the small opening size is solved, and the effect of better metal filling is achieved even if the opening size is small.
Description
Technical Field
The invention relates to a semiconductor device manufacturing method, a semiconductor device manufacturing device and a storage medium, and belongs to the technical field of semiconductors.
Background
In the existing scheme, when a semiconductor device is manufactured, if the size of a filling metal is small, a cavity can appear in the poor appearance of the semiconductor device after the metal filling.
Disclosure of Invention
The invention aims to provide a semiconductor device manufacturing method, a semiconductor device manufacturing device and a storage medium, which are used for solving the problems in the prior art.
In order to achieve the purpose, the invention provides the following technical scheme:
according to a first aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, the method including:
depositing an insulating medium layer on the surface of the single crystal substrate;
coating photoresist on the upper layer of the insulating medium layer;
after the photoresist is coated, photoetching and etching are carried out on the insulating medium layer, so that an opening with the width reduced along with the increase of the depth is obtained;
and removing the photoresist, and filling metal in the opening.
Optionally, the opening is stepped and includes n levels, the width of the ith level is greater than the width of the (i + 1) th level, i is greater than 0 and less than or equal to n-1, n is an integer greater than or equal to 2, and the 1 st level is the uppermost layer.
Optionally, the heights of the steps of each stage are the same.
Optionally, the height of the insulating medium layer is h, and the height of each step is h/n.
Alternatively, the width of the ith stage, i +1 th stage, is equal to the width of the (i + 1) th stage, i +2 th stage.
Optionally, the insulating dielectric layer is made of SiO2And SiN.
Optionally, the thickness of the insulating dielectric layer is not more than 2 μm.
Optionally, the performing photolithography and etching on the insulating dielectric layer after coating the photoresist to obtain an opening with a width decreasing with an increase in depth includes:
and photoetching and etching the insulating medium layer after coating the photoresist to obtain an opening with the width decreasing along with the depth increase.
In a second aspect, there is provided a semiconductor device manufacturing apparatus, the apparatus comprising a memory and a processor, the memory having at least one program instruction stored therein, the processor implementing the method according to the first aspect by loading and executing the at least one program instruction.
In a third aspect, there is provided a computer storage medium having stored therein at least one program instruction which is loaded and executed by a processor to implement the method of the first aspect.
When the insulating medium layer is etched, the opening with the width reduced along with the increase of the depth is obtained, and then after the photoresist is removed, metal is filled in the opening, so that the problem that in the prior art, due to the fact that the size of the opening is small, the appearance of a semiconductor device after metal filling is poor, and a cavity can be formed is solved, and the effect of filling metal well even if the size of the opening is small is achieved.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
FIG. 1 is a method flow diagram of a method of fabricating a semiconductor device in accordance with the present invention;
FIG. 2 is a schematic structural diagram illustrating a deposited insulating dielectric layer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure after application of a photoresist according to one embodiment of the present invention;
FIGS. 4 and 5 are schematic structural diagrams after photolithography and etching, respectively, according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a semiconductor device obtained after removing the photoresist according to an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown, where as shown in fig. 1, the method includes:
the material of the single crystal substrate may be single crystal silicon, and in actual implementation, the single crystal substrate may be selected according to actual growth requirements, which is not limited in the present application.
The insulating medium layer may be made of SiO2And SiN, and, in practical implementations, the thickness of the insulating dielectric layer does not exceed 2 μm. Referring to fig. 2, a schematic diagram of the structure after depositing the insulating dielectric layer is shown.
102, coating photoresist on the upper layer of the insulating medium layer;
referring to fig. 3, a schematic diagram of the structure after coating the photoresist is shown.
103, after the photoresist is coated, photoetching and etching are carried out on the insulating medium layer to obtain an opening with the width decreasing along with the increase of the depth;
the formed opening is bowl-shaped, and the width is continuously reduced. Specifically, the opening is in a step shape and comprises n levels, the width of the ith level is larger than that of the (i + 1) th level, i is larger than 0 and is not larger than n-1, n is an integer larger than or equal to 2, and the 1 st level is the uppermost layer.
Optionally, the heights of the steps of each stage are the same. The height of the insulating medium layer is h, and the height of each step is h/n. In practical implementation, the height of each step may be a preset value, the height of the insulating medium layer is h, and the number of steps n required to be formed may be determined according to the height of the insulating medium layer and the preset value, that is, n is h/the preset value. The preset value may be a default value or a custom value, which is not limited herein.
In addition, the widths of the steps of each stage may be decreased by the same width, that is, the width of the ith stage — the width of the (i + 1) th stage — the width of the (i + 2) th stage. Please refer to fig. 4 and 5, which show the structure of the present application after photolithography and etching.
In practical implementation, the photoresist is coated, then photoetching is carried out, and etching is carried out on the insulating medium layer, so that the opening with the width reduced along with the depth increase is obtained.
And 104, removing the photoresist, and filling metal in the opening.
Please refer to fig. 6, which shows a schematic structure diagram after filling metal.
In summary, by performing photolithography and etching on the insulating dielectric layer, an opening with a width decreasing with increasing depth is obtained, and then metal is filled in the opening after the photoresist is removed, so that the problem that a semiconductor device filled with metal has poor appearance and a blank space due to small opening size in the prior art is solved, and the effect of filling metal well even if the opening size is small is achieved.
The present application also provides a semiconductor device fabrication apparatus comprising a memory having at least one program instruction stored therein and a processor that implements the method described above by loading and executing the at least one program instruction.
The present application also provides a computer storage medium having stored therein at least one program instruction, which is loaded and executed by a processor to implement the method as described above.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method of fabricating a semiconductor device, the method comprising:
depositing an insulating medium layer on the surface of the single crystal substrate;
coating photoresist on the upper layer of the insulating medium layer;
after the photoresist is coated, photoetching and etching are carried out on the insulating medium layer, so that an opening with the width reduced along with the increase of the depth is obtained;
and removing the photoresist, and filling metal in the opening.
2. The method of claim 1, wherein the opening is stepped and includes n stages, the width of the i-th stage is greater than the width of the i + 1-th stage, 0 < i ≦ n-1, n is an integer greater than or equal to 2, and the 1-th stage is the uppermost stage.
3. The method of claim 2, wherein the steps are of the same height.
4. The method of claim 2, wherein the height of the insulating dielectric layer is h, and the height of each step is h/n.
5. The method of claim 2, wherein the width of the ith stage-the width of the (i + 1) th stage-the width of the (i + 2) th stage.
6. The method according to any one of claims 1 to 5, wherein the material of the insulating dielectric layer is SiO2And SiN.
7. A method according to any one of claims 1 to 5, wherein the thickness of the dielectric layer is not more than 2 μm.
8. The method of any of claims 1 to 5, wherein said performing photolithography and etching on said insulating dielectric layer after coating said photoresist to obtain an opening with decreasing width as depth increases comprises:
and photoetching and etching the insulating medium layer after coating the photoresist to obtain an opening with the width decreasing along with the depth increase.
9. A semiconductor device manufacturing apparatus, comprising a memory having at least one program instruction stored therein and a processor, wherein the processor implements the method of any one of claims 1 to 8 by loading and executing the at least one program instruction.
10. A computer storage medium having stored therein at least one program instruction which is loaded and executed by a processor to implement the method of any one of claims 1 to 8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111398314.8A CN114203557A (en) | 2021-11-23 | 2021-11-23 | Semiconductor device manufacturing method, semiconductor device manufacturing apparatus and storage medium |
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| CN202111398314.8A CN114203557A (en) | 2021-11-23 | 2021-11-23 | Semiconductor device manufacturing method, semiconductor device manufacturing apparatus and storage medium |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6200906B1 (en) * | 1998-12-17 | 2001-03-13 | Micron Technology, Inc. | Stepped photoresist profile and opening formed using the profile |
| US20020058370A1 (en) * | 2000-08-31 | 2002-05-16 | Young-Mo Lee | Method for forming metal wire interconnection in semiconductor devices using dual damascene process |
| US20030020180A1 (en) * | 2001-07-24 | 2003-01-30 | Ahn Kie Y. | Copper technology for ULSI metallization |
| CN101996939A (en) * | 2009-08-26 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for producing metal plug |
| US20150262873A1 (en) * | 2014-03-13 | 2015-09-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device and Method |
| CN105845668A (en) * | 2015-01-17 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | MIM capacitor structure and making method thereof |
| US20160276262A1 (en) * | 2015-03-17 | 2016-09-22 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing semiconductor device |
-
2021
- 2021-11-23 CN CN202111398314.8A patent/CN114203557A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6200906B1 (en) * | 1998-12-17 | 2001-03-13 | Micron Technology, Inc. | Stepped photoresist profile and opening formed using the profile |
| US20020058370A1 (en) * | 2000-08-31 | 2002-05-16 | Young-Mo Lee | Method for forming metal wire interconnection in semiconductor devices using dual damascene process |
| US20030020180A1 (en) * | 2001-07-24 | 2003-01-30 | Ahn Kie Y. | Copper technology for ULSI metallization |
| CN101996939A (en) * | 2009-08-26 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for producing metal plug |
| US20150262873A1 (en) * | 2014-03-13 | 2015-09-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device and Method |
| CN105845668A (en) * | 2015-01-17 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | MIM capacitor structure and making method thereof |
| US20160276262A1 (en) * | 2015-03-17 | 2016-09-22 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing semiconductor device |
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