CN114203250A - Data storage method and data reading method of solid-state memory and solid-state memory - Google Patents
Data storage method and data reading method of solid-state memory and solid-state memory Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G06—COMPUTING OR CALCULATING; COUNTING
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
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Abstract
The invention provides a data storage method and a data reading method of a solid-state memory and the solid-state memory, wherein the data storage method comprises the following steps: performing error correction code coding on data to be stored by using an LDPC code with a target check matrix, wherein the target check matrix at least comprises a core sub-matrix and a sparse sub-matrix; storing encoded data generated according to the core sub-matrix encoding and conventional check bits in a preset conventional storage area; and storing the redundant check bits generated according to the sparse submatrix coding in a preset redundant storage area. When data is read, reading the coded data, the conventional check bit and the corresponding redundancy check bit; and splicing the encoded data, the conventional check bits and the redundant check bits to finish decoding. The invention reduces the encoding complexity, effectively prolongs the service life of the solid-state memory by generating the redundant check bit, simultaneously provides an error correcting code solution when reading data, and improves the utilization rate of the storage space and the writing and reading speed.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to a data storage method and a data reading method of a solid-state memory and the solid-state memory.
Background
More and more high-capacity flash memories currently adopt 3D NAND technology. The new memories such as 3D QLC (each unit stores 4-bit information), PLC (each unit stores 5-bit information) and the like generally have the problem that the original bit error rate (RBER) rises rapidly along with the cycle number, which results in that the advantage of the unit bit cost is offset by the severely shortened life. Reducing the code rate of the ECC is a possible solution, and compared with the current mainstream LDPC with a length of 4K + (the length exceeds 4 kbytes), an error correction gain of about 50% can be obtained by increasing the coding length by about 3%. However, due to the size limitation of word line, the free space of each page is very limited, even all encoded bits cannot be stored, and the bits of the super-long part must be punctured to match the size of the physical page. Therefore, on the premise of not increasing the size of the word, the coding with lower code rate is realized, and only other storage spaces are borrowed.
In a conventional ECC scheme, referring to fig. 1(a) -1 (c), fig. 1(a) shows a storage structure of a physical page, which is divided into two parts, a data area and a spare area, storing user data + metadata and parity bits, respectively. This way only one read operation is needed to read one ECC encoded frame, which is fast. However, since the size of the spare area is very small, the equivalent code rate of the ECC is usually as high as about 0.9. In addition, with the introduction of new technologies such as open channel technology and compression technology, the bit width of matadata tends to increase gradually, which further reduces the amount of spare area that is limited, and further causes the ECC equivalent code rate of the conventional scheme to gradually increase, the error correction capability to synchronously decrease, and finally the service life of the SSD to be shortened. If the conventional ECC scheme is used, the data structure in the physical page is as shown in fig. 1(b), and if the ECC with lower equivalent low code rate is used, the data area will inevitably exceed the size of the spare area after being encoded, as shown in fig. 1(c), where CBs represents check bits and ECBs represents extra-long check bits.
In the prior art, the storage of the super-long part is generally carried out in the following two ways.
Cross page mode: the very long part is stored directly to the head of the next logical page, so each logical page spans 2 physical pages. In this way, reading one logical page at a time triggers 2 times of reading operations of the physical page, and the time delay is too large. In addition, this approach also requires recording the offset value of each logical page start position, which increases the complexity of the FTL.
PG decorupling mode: the physical page is divided into a data area and an ECC area, wherein the data area is used for storing an uncoded data frame, and the ECC area is only used for storing parity bits obtained by coding. This approach still requires reading 2 physical pages at a time, and the data area does not fully utilize the spare area to store part of parity bits, resulting in waste of storage space and reduced flexibility of ECC policy.
Disclosure of Invention
In view of the above problems, the present invention has been made to provide a data storage method, a data reading method, and a solid-state memory of a solid-state memory that overcome or at least partially solve the above problems.
In one aspect of the present invention, a data storage method of a solid-state memory is provided, the method including:
performing error correction code coding on data to be stored by using an LDPC code with a target check matrix, wherein the target check matrix at least comprises a core sub-matrix and a sparse sub-matrix;
the core sub-matrix is used for generating encoded data and conventional check bits, and the sparse sub-matrix is used for generating redundant check bits exceeding the data length of the conventional check bits;
storing encoded data generated according to the core sub-matrix encoding and conventional check bits in a preset conventional storage area;
and storing the redundant check bits generated according to the sparse submatrix coding in a preset redundant storage area.
Further, the method further comprises:
the solid-state memory storage area is classified to divide the storage area into a regular storage area and a redundant storage area, wherein the regular storage area is used for storing the encoded data and the regular check bits, and the redundant storage area is used for storing the redundant check bits.
Further, the classifying the solid-state memory storage area comprises:
the physical addresses of the memory cells are classified to divide the memory cells into a regular memory area and a redundant memory area.
Further, the redundant storage areas are distributed in the preset positions of the storage units in a centralized mode or are uniformly distributed in the storage units.
Further, the classifying the solid-state memory storage area comprises:
and classifying the physical addresses of the memory chips so as to divide the memory chips into conventional memory chips and redundant memory chips, wherein the redundant memory areas are distributed in a centralized manner in the designated memory units of the redundant memory chips.
Further, the target check matrix further includes a zero matrix and a unit diagonal matrix, and the target check matrix has the following structure:
the core sub-matrix and the zero matrix have the same row number, the core sub-matrix and the sparse sub-matrix have the same column number, and the sparse sub-matrix and the unit diagonal matrix have the same row number.
Further, the method further comprises:
after storing the data in the corresponding storage area, recording the address correspondence between the storage addresses of the encoded data and the regular check bits and the storage addresses of the corresponding redundant check bits.
In still another aspect of the present invention, there is provided a data reading method of a solid-state memory, for reading data stored by the data storage method of the solid-state memory, the method including:
reading the coded data, the conventional check bits and the redundancy check bits corresponding to the coded data and the conventional check bits;
and splicing the encoded data, the conventional check bits and the redundant check bits, and decoding the spliced data by using the error correction code.
Further, the reading the encoded data, the normal check bits, and the redundancy check bits corresponding to the encoded data and the normal check bits includes:
searching an address corresponding relation according to the data reading address to obtain a storage address of a redundancy check bit corresponding to the data to be read;
reading the redundancy check bits according to the acquired storage address, and caching the acquired redundancy check bits by taking the data reading address as an index;
and when the coded data and the conventional check bits in the data reading address are read, acquiring corresponding redundancy check bits from the buffer data according to the data reading address.
In still another aspect of the present invention, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the data storage method of the solid-state memory or the steps of the data reading method of the solid-state memory as described above.
In yet another aspect of the present invention, there is also provided a solid-state memory including a storage controller including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the data storage method of the solid-state memory or the steps of the data reading method of the solid-state memory as above when executing the computer program.
The data storage method, the data reading method and the solid-state memory of the solid-state memory provided by the embodiment of the invention can simply and quickly generate the redundancy check bits, reduce the coding complexity and effectively prolong the service life of the solid-state memory through the generation of the redundancy check bits. Furthermore, the invention provides a more reasonable and efficient storage allocation strategy and a cache architecture for the ultra-long coded data, and simultaneously provides an error correction code solution for data reading, thereby improving the utilization rate of storage space and the writing and reading rates.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
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Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1(a) is a schematic diagram of a structure of a storage area in a physical page;
FIG. 1(b) is a diagram illustrating a data structure in a physical page in a conventional ECC scheme;
FIG. 1(c) is a diagram illustrating a data structure in a physical page in an ultra-long ECC scheme;
fig. 2 is a flowchart of a data storage method of a solid-state memory according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a data storage layout according to an embodiment of the present invention;
FIG. 4 is a flowchart of a data reading method of a solid-state memory according to an embodiment of the present invention;
fig. 5 is a schematic diagram of obtaining buffered redundancy check bits according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 2 schematically shows a flow chart of a data storage method of the solid-state memory according to an embodiment of the present invention. Referring to fig. 2, the data storage method of the solid-state memory according to the embodiment of the present invention specifically includes the following steps:
and S11, carrying out error correction code coding on the data to be stored by adopting an LDPC code with a target check matrix, wherein the target check matrix at least comprises a core sub-matrix and a sparse sub-matrix.
The core sub-matrix is used for generating encoded data and conventional check bits, and the sparse sub-matrix is used for generating redundant check bits exceeding the data length of the conventional check bits.
And S12, storing the coded data generated according to the core sub-matrix coding and the conventional check bits in a preset conventional storage area.
And S13, storing the redundant check bits generated according to the sparse submatrix coding in a preset redundant storage area.
In the embodiment of the invention, after the data is stored in the corresponding storage area, the record coding data and the address corresponding relation between the storage address of the conventional check bit and the storage address of the corresponding redundancy check bit are stored, so that the storage address of the redundancy check bit corresponding to the data to be read can be found quickly in the data reading process.
In the embodiment of the invention, the storage area of the solid-state memory is classified in advance to divide the storage area into a regular storage area and a redundant storage area, wherein the regular storage area is used for storing encoded data and regular check bits, and the redundant storage area is used for storing redundant check bits.
Specifically, the classification of the storage area of the solid-state memory may be a classification of a physical address of a memory chip or a physical address of a memory unit. Wherein, the storage unit can be selected as a unit of physical block.
In the data storage method of the solid-state memory according to the embodiment of the present invention, first, physical addresses are divided into two types in the layout of data storage: regular memory area (Regular area) and Redundant memory area (Redundant area). Wherein, Regular ECC encoded frames are stored in Regular area, but not uncoded data frames in PG decoding mode; the Redundant area stores the extra-long part after ECC coding, not all CBs.
The data stored in each physical page of the Regular area part can be directly decoded by an existing decoder, or can be jointly decoded after being spliced with the corresponding super-long part in the reduced area.
The occupation ratio of the reduce area can be flexibly adjusted, and the principle of configuration is to balance the service life of the medium and the storage cost of a unit bit. Especially for QLC media, SSD can be nearly doubled in lifetime if 5% capacity is configured to store the ECC extra-long portion.
Compared with the prior art, the data layout mode provided by the invention can sufficiently cope with the error correction capability of the conventional ECC coding frame when the wear rate of the memory is not high. The extra-long CBs in the Redundant area may not be read at this time. This reduces both the complexity and latency of reading data and the workload of the ECC decoder. In contrast, the PG decoding scheme has to read out the redundant CBs and the data frame from different physical addresses in any case, and the workload of the decoder is always the largest.
In addition, in the PG Decoupling mode, the data area only stores the uncoded data frame. Since data frames are all presented in fixed block lengths of 512, 1024, 2048 or 4096 bytes, and the size of the physical pages of the memory is slightly longer than an integer multiple of 512, one physical page cannot be filled up with data frames alone, thereby causing waste of storage space. The data storage method of the invention can fully utilize the wasted space and simultaneously improve the reliability of storage.
The data storage method of the solid-state memory provided by the embodiment of the invention can simply and quickly generate the redundancy check bits, reduces the coding complexity, and effectively prolongs the service life of the solid-state memory through the generation of the redundancy check bits. Furthermore, the invention also provides a more reasonable and efficient storage allocation strategy and cache architecture of the super-long coded data, and the utilization rate of the storage space is improved.
In a specific embodiment, the target check matrix includes a zero matrix and a unit diagonal matrix in addition to the core submatrix and the sparse submatrix, and the target check matrix has the following structure:
the core sub-matrix and the zero matrix have the same row number, the core sub-matrix and the sparse sub-matrix have the same column number, and the sparse sub-matrix and the unit diagonal matrix have the same row number.
Specifically, the target check matrix is composed of four parts, which are respectively called a core sub-matrix, a zero matrix, a sparse sub-matrix and a unit diagonal matrix.
The core submatrix is used for generating an encoded data frame of the regular storage area, and comprises encoded data and regular check bits.
The unit diagonal matrix and the sparse matrix have the same row number, and the redundant check bits of the redundant storage area can be generated by using a parity check method.
The low-density parity check code LDPC with the check matrix of the structure has the advantages that:
1) the redundant check bits ECBs are generated simply, and the coding complexity is reduced; meanwhile, as long as the core matrix is reasonably designed, the decoding performance of the LDPC code can be comparable to that of the LDPC code with the same code length and code rate specially and optimally designed.
2) Check matrixes with different redundancy lengths can be flexibly constructed by using the same core matrix. Because the design of the core matrix is difficult, if corresponding special check matrixes are designed for different redundancy lengths, the design is very difficult, and several sets of corresponding encoders are also needed to be configured, which undoubtedly greatly increases the chip cost. The technical scheme of the invention can meet the requirement only by constructing the sparse matrix with enough rows once and intercepting proper rows from top to bottom to match the length of CBs according to the requirement.
In one embodiment, the classification of the solid-state memory storage area may be: the physical addresses of the memory cells are classified to divide the memory cells into a regular memory area and a redundant memory area. The redundant storage areas are distributed at the tail of the storage unit in a centralized mode or are distributed in the storage unit uniformly.
One possible data storage layout is given in fig. 3. Fig. 3 is a layout form with blocks as units, and in each block, a certain proportion of pages may be configured as redundant pages for storing ECC super-long parts of the remaining regular pages in the block. The positions of the redundant pages can be uniformly distributed or intensively placed in the block.
Specifically, for example, when the redundant storage areas are distributed at the tail of the storage unit in a centralized manner, assuming that one block spans 128 sub-line words, the physical page pages on the last 4 word lines may be set as redundant pages. And when the regular page of the block is written, importing the redundancy check bit ECBs data corresponding to the block in the special ECC cache into a redundant page.
In fig. 3, PPN denotes a physical page in the normal storage area, and an invalid page in dark gray denotes that the data stored therein has failed. X1-X124 in the Redundant area store redundancy check bits ECBs corresponding to PPN X1-X124 of the regular area respectively. If a certain PPN in a regular area is marked as invalid, the corresponding check bits ECBs in the redundant area are also marked as invalid.
In a specific embodiment, the classifying the storage area of the solid-state memory may further be: and classifying the physical addresses of the memory chips so as to divide the memory chips into conventional memory chips and redundant memory chips, wherein the redundant memory areas are distributed in a centralized manner in the designated memory units of the redundant memory chips.
When the storage area of the solid-state memory is divided, the ultra-long part of data and the corresponding ECC coding frame are not stored in the same physical block. The super-long part can be centralized or distributed in other Die stored on the same chip, or some blocks stored on other chips, or even some special nonvolatile memories. The advantage of such a division is that the concurrent read-write capability of a plurality of channels of modern memory chips and memory controllers can be fully utilized, and the conventional ECC encoded frame and the ultra-long part are written in or read out in parallel, so that the read-write delay is reduced to the maximum extent.
Fig. 4 schematically shows a flowchart of a data reading method of the solid-state memory according to an embodiment of the present invention. Referring to fig. 4, the data reading method of the solid-state memory according to the embodiment of the present invention specifically includes the following steps:
and S21, reading the coded data, the normal check bits and the redundancy check bits corresponding to the coded data and the normal check bits.
The method comprises the steps that reading coded data and conventional check bits are stored in a conventional storage area, corresponding redundancy check bits are stored in a redundancy storage area, when data are read, the storage address of the redundancy check bit corresponding to data to be read can be quickly found according to the address corresponding relation between the storage address of the coded data and the conventional check bits which are stored and recorded during data writing and the storage address of the corresponding redundancy check bits, and the corresponding redundancy check bits are obtained.
And S22, splicing the coded data, the conventional check bits and the redundant check bits, and decoding the spliced data by using the error correction codes.
Specifically, the reading of the encoded data, the normal check bits, and the redundancy check bits corresponding to the encoded data and the normal check bits includes: searching an address corresponding relation according to the data reading address to obtain a storage address of a redundancy check bit corresponding to the data to be read; reading the redundancy check bits according to the acquired storage address, and caching the acquired redundancy check bits by taking the data reading address as an index; and when the coded data and the conventional check bits in the data reading address are read, acquiring corresponding redundancy check bits from the buffer data according to the data reading address.
In this embodiment, in order to improve the throughput of reading a file and reduce the problem of write amplification in the conventional Decoupling scheme, an element called an ECC cache is introduced, where the ECC cache includes two elements:
ECC SRAM component: for buffering a certain number of redundancy check bits ECBs.
ECC CAM (Content-addressable memory) component: the ECC SRAM module is used for storing mapping relations of physical addresses in each SRAM unit and in the memory in the ECC SRAM assembly.
Referring to FIG. 5, the present invention illustrates how ECBs for a physical page are obtained by the embodiment shown in FIG. 5. Firstly, reading a redundant area in the block data and caching the redundant area into an ECC SRAM component in ECC cache before reading the block data; then, when reading the data corresponding to the physical address A, finding the address in the SRAM from the CAM according to the address A, and using the ECB thereinAReading out; finally, the ECB is mixedAAnd splicing the data in the physical address A and sending the spliced data to an ECC decoder.
The invention provides a more reasonable and efficient distribution strategy and a cache architecture of the ultra-long coded data, provides a matched error correction code solution, and can improve the service life of the solid-state memory and the utilization rate of the storage space and the writing and reading rates.
Furthermore, an embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the data storage method of the solid-state memory or the steps of the data reading method of the solid-state memory as described above.
In addition, the solid-state memory includes a storage controller, the storage controller includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the data storage method of the solid-state memory or the steps of the data reading method of the solid-state memory when executing the program. Such as steps S11-S13 shown in fig. 2, or steps S21-S22 shown in fig. 4.
The data storage method, the data reading method and the solid-state memory of the solid-state memory provided by the embodiment of the invention can simply and quickly generate the redundancy check bits, reduce the coding complexity and effectively prolong the service life of the solid-state memory through the generation of the redundancy check bits. Furthermore, the invention provides a more reasonable and efficient storage allocation strategy and a cache architecture for the ultra-long coded data, and simultaneously provides an error correction code solution for data reading, thereby improving the utilization rate of storage space and the writing and reading rates.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, any of the claimed embodiments may be used in any combination.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (11)
1. A method of data storage in a solid state memory, the method comprising:
performing error correction code coding on data to be stored by using an LDPC code with a target check matrix, wherein the target check matrix at least comprises a core sub-matrix and a sparse sub-matrix;
the core sub-matrix is used for generating encoded data and conventional check bits, and the sparse sub-matrix is used for generating redundant check bits exceeding the data length of the conventional check bits;
storing encoded data generated according to the core sub-matrix encoding and conventional check bits in a preset conventional storage area;
and storing the redundant check bits generated according to the sparse submatrix coding in a preset redundant storage area.
2. The method of claim 1, further comprising:
the solid-state memory storage area is classified to divide the storage area into a regular storage area and a redundant storage area, wherein the regular storage area is used for storing the encoded data and the regular check bits, and the redundant storage area is used for storing the redundant check bits.
3. The method of claim 2, wherein the classifying the solid-state memory storage area comprises:
the physical addresses of the memory cells are classified to divide the memory cells into a regular memory area and a redundant memory area.
4. The method according to claim 3, wherein the redundant memory areas are distributed in a predetermined position of the memory unit in a centralized manner or uniformly distributed in the memory unit.
5. The method of claim 2, wherein the classifying the solid-state memory storage area comprises:
and classifying the physical addresses of the memory chips so as to divide the memory chips into conventional memory chips and redundant memory chips, wherein the redundant memory areas are distributed in a centralized manner in the designated memory units of the redundant memory chips.
6. The method of any one of claims 1-5, wherein the target check matrix further comprises a zero matrix and a unit diagonal matrix, and the target check matrix has the following structure:
the core sub-matrix and the zero matrix have the same row number, the core sub-matrix and the sparse sub-matrix have the same column number, and the sparse sub-matrix and the unit diagonal matrix have the same row number.
7. The method according to any one of claims 1-5, further comprising:
after storing the data in the corresponding storage area, recording the address correspondence between the storage addresses of the encoded data and the regular check bits and the storage addresses of the corresponding redundant check bits.
8. A method for reading data from a solid-state memory, the method being used for reading data stored by the method according to any of claims 1 to 7, the method further comprising:
reading the coded data, the conventional check bits and the redundancy check bits corresponding to the coded data and the conventional check bits;
and splicing the encoded data, the conventional check bits and the redundant check bits, and decoding the spliced data by using the error correction code.
9. The method of claim 8, wherein reading the encoded data, the regular check bits, and the redundancy check bits corresponding to the encoded data, the regular check bits comprises:
searching an address corresponding relation according to the data reading address to obtain a storage address of a redundancy check bit corresponding to the data to be read;
reading the redundancy check bits according to the acquired storage address, and caching the acquired redundancy check bits by taking the data reading address as an index;
and when the coded data and the conventional check bits in the data reading address are read, acquiring corresponding redundancy check bits from the buffer data according to the data reading address.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7 or the steps of the method according to any one of claims 8 to 9.
11. A solid-state memory comprising a memory controller, the memory controller comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method according to any one of claims 1 to 7 or the steps of the method according to any one of claims 8 to 9 when executing the computer program.
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